[PATCH] PCI: j721e: Add config guards for Cadence Host and Endpoint library APIs

[PATCH] PCI: j721e: Add config guards for Cadence Host and Endpoint library APIs

[Siddharth Vadapalli]

Commit under Fixes enabled loadable module support for the driver under
the assumption that it shall be the sole user of the Cadence Host and
Endpoint library APIs. This assumption guarantees that we won't end up
in a case where the driver is built-in and the library support is built
as a loadable module.

With the introduction of [1], this assumption is no longer valid. The
SG2042 driver could be built as a loadable module, implying that the
Cadence Host library is also selected as a loadable module. However, the
pci-j721e.c driver could be built-in as indicated by CONFIG_PCI_J721E=y
due to which the Cadence Endpoint library is built-in. Despite the
library drivers being built as specified by their respective consumers,
since the 'pci-j721e.c' driver has references to the Cadence Host
library APIs as well, we run into a build error as reported at [0].

Fix this by adding config guards as a temporary workaround. The proper
fix is to split the 'pci-j721e.c' driver into independent Host and
Endpoint drivers as aligned at [2].

Fixes: a2790bf81f0f ("PCI: j721e: Add support to build as a loadable module")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202511111705.MZ7ls8Hm-lkp@intel.com/
Cc: <stable@vger.kernel.org>
[0]: https://lore.kernel.org/r/202511111705.MZ7ls8Hm-lkp@intel.com/
[1]: commit 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver")
[2]: https://lore.kernel.org/r/37f6f8ce-12b2-44ee-a94c-f21b29c98821@app.fastmail.com/
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 43 +++++++++++++---------
 1 file changed, 26 insertions(+), 17 deletions(-)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 5bc5ab20aa6d..67c5e02afccf 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -628,10 +628,12 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 			gpiod_set_value_cansleep(gpiod, 1);
 		}
 
-		ret = cdns_pcie_host_setup(rc);
-		if (ret < 0) {
-			clk_disable_unprepare(pcie->refclk);
-			goto err_pcie_setup;
+		if (IS_ENABLED(CONFIG_PCI_J721E_HOST)) {
+			ret = cdns_pcie_host_setup(rc);
+			if (ret < 0) {
+				clk_disable_unprepare(pcie->refclk);
+				goto err_pcie_setup;
+			}
 		}
 
 		break;
@@ -642,9 +644,11 @@ static int j721e_pcie_probe(struct platform_device *pdev)
 			goto err_get_sync;
 		}
 
-		ret = cdns_pcie_ep_setup(ep);
-		if (ret < 0)
-			goto err_pcie_setup;
+		if (IS_ENABLED(CONFIG_PCI_J721E_EP)) {
+			ret = cdns_pcie_ep_setup(ep);
+			if (ret < 0)
+				goto err_pcie_setup;
+		}
 
 		break;
 	}
@@ -669,10 +673,11 @@ static void j721e_pcie_remove(struct platform_device *pdev)
 	struct cdns_pcie_ep *ep;
 	struct cdns_pcie_rc *rc;
 
-	if (pcie->mode == PCI_MODE_RC) {
+	if (IS_ENABLED(CONFIG_PCI_J721E_HOST) &&
+	    pcie->mode == PCI_MODE_RC) {
 		rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie);
 		cdns_pcie_host_disable(rc);
-	} else {
+	} else if (IS_ENABLED(CONFIG_PCI_J721E_EP)) {
 		ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie);
 		cdns_pcie_ep_disable(ep);
 	}
@@ -739,10 +744,12 @@ static int j721e_pcie_resume_noirq(struct device *dev)
 			gpiod_set_value_cansleep(pcie->reset_gpio, 1);
 		}
 
-		ret = cdns_pcie_host_link_setup(rc);
-		if (ret < 0) {
-			clk_disable_unprepare(pcie->refclk);
-			return ret;
+		if (IS_ENABLED(CONFIG_PCI_J721E_HOST)) {
+			ret = cdns_pcie_host_link_setup(rc);
+			if (ret < 0) {
+				clk_disable_unprepare(pcie->refclk);
+				return ret;
+			}
 		}
 
 		/*
@@ -752,10 +759,12 @@ static int j721e_pcie_resume_noirq(struct device *dev)
 		for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
 			rc->avail_ib_bar[bar] = true;
 
-		ret = cdns_pcie_host_init(rc);
-		if (ret) {
-			clk_disable_unprepare(pcie->refclk);
-			return ret;
+		if (IS_ENABLED(CONFIG_PCI_J721E_HOST)) {
+			ret = cdns_pcie_host_init(rc);
+			if (ret) {
+				clk_disable_unprepare(pcie->refclk);
+				return ret;
+			}
 		}
 	}
 
-- 
2.51.1

Re: [PATCH] PCI: j721e: Add config guards for Cadence Host and Endpoint library APIs

[Arnd Bergmann]

On Mon, Nov 17, 2025, at 12:32, Siddharth Vadapalli wrote:
> Commit under Fixes enabled loadable module support for the driver under
> the assumption that it shall be the sole user of the Cadence Host and
> Endpoint library APIs. This assumption guarantees that we won't end up
> in a case where the driver is built-in and the library support is built
> as a loadable module.
>
> With the introduction of [1], this assumption is no longer valid. The
> SG2042 driver could be built as a loadable module, implying that the
> Cadence Host library is also selected as a loadable module. However, the
> pci-j721e.c driver could be built-in as indicated by CONFIG_PCI_J721E=y
> due to which the Cadence Endpoint library is built-in. Despite the
> library drivers being built as specified by their respective consumers,
> since the 'pci-j721e.c' driver has references to the Cadence Host
> library APIs as well, we run into a build error as reported at [0].
>
> Fix this by adding config guards as a temporary workaround. The proper
> fix is to split the 'pci-j721e.c' driver into independent Host and
> Endpoint drivers as aligned at [2].
>
> Fixes: a2790bf81f0f ("PCI: j721e: Add support to build as a loadable 
> module")
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: 
> https://lore.kernel.org/oe-kbuild-all/202511111705.MZ7ls8Hm-lkp@intel.com/
> Cc: <stable@vger.kernel.org>
> [0]: https://lore.kernel.org/r/202511111705.MZ7ls8Hm-lkp@intel.com/
> [1]: commit 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver")
> [2]: 
> https://lore.kernel.org/r/37f6f8ce-12b2-44ee-a94c-f21b29c98821@app.fastmail.com/
> Suggested-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Looks good to me,

Reviewed-by: Arnd Bergmann <arnd@arndb.de>

Re: [PATCH] PCI: j721e: Add config guards for Cadence Host and Endpoint library APIs

[Manivannan Sadhasivam]

On Mon, 17 Nov 2025 17:02:06 +0530, Siddharth Vadapalli wrote:
> Commit under Fixes enabled loadable module support for the driver under
> the assumption that it shall be the sole user of the Cadence Host and
> Endpoint library APIs. This assumption guarantees that we won't end up
> in a case where the driver is built-in and the library support is built
> as a loadable module.
> 
> With the introduction of [1], this assumption is no longer valid. The
> SG2042 driver could be built as a loadable module, implying that the
> Cadence Host library is also selected as a loadable module. However, the
> pci-j721e.c driver could be built-in as indicated by CONFIG_PCI_J721E=y
> due to which the Cadence Endpoint library is built-in. Despite the
> library drivers being built as specified by their respective consumers,
> since the 'pci-j721e.c' driver has references to the Cadence Host
> library APIs as well, we run into a build error as reported at [0].
> 
> [...]

Applied, thanks!

[1/1] PCI: j721e: Add config guards for Cadence Host and Endpoint library APIs
      commit: 4b361b1e92be255ff923453fe8db74086cc7cf66

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>

Re: [PATCH] PCI: j721e: Add config guards for Cadence Host and Endpoint library APIs

[Bjorn Helgaas]

On Mon, Nov 17, 2025 at 05:02:06PM +0530, Siddharth Vadapalli wrote:
> Commit under Fixes enabled loadable module support for the driver under
> the assumption that it shall be the sole user of the Cadence Host and
> Endpoint library APIs. This assumption guarantees that we won't end up
> in a case where the driver is built-in and the library support is built
> as a loadable module.
> 
> With the introduction of [1], this assumption is no longer valid. The
> SG2042 driver could be built as a loadable module, implying that the
> Cadence Host library is also selected as a loadable module. However, the
> pci-j721e.c driver could be built-in as indicated by CONFIG_PCI_J721E=y
> due to which the Cadence Endpoint library is built-in. Despite the
> library drivers being built as specified by their respective consumers,
> since the 'pci-j721e.c' driver has references to the Cadence Host
> library APIs as well, we run into a build error as reported at [0].
> 
> Fix this by adding config guards as a temporary workaround. The proper
> fix is to split the 'pci-j721e.c' driver into independent Host and
> Endpoint drivers as aligned at [2].

If we know what the proper fix is, why aren't we just doing that
instead of adding a temporary workaround?

> Fixes: a2790bf81f0f ("PCI: j721e: Add support to build as a loadable module")
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202511111705.MZ7ls8Hm-lkp@intel.com/
> Cc: <stable@vger.kernel.org>
> [0]: https://lore.kernel.org/r/202511111705.MZ7ls8Hm-lkp@intel.com/
> [1]: commit 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver")
> [2]: https://lore.kernel.org/r/37f6f8ce-12b2-44ee-a94c-f21b29c98821@app.fastmail.com/
> Suggested-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>  drivers/pci/controller/cadence/pci-j721e.c | 43 +++++++++++++---------
>  1 file changed, 26 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index 5bc5ab20aa6d..67c5e02afccf 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -628,10 +628,12 @@ static int j721e_pcie_probe(struct platform_device *pdev)
>  			gpiod_set_value_cansleep(gpiod, 1);
>  		}
>  
> -		ret = cdns_pcie_host_setup(rc);
> -		if (ret < 0) {
> -			clk_disable_unprepare(pcie->refclk);
> -			goto err_pcie_setup;
> +		if (IS_ENABLED(CONFIG_PCI_J721E_HOST)) {
> +			ret = cdns_pcie_host_setup(rc);
> +			if (ret < 0) {
> +				clk_disable_unprepare(pcie->refclk);
> +				goto err_pcie_setup;
> +			}
>  		}
>  
>  		break;
> @@ -642,9 +644,11 @@ static int j721e_pcie_probe(struct platform_device *pdev)
>  			goto err_get_sync;
>  		}
>  
> -		ret = cdns_pcie_ep_setup(ep);
> -		if (ret < 0)
> -			goto err_pcie_setup;
> +		if (IS_ENABLED(CONFIG_PCI_J721E_EP)) {
> +			ret = cdns_pcie_ep_setup(ep);
> +			if (ret < 0)
> +				goto err_pcie_setup;
> +		}
>  
>  		break;
>  	}
> @@ -669,10 +673,11 @@ static void j721e_pcie_remove(struct platform_device *pdev)
>  	struct cdns_pcie_ep *ep;
>  	struct cdns_pcie_rc *rc;
>  
> -	if (pcie->mode == PCI_MODE_RC) {
> +	if (IS_ENABLED(CONFIG_PCI_J721E_HOST) &&
> +	    pcie->mode == PCI_MODE_RC) {
>  		rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie);
>  		cdns_pcie_host_disable(rc);
> -	} else {
> +	} else if (IS_ENABLED(CONFIG_PCI_J721E_EP)) {
>  		ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie);
>  		cdns_pcie_ep_disable(ep);
>  	}
> @@ -739,10 +744,12 @@ static int j721e_pcie_resume_noirq(struct device *dev)
>  			gpiod_set_value_cansleep(pcie->reset_gpio, 1);
>  		}
>  
> -		ret = cdns_pcie_host_link_setup(rc);
> -		if (ret < 0) {
> -			clk_disable_unprepare(pcie->refclk);
> -			return ret;
> +		if (IS_ENABLED(CONFIG_PCI_J721E_HOST)) {
> +			ret = cdns_pcie_host_link_setup(rc);
> +			if (ret < 0) {
> +				clk_disable_unprepare(pcie->refclk);
> +				return ret;
> +			}
>  		}
>  
>  		/*
> @@ -752,10 +759,12 @@ static int j721e_pcie_resume_noirq(struct device *dev)
>  		for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
>  			rc->avail_ib_bar[bar] = true;
>  
> -		ret = cdns_pcie_host_init(rc);
> -		if (ret) {
> -			clk_disable_unprepare(pcie->refclk);
> -			return ret;
> +		if (IS_ENABLED(CONFIG_PCI_J721E_HOST)) {
> +			ret = cdns_pcie_host_init(rc);
> +			if (ret) {
> +				clk_disable_unprepare(pcie->refclk);
> +				return ret;
> +			}
>  		}
>  	}
>  
> -- 
> 2.51.1
> 

Re: [PATCH] PCI: j721e: Add config guards for Cadence Host and Endpoint library APIs

[Siddharth Vadapalli]

On Fri, 2025-12-26 at 11:19 -0600, Bjorn Helgaas wrote:

Hello Bjorn,

> On Mon, Nov 17, 2025 at 05:02:06PM +0530, Siddharth Vadapalli wrote:
> > Commit under Fixes enabled loadable module support for the driver under
> > the assumption that it shall be the sole user of the Cadence Host and
> > Endpoint library APIs. This assumption guarantees that we won't end up
> > in a case where the driver is built-in and the library support is built
> > as a loadable module.
> > 
> > With the introduction of [1], this assumption is no longer valid. The
> > SG2042 driver could be built as a loadable module, implying that the
> > Cadence Host library is also selected as a loadable module. However, the
> > pci-j721e.c driver could be built-in as indicated by CONFIG_PCI_J721E=y
> > due to which the Cadence Endpoint library is built-in. Despite the
> > library drivers being built as specified by their respective consumers,
> > since the 'pci-j721e.c' driver has references to the Cadence Host
> > library APIs as well, we run into a build error as reported at [0].
> > 
> > Fix this by adding config guards as a temporary workaround. The proper
> > fix is to split the 'pci-j721e.c' driver into independent Host and
> > Endpoint drivers as aligned at [2].
> 
> If we know what the proper fix is, why aren't we just doing that
> instead of adding a temporary workaround?

The issue appeared (was discovered) since commit [1] mentioned below. After
the issue was reported, and given the severity of the issue (build failure
[0] below), refactoring the driver in the short time frame (issue was
reported close to the end of the merge window) didn't seem feasible.
Therefore, the temporary workaround was posted to address the issue
quickly. I will be posting a series to refactor the driver in a few weeks.

> 
> > Fixes: a2790bf81f0f ("PCI: j721e: Add support to build as a loadable module")
> > Reported-by: kernel test robot <lkp@intel.com>
> > Closes: https://lore.kernel.org/oe-kbuild-all/202511111705.MZ7ls8Hm-lkp@intel.com/
> > Cc: <stable@vger.kernel.org>
> > [0]: https://lore.kernel.org/r/202511111705.MZ7ls8Hm-lkp@intel.com/
> > [1]: commit 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver")
> > [2]: https://lore.kernel.org/r/37f6f8ce-12b2-44ee-a94c-f21b29c98821@app.fastmail.com/
> > Suggested-by: Arnd Bergmann <arnd@arndb.de>
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> >  drivers/pci/controller/cadence/pci-j721e.c | 43 +++++++++++++---------
> >  1 file changed, 26 insertions(+), 17 deletions(-)

[TRIMMED]

Regards,
Siddharth.