Re: [PATCH v2 2/3] cpufreq: ti-cpufreq: add support for AM62L3 SoC

[Dhruva Gole <d-gole@ti.com>]

On Jan 16, 2026 at 15:15:29 -0600, Kendall Willis wrote:
> On 1/16/26 04:21, Dhruva Gole wrote:
> > Add CPUFreq support for the AM62L3 SoC with the appropriate
> > AM62L3 speed grade constants according to the datasheet [1].
> > 
> > This follows the same architecture-specific implementation pattern
> > as other TI SoCs in the AM6x family.
> > 
> > While at it, also sort instances where the SOC family names
> > were not sorted alphabetically.
> > 
> > [1] https://www.ti.com/lit/pdf/SPRSPA1
> > 
> > Signed-off-by: Dhruva Gole <d-gole@ti.com>
> > ---
> >   drivers/cpufreq/ti-cpufreq.c | 34 +++++++++++++++++++++++++++++++++-
> >   1 file changed, 33 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c
> > index 6ee76f5fe9c567b0b88797ddb51764a2a5606b16..4e65e96b784ee908716c63316bb54eb1ac1efc49 100644
> > --- a/drivers/cpufreq/ti-cpufreq.c
> > +++ b/drivers/cpufreq/ti-cpufreq.c
> > @@ -48,6 +48,12 @@
> >   #define AM625_SUPPORT_S_MPU_OPP			BIT(1)
> >   #define AM625_SUPPORT_T_MPU_OPP			BIT(2)
> > +#define AM62L3_EFUSE_E_MPU_OPP			5
> > +#define AM62L3_EFUSE_O_MPU_OPP			15
> > +
> > +#define AM62L3_SUPPORT_E_MPU_OPP		BIT(0)
> > +#define AM62L3_SUPPORT_O_MPU_OPP		BIT(1)
> > +
> 
> Shouldn't these defines for AM62L be placed after the AM62A defines to
> maintain alphabetical order?
> 
> >   enum {
> >   	AM62A7_EFUSE_M_MPU_OPP =		13,
> >   	AM62A7_EFUSE_N_MPU_OPP,
> > @@ -213,6 +219,22 @@ static unsigned long am625_efuse_xlate(struct ti_cpufreq_data *opp_data,
> >   	return calculated_efuse;
> >   }
> > +static unsigned long am62l3_efuse_xlate(struct ti_cpufreq_data *opp_data,
> > +				       unsigned long efuse)
> > +{
> > +	unsigned long calculated_efuse = AM62L3_SUPPORT_E_MPU_OPP;
> > +
> > +	switch (efuse) {
> > +	case AM62L3_EFUSE_O_MPU_OPP:
> > +		calculated_efuse |= AM62L3_SUPPORT_O_MPU_OPP;
> > +		fallthrough;
> > +	case AM62L3_EFUSE_E_MPU_OPP:
> > +		calculated_efuse |= AM62L3_SUPPORT_E_MPU_OPP;
> > +	}
> > +
> > +	return calculated_efuse;
> > +}
> > +
> >   static struct ti_cpufreq_soc_data am3x_soc_data = {
> >   	.efuse_xlate = amx3_efuse_xlate,
> >   	.efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
> > @@ -313,8 +335,9 @@ static struct ti_cpufreq_soc_data am3517_soc_data = {
> >   static const struct soc_device_attribute k3_cpufreq_soc[] = {
> >   	{ .family = "AM62X", },
> >   	{ .family = "AM62AX", },
> > -	{ .family = "AM62PX", },
> >   	{ .family = "AM62DX", },
> > +	{ .family = "AM62LX", },
> > +	{ .family = "AM62PX", },
> >   	{ /* sentinel */ }
> >   };
> > @@ -327,6 +350,14 @@ static struct ti_cpufreq_soc_data am625_soc_data = {
> >   	.quirks = TI_QUIRK_SYSCON_IS_SINGLE_REG,
> >   };
> > +static struct ti_cpufreq_soc_data am62l3_soc_data = {
> > +	.efuse_xlate = am62l3_efuse_xlate,
> > +	.efuse_offset = 0x0,
> > +	.efuse_mask = 0x07c0,
> > +	.efuse_shift = 0x6,
> > +	.multi_regulator = false,
> > +};
> > +
> 
> Same thing here with the AM62L struct being before the AM62A struct which is
> not alphabetical.

okay addressing and sending next rev, thanks for reviewing.

> 
> >   static struct ti_cpufreq_soc_data am62a7_soc_data = {
> >   	.efuse_xlate = am62a7_efuse_xlate,
> >   	.efuse_offset = 0x0,
> > @@ -463,6 +494,7 @@ static const struct of_device_id ti_cpufreq_of_match[]  __maybe_unused = {
> >   	{ .compatible = "ti,am625", .data = &am625_soc_data, },
> >   	{ .compatible = "ti,am62a7", .data = &am62a7_soc_data, },
> >   	{ .compatible = "ti,am62d2", .data = &am62a7_soc_data, },
> > +	{ .compatible = "ti,am62l3", .data = &am62l3_soc_data, },
> >   	{ .compatible = "ti,am62p5", .data = &am62p5_soc_data, },
> >   	/* legacy */
> >   	{ .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
> > 
> 
> Best,
> Kendall Willis <k-willis@ti.com>
> 

-- 
Best regards,
Dhruva Gole
Texas Instruments Incorporated