From: Richard Zhu <hongxing.zhu@nxp.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
bhelgaas@google.com, frank.li@nxp.com, l.stach@pengutronix.de,
lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de,
festevam@gmail.com
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v8 3/5] arm64: dts: imx94: Add pcie0 and pcie0-ep supports
Date: Tue, 24 Mar 2026 10:30:34 +0800 [thread overview]
Message-ID: <20260324023036.784466-4-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <20260324023036.784466-1-hongxing.zhu@nxp.com>
Add pcie0 and pcie0-ep supports.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx94.dtsi | 88 ++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index 38488147a3ef..5d19c34cbc2b 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -66,6 +66,13 @@ sai4_mclk: clock-sai4-mclk1 {
clock-output-names = "sai4_mclk";
};
+ clk_sys100m: clock-sys100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "clk_sys100m";
+ };
+
firmware {
scmi {
compatible = "arm,scmi";
@@ -1230,6 +1237,14 @@ wdog3: watchdog@49220000 {
};
};
+ hsio_blk_ctl: syscon@4c0100c0 {
+ compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
+ reg = <0x0 0x4c0100c0 0x0 0x1>;
+ #clock-cells = <1>;
+ clocks = <&clk_sys100m>;
+ power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
+ };
+
usb3: usb@4c100000 {
compatible = "nxp,imx94-dwc3", "nxp,imx8mp-dwc3";
reg = <0x0 0x4c100000 0x0 0x10000>,
@@ -1284,6 +1299,79 @@ usbmisc: usbmisc@4c200200 {
#index-cells = <1>;
};
+ pcie0: pcie@4c300000 {
+ compatible = "fsl,imx94-pcie", "fsl,imx95-pcie";
+ reg = <0 0x4c300000 0 0x10000>,
+ <0 0x60100000 0 0xfe00000>,
+ <0 0x4c360000 0 0x10000>,
+ <0 0x4c340000 0 0x4000>;
+ reg-names = "dbi", "config", "atu", "app";
+ ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
+ <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <2>;
+ msi-map = <0x0 &its 0x10 0x1>,
+ <0x100 &its 0x11 0x7>;
+ msi-map-mask = <0x1ff>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ num-viewport = <8>;
+ interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX94_CLK_HSIO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
+ <&hsio_blk_ctl 0>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
+ assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
+ assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
+ assigned-clock-parents = <0>, <0>,
+ <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
+ power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
+ fsl,max-link-speed = <3>;
+ status = "disabled";
+ };
+
+ pcie0_ep: pcie-ep@4c300000 {
+ compatible = "fsl,imx94-pcie-ep", "fsl,imx95-pcie-ep";
+ reg = <0 0x4c300000 0 0x10000>,
+ <0 0x4c360000 0 0x1000>,
+ <0 0x4c320000 0 0x1000>,
+ <0 0x4c340000 0 0x4000>,
+ <0 0x4c370000 0 0x10000>,
+ <0x9 0 1 0>;
+ reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ clocks = <&scmi_clk IMX94_CLK_HSIO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
+ assigned-clocks = <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX94_CLK_HSIOPLL>,
+ <&scmi_clk IMX94_CLK_HSIOPCIEAUX>;
+ assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
+ assigned-clock-parents = <0>, <0>,
+ <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
+ msi-map = <0x0 &its 0x10 0x1>;
+ power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
+ status = "disabled";
+ };
+
netc_blk_ctrl: system-controller@4ceb0000 {
compatible = "nxp,imx94-netc-blk-ctrl";
reg = <0x0 0x4ceb0000 0x0 0x10000>,
--
2.37.1
next prev parent reply other threads:[~2026-03-24 2:29 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-24 2:30 [PATCH v8 0/5] Add i.MX943 PCIe supports Richard Zhu
2026-03-24 2:30 ` [PATCH v8 1/5] dt-bindings: PCI: imx6q-pcie: Change maxItems of clocks and clock-names to 6 Richard Zhu
2026-03-24 2:30 ` [PATCH v8 2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and i.MX943 PCIe compatible strings Richard Zhu
2026-03-25 0:54 ` Rob Herring (Arm)
2026-03-24 2:30 ` Richard Zhu [this message]
2026-05-04 21:18 ` [PATCH v8 3/5] arm64: dts: imx94: Add pcie0 and pcie0-ep supports Frank Li
2026-05-06 4:01 ` Hongxing Zhu
2026-03-24 2:30 ` [PATCH v8 4/5] arm64: dts: imx943: Add pcie1 and pcie1-ep supports Richard Zhu
2026-03-24 2:30 ` [PATCH v8 5/5] arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support Richard Zhu
2026-03-24 8:10 ` Manivannan Sadhasivam
2026-04-04 10:42 ` (subset) [PATCH v8 0/5] Add i.MX943 PCIe supports Manivannan Sadhasivam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260324023036.784466-4-hongxing.zhu@nxp.com \
--to=hongxing.zhu@nxp.com \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=frank.li@nxp.com \
--cc=imx@lists.linux.dev \
--cc=kernel@pengutronix.de \
--cc=krzk+dt@kernel.org \
--cc=kwilczynski@kernel.org \
--cc=l.stach@pengutronix.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=mani@kernel.org \
--cc=robh@kernel.org \
--cc=s.hauer@pengutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox