[PATCH v8 0/4] Add Qualcomm extended CTI support

[PATCH v8 0/4] Add Qualcomm extended CTI support

[Yingchao Deng]

The Qualcomm extended CTI is a heavily parameterized version of ARM’s
CSCTI. It allows a debugger to send to trigger events to a processor or to
send a trigger event to one or more processors when a trigger event occurs
on another processor on the same SoC, or even between SoCs.

Qualcomm extended CTI supports up to 128 triggers. And some of the register
offsets are changed.

The commands to configure CTI triggers are the same as ARM's CTI.

Prerequisites:
   This series depends on the following CoreSight fix:
   [PATCH v2 1/1] coresight: fix issue where coresight component has no claimtags
Link: https://lore.kernel.org/all/20251027223545.2801-2-mike.leach@linaro.org/

Changes in v8:
1. Rebased on top of linux-next-20260424.
2. patch 1: Use devm_bitmap_zalloc() with nr_trig_max instead of per-connection
   signal counts; add bitmap_zalloc() for filter trigger group.
3. patch 2: Add #include <linux/bitfield.h>; move CTIINOUTEN_MAX expansion
   to patch3.
4. patch 3: wrap CLAIMSET clear with CS_UNLOCK/CS_LOCK; move CTIINOUTEN_MAX
   to 128 here with comment; fix macro alignment in qcom-cti.h.
5. patch 4: Make qcom_suffix_registers[] static.

Changes in v7:
1. Split the extended CTI support into smaller, logically independent
   patches to improve reviewability.
2. Removed the dual offset-array based register access used in v6 for
   standard and Qualcomm CTIs. Register addressing is now unified through
   a single code path by encoding the register index together with the base
   offset and applying variant-specific translation at the final MMIO
   access point. 
3. Removed ext_reg_sel, extend the CTI sysfs interface to expose banked 
   register instances on Qualcomm CTIs only. Numbered sysfs nodes are
   hidden on standard ARM CTIs, and on Qualcomm CTIs their visibility is
   derived from nr_trig_max (32 triggers per bank), ensuring that only
   registers backed by hardware are exposed.
Link to v6 - https://lore.kernel.org/all/20251202-extended_cti-v6-0-ab68bb15c4f5@oss.qualcomm.com/

Changes in v6:
1. Rename regs_idx to ext_reg_sel and add information in documentation
   file.
2. Reset CLAIMSET to zero for qcom-cti during probe.
3. Retrieve idx value under spinlock.
4. Use yearless copyright for qcom-cti.h.
Link to v5 - https://lore.kernel.org/all/20251020-extended_cti-v5-0-6f193da2d467@oss.qualcomm.com/

Changes in v5:
1. Move common part in qcom-cti.h to coresight-cti.h.
2. Convert trigger usage fields to dynamic bitmaps and arrays.
3. Fix holes in struct cti_config to save some space.
4. Revert the previous changes related to the claim tag in
   cti_enable/disable_hw.
Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/

Changes in v4:
1. Read the DEVARCH registers to identify Qualcomm CTI.
2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and
coresight_cti_reg_store() functions accordingly.
3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h.
Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/

Changes in v3:
1. Rename is_extended_cti() to of_is_extended_cti().
2. Add the missing 'i' when write the CTI trigger registers.
3. Convert the multi-line output in sysfs to single line.
4. Initialize offset arrays using designated initializer.
Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/

Changes in V2:
1. Add enum for compatible items.
2. Move offset arrays to coresight-cti-core

Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
---
Yingchao Deng (4):
      coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays
      coresight: cti: encode trigger register index in register offsets
      coresight: cti: add Qualcomm extended CTI identification and quirks
      coresight: cti: expose banked sysfs registers for Qualcomm extended CTI

 drivers/hwtracing/coresight/coresight-cti-core.c   | 118 ++++++++++++++++-----
 .../hwtracing/coresight/coresight-cti-platform.c   |  26 +++--
 drivers/hwtracing/coresight/coresight-cti-sysfs.c  |  76 +++++++++++--
 drivers/hwtracing/coresight/coresight-cti.h        |  32 ++++--
 drivers/hwtracing/coresight/qcom-cti.h             |  65 ++++++++++++
 5 files changed, 265 insertions(+), 52 deletions(-)
---
base-commit: 8594d92c94a3624acf07acf634a5e73a8c8f63e2
change-id: 20260426-extended-cti-32f728f93cba

Best regards,
-- 
Yingchao Deng <yingchao.deng@oss.qualcomm.com>

[PATCH v8 1/4] coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays

[Yingchao Deng]

Replace the fixed-size u32 fields in the cti_config and cti_trig_grp
structure with dynamically allocated bitmaps and arrays. This allows
memory to be allocated based on the actual number of triggers during probe
time, reducing memory footprint and improving scalability for platforms
with varying trigger counts.

Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
---
 drivers/hwtracing/coresight/coresight-cti-core.c   | 59 +++++++++++++++++-----
 .../hwtracing/coresight/coresight-cti-platform.c   | 26 +++++++---
 drivers/hwtracing/coresight/coresight-cti-sysfs.c  | 14 ++---
 drivers/hwtracing/coresight/coresight-cti.h        | 12 ++---
 4 files changed, 76 insertions(+), 35 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c
index 2f4c9362709a..4e7d12bd2d3e 100644
--- a/drivers/hwtracing/coresight/coresight-cti-core.c
+++ b/drivers/hwtracing/coresight/coresight-cti-core.c
@@ -161,8 +161,8 @@ void cti_write_intack(struct device *dev, u32 ackval)
 /* DEVID[19:16] - number of CTM channels */
 #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19))
 
-static void cti_set_default_config(struct device *dev,
-				   struct cti_drvdata *drvdata)
+static int cti_set_default_config(struct device *dev,
+				  struct cti_drvdata *drvdata)
 {
 	struct cti_config *config = &drvdata->config;
 	u32 devid;
@@ -181,6 +181,26 @@ static void cti_set_default_config(struct device *dev,
 		config->nr_trig_max = CTIINOUTEN_MAX;
 	}
 
+	config->trig_in_use = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL);
+	if (!config->trig_in_use)
+		return -ENOMEM;
+
+	config->trig_out_use = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL);
+	if (!config->trig_out_use)
+		return -ENOMEM;
+
+	config->trig_out_filter = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL);
+	if (!config->trig_out_filter)
+		return -ENOMEM;
+
+	config->ctiinen = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), GFP_KERNEL);
+	if (!config->ctiinen)
+		return -ENOMEM;
+
+	config->ctiouten = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), GFP_KERNEL);
+	if (!config->ctiouten)
+		return -ENOMEM;
+
 	config->nr_ctm_channels = CTI_DEVID_CTMCHANNELS(devid);
 
 	/* Most regs default to 0 as zalloc'ed except...*/
@@ -189,6 +209,7 @@ static void cti_set_default_config(struct device *dev,
 	config->enable_req_count = 0;
 
 	config->asicctl_impl = !!FIELD_GET(GENMASK(4, 0), devid);
+	return 0;
 }
 
 /*
@@ -219,8 +240,10 @@ int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata,
 	cti_dev->nr_trig_con++;
 
 	/* add connection usage bit info to overall info */
-	drvdata->config.trig_in_use |= tc->con_in->used_mask;
-	drvdata->config.trig_out_use |= tc->con_out->used_mask;
+	bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use,
+		  tc->con_in->used_mask, drvdata->config.nr_trig_max);
+	bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use,
+		  tc->con_out->used_mask, drvdata->config.nr_trig_max);
 
 	return 0;
 }
@@ -231,6 +254,8 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,
 {
 	struct cti_trig_con *tc = NULL;
 	struct cti_trig_grp *in = NULL, *out = NULL;
+	struct cti_drvdata *drvdata = dev_get_drvdata(dev);
+	int n_trigs = drvdata->config.nr_trig_max;
 
 	tc = devm_kzalloc(dev, sizeof(struct cti_trig_con), GFP_KERNEL);
 	if (!tc)
@@ -242,12 +267,20 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,
 	if (!in)
 		return NULL;
 
+	in->used_mask = devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL);
+	if (!in->used_mask)
+		return NULL;
+
 	out = devm_kzalloc(dev,
 			   offsetof(struct cti_trig_grp, sig_types[out_sigs]),
 			   GFP_KERNEL);
 	if (!out)
 		return NULL;
 
+	out->used_mask = devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL);
+	if (!out->used_mask)
+		return NULL;
+
 	tc->con_in = in;
 	tc->con_out = out;
 	tc->con_in->nr_sigs = in_sigs;
@@ -263,7 +296,6 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata)
 {
 	int ret = 0;
 	int n_trigs = drvdata->config.nr_trig_max;
-	u32 n_trig_mask = GENMASK(n_trigs - 1, 0);
 	struct cti_trig_con *tc = NULL;
 
 	/*
@@ -274,8 +306,8 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata)
 	if (!tc)
 		return -ENOMEM;
 
-	tc->con_in->used_mask = n_trig_mask;
-	tc->con_out->used_mask = n_trig_mask;
+	bitmap_fill(tc->con_in->used_mask, n_trigs);
+	bitmap_fill(tc->con_out->used_mask, n_trigs);
 	ret = cti_add_connection_entry(dev, drvdata, tc, NULL, "default");
 	return ret;
 }
@@ -288,7 +320,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,
 {
 	struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
 	struct cti_config *config = &drvdata->config;
-	u32 trig_bitmask;
 	u32 chan_bitmask;
 	u32 reg_value;
 	int reg_offset;
@@ -298,18 +329,16 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,
 	   (trigger_idx >= config->nr_trig_max))
 		return -EINVAL;
 
-	trig_bitmask = BIT(trigger_idx);
-
 	/* ensure registered triggers and not out filtered */
 	if (direction == CTI_TRIG_IN)	{
-		if (!(trig_bitmask & config->trig_in_use))
+		if (!(test_bit(trigger_idx, config->trig_in_use)))
 			return -EINVAL;
 	} else {
-		if (!(trig_bitmask & config->trig_out_use))
+		if (!(test_bit(trigger_idx, config->trig_out_use)))
 			return -EINVAL;
 
 		if ((config->trig_filter_enable) &&
-		    (config->trig_out_filter & trig_bitmask))
+		    test_bit(trigger_idx, config->trig_out_filter))
 			return -EINVAL;
 	}
 
@@ -687,7 +716,9 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
 	raw_spin_lock_init(&drvdata->spinlock);
 
 	/* initialise CTI driver config values */
-	cti_set_default_config(dev, drvdata);
+	ret = cti_set_default_config(dev, drvdata);
+	if (ret)
+		return ret;
 
 	pdata = coresight_cti_get_platform_data(dev);
 	if (IS_ERR(pdata)) {
diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c
index 4eff96f48594..557debbc8ca4 100644
--- a/drivers/hwtracing/coresight/coresight-cti-platform.c
+++ b/drivers/hwtracing/coresight/coresight-cti-platform.c
@@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct device *dev,
 		goto create_v8_etm_out;
 
 	/* build connection data */
-	tc->con_in->used_mask = 0xF0; /* sigs <4,5,6,7> */
-	tc->con_out->used_mask = 0xF0; /* sigs <4,5,6,7> */
+	bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */
+	bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */
 
 	/*
 	 * The EXTOUT type signals from the ETM are connected to a set of input
@@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct device *dev,
 		goto of_create_v8_out;
 
 	/* Set the v8 PE CTI connection data */
-	tc->con_in->used_mask = 0x3; /* sigs <0 1> */
+	bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */
 	tc->con_in->sig_types[0] = PE_DBGTRIGGER;
 	tc->con_in->sig_types[1] = PE_PMUIRQ;
-	tc->con_out->used_mask = 0x7; /* sigs <0 1 2 > */
+	bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */
 	tc->con_out->sig_types[0] = PE_EDBGREQ;
 	tc->con_out->sig_types[1] = PE_DBGRESTART;
 	tc->con_out->sig_types[2] = PE_CTIIRQ;
@@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device *dev,
 		goto of_create_v8_out;
 
 	/* filter pe_edbgreq - PE trigout sig <0> */
-	drvdata->config.trig_out_filter |= 0x1;
+	set_bit(0, drvdata->config.trig_out_filter);
 
 of_create_v8_out:
 	return ret;
@@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp *tgrp,
 	if (!err) {
 		/* set the signal usage mask */
 		for (idx = 0; idx < tgrp->nr_sigs; idx++)
-			tgrp->used_mask |= BIT(values[idx]);
+			set_bit(values[idx], tgrp->used_mask);
 	}
 
 	kfree(values);
@@ -316,23 +316,33 @@ static int cti_plat_process_filter_sigs(struct cti_drvdata *drvdata,
 {
 	struct cti_trig_grp *tg = NULL;
 	int err = 0, nr_filter_sigs;
+	int nr_trigs = drvdata->config.nr_trig_max;
 
 	nr_filter_sigs = cti_plat_count_sig_elements(fwnode,
 						     CTI_DT_FILTER_OUT_SIGS);
 	if (nr_filter_sigs == 0)
 		return 0;
 
-	if (nr_filter_sigs > drvdata->config.nr_trig_max)
+	if (nr_filter_sigs > nr_trigs)
 		return -EINVAL;
 
 	tg = kzalloc_obj(*tg);
 	if (!tg)
 		return -ENOMEM;
 
+	tg->used_mask = bitmap_zalloc(nr_trigs, GFP_KERNEL);
+	if (!tg->used_mask) {
+		kfree(tg);
+		return -ENOMEM;
+	}
+
 	err = cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS);
 	if (!err)
-		drvdata->config.trig_out_filter |= tg->used_mask;
+		bitmap_or(drvdata->config.trig_out_filter,
+			  drvdata->config.trig_out_filter,
+			  tg->used_mask, nr_trigs);
 
+	bitmap_free(tg->used_mask);
 	kfree(tg);
 	return err;
 }
diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
index 3fe2c916d228..2bbfa405cb6b 100644
--- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
@@ -719,12 +719,12 @@ static ssize_t trigout_filtered_show(struct device *dev,
 	struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
 	struct cti_config *cfg = &drvdata->config;
 	int nr_trig_max = cfg->nr_trig_max;
-	unsigned long mask = cfg->trig_out_filter;
+	unsigned long *mask = cfg->trig_out_filter;
 
-	if (mask == 0)
+	if (bitmap_empty(mask, nr_trig_max))
 		return 0;
 
-	return sysfs_emit(buf, "%*pbl\n", nr_trig_max, &mask);
+	return sysfs_emit(buf, "%*pbl\n", nr_trig_max, mask);
 }
 static DEVICE_ATTR_RO(trigout_filtered);
 
@@ -931,9 +931,9 @@ static ssize_t trigin_sig_show(struct device *dev,
 	struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
 	struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
 	struct cti_config *cfg = &drvdata->config;
-	unsigned long mask = con->con_in->used_mask;
+	unsigned long *mask = con->con_in->used_mask;
 
-	return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask);
+	return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask);
 }
 
 static ssize_t trigout_sig_show(struct device *dev,
@@ -945,9 +945,9 @@ static ssize_t trigout_sig_show(struct device *dev,
 	struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
 	struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
 	struct cti_config *cfg = &drvdata->config;
-	unsigned long mask = con->con_out->used_mask;
+	unsigned long *mask = con->con_out->used_mask;
 
-	return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask);
+	return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask);
 }
 
 /* convert a sig type id to a name */
diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h
index c5f9e79fabc6..ef079fc18b72 100644
--- a/drivers/hwtracing/coresight/coresight-cti.h
+++ b/drivers/hwtracing/coresight/coresight-cti.h
@@ -68,7 +68,7 @@ struct fwnode_handle;
  */
 struct cti_trig_grp {
 	int nr_sigs;
-	u32 used_mask;
+	unsigned long *used_mask;
 	int sig_types[];
 };
 
@@ -145,17 +145,17 @@ struct cti_config {
 	int enable_req_count;
 
 	/* registered triggers and filtering */
-	u32 trig_in_use;
-	u32 trig_out_use;
-	u32 trig_out_filter;
+	unsigned long *trig_in_use;
+	unsigned long *trig_out_use;
+	unsigned long *trig_out_filter;
 	bool trig_filter_enable;
 	u8 xtrig_rchan_sel;
 
 	/* cti cross trig programmable regs */
 	u32 ctiappset;
 	u8 ctiinout_sel;
-	u32 ctiinen[CTIINOUTEN_MAX];
-	u32 ctiouten[CTIINOUTEN_MAX];
+	u32 *ctiinen;
+	u32 *ctiouten;
 	u32 ctigate;
 	u32 asicctl;
 };

-- 
2.43.0

Re: [PATCH v8 1/4] coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays

[Jie Gan]

On 4/26/2026 5:44 PM, Yingchao Deng wrote:
> Replace the fixed-size u32 fields in the cti_config and cti_trig_grp
> structure with dynamically allocated bitmaps and arrays. This allows
> memory to be allocated based on the actual number of triggers during probe
> time, reducing memory footprint and improving scalability for platforms
> with varying trigger counts.
> 
> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> ---
>   drivers/hwtracing/coresight/coresight-cti-core.c   | 59 +++++++++++++++++-----
>   .../hwtracing/coresight/coresight-cti-platform.c   | 26 +++++++---
>   drivers/hwtracing/coresight/coresight-cti-sysfs.c  | 14 ++---
>   drivers/hwtracing/coresight/coresight-cti.h        | 12 ++---
>   4 files changed, 76 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c
> index 2f4c9362709a..4e7d12bd2d3e 100644
> --- a/drivers/hwtracing/coresight/coresight-cti-core.c
> +++ b/drivers/hwtracing/coresight/coresight-cti-core.c
> @@ -161,8 +161,8 @@ void cti_write_intack(struct device *dev, u32 ackval)
>   /* DEVID[19:16] - number of CTM channels */
>   #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19))
>   
> -static void cti_set_default_config(struct device *dev,
> -				   struct cti_drvdata *drvdata)
> +static int cti_set_default_config(struct device *dev,
> +				  struct cti_drvdata *drvdata)
>   {
>   	struct cti_config *config = &drvdata->config;
>   	u32 devid;
> @@ -181,6 +181,26 @@ static void cti_set_default_config(struct device *dev,
>   		config->nr_trig_max = CTIINOUTEN_MAX;
>   	}
>   
> +	config->trig_in_use = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL);
> +	if (!config->trig_in_use)
> +		return -ENOMEM;
> +
> +	config->trig_out_use = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL);
> +	if (!config->trig_out_use)
> +		return -ENOMEM;
> +
> +	config->trig_out_filter = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL);
> +	if (!config->trig_out_filter)
> +		return -ENOMEM;
> +
> +	config->ctiinen = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), GFP_KERNEL);
> +	if (!config->ctiinen)
> +		return -ENOMEM;
> +
> +	config->ctiouten = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), GFP_KERNEL);
> +	if (!config->ctiouten)
> +		return -ENOMEM;
> +
>   	config->nr_ctm_channels = CTI_DEVID_CTMCHANNELS(devid);
>   
>   	/* Most regs default to 0 as zalloc'ed except...*/
> @@ -189,6 +209,7 @@ static void cti_set_default_config(struct device *dev,
>   	config->enable_req_count = 0;
>   
>   	config->asicctl_impl = !!FIELD_GET(GENMASK(4, 0), devid);
> +	return 0;
>   }
>   
>   /*
> @@ -219,8 +240,10 @@ int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata,
>   	cti_dev->nr_trig_con++;
>   
>   	/* add connection usage bit info to overall info */
> -	drvdata->config.trig_in_use |= tc->con_in->used_mask;
> -	drvdata->config.trig_out_use |= tc->con_out->used_mask;
> +	bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use,
> +		  tc->con_in->used_mask, drvdata->config.nr_trig_max);
> +	bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use,
> +		  tc->con_out->used_mask, drvdata->config.nr_trig_max);
>   
>   	return 0;
>   }
> @@ -231,6 +254,8 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,
>   {
>   	struct cti_trig_con *tc = NULL;
>   	struct cti_trig_grp *in = NULL, *out = NULL;
> +	struct cti_drvdata *drvdata = dev_get_drvdata(dev);
> +	int n_trigs = drvdata->config.nr_trig_max;
>   
>   	tc = devm_kzalloc(dev, sizeof(struct cti_trig_con), GFP_KERNEL);
>   	if (!tc)
> @@ -242,12 +267,20 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,
>   	if (!in)
>   		return NULL;
>   
> +	in->used_mask = devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL);
> +	if (!in->used_mask)
> +		return NULL;
> +
>   	out = devm_kzalloc(dev,
>   			   offsetof(struct cti_trig_grp, sig_types[out_sigs]),
>   			   GFP_KERNEL);
>   	if (!out)
>   		return NULL;
>   
> +	out->used_mask = devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL);
> +	if (!out->used_mask)
> +		return NULL;
> +
>   	tc->con_in = in;
>   	tc->con_out = out;
>   	tc->con_in->nr_sigs = in_sigs;
> @@ -263,7 +296,6 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata)
>   {
>   	int ret = 0;
>   	int n_trigs = drvdata->config.nr_trig_max;
> -	u32 n_trig_mask = GENMASK(n_trigs - 1, 0);
>   	struct cti_trig_con *tc = NULL;
>   
>   	/*
> @@ -274,8 +306,8 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata)
>   	if (!tc)
>   		return -ENOMEM;
>   
> -	tc->con_in->used_mask = n_trig_mask;
> -	tc->con_out->used_mask = n_trig_mask;
> +	bitmap_fill(tc->con_in->used_mask, n_trigs);
> +	bitmap_fill(tc->con_out->used_mask, n_trigs);
>   	ret = cti_add_connection_entry(dev, drvdata, tc, NULL, "default");
>   	return ret;
>   }
> @@ -288,7 +320,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,
>   {
>   	struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
>   	struct cti_config *config = &drvdata->config;
> -	u32 trig_bitmask;
>   	u32 chan_bitmask;
>   	u32 reg_value;
>   	int reg_offset;
> @@ -298,18 +329,16 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,
>   	   (trigger_idx >= config->nr_trig_max))
>   		return -EINVAL;
>   
> -	trig_bitmask = BIT(trigger_idx);
> -
>   	/* ensure registered triggers and not out filtered */
>   	if (direction == CTI_TRIG_IN)	{
> -		if (!(trig_bitmask & config->trig_in_use))
> +		if (!(test_bit(trigger_idx, config->trig_in_use)))
>   			return -EINVAL;
>   	} else {
> -		if (!(trig_bitmask & config->trig_out_use))
> +		if (!(test_bit(trigger_idx, config->trig_out_use)))
>   			return -EINVAL;
>   
>   		if ((config->trig_filter_enable) &&
> -		    (config->trig_out_filter & trig_bitmask))
> +		    test_bit(trigger_idx, config->trig_out_filter))
>   			return -EINVAL;
>   	}
>   
> @@ -687,7 +716,9 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
>   	raw_spin_lock_init(&drvdata->spinlock);
>   
>   	/* initialise CTI driver config values */
> -	cti_set_default_config(dev, drvdata);
> +	ret = cti_set_default_config(dev, drvdata);
> +	if (ret)
> +		return ret;
>   
>   	pdata = coresight_cti_get_platform_data(dev);
>   	if (IS_ERR(pdata)) {
> diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c
> index 4eff96f48594..557debbc8ca4 100644
> --- a/drivers/hwtracing/coresight/coresight-cti-platform.c
> +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c
> @@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct device *dev,
>   		goto create_v8_etm_out;
>   
>   	/* build connection data */
> -	tc->con_in->used_mask = 0xF0; /* sigs <4,5,6,7> */
> -	tc->con_out->used_mask = 0xF0; /* sigs <4,5,6,7> */
> +	bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */
> +	bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */
>   
>   	/*
>   	 * The EXTOUT type signals from the ETM are connected to a set of input
> @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct device *dev,
>   		goto of_create_v8_out;
>   
>   	/* Set the v8 PE CTI connection data */
> -	tc->con_in->used_mask = 0x3; /* sigs <0 1> */
> +	bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */
>   	tc->con_in->sig_types[0] = PE_DBGTRIGGER;
>   	tc->con_in->sig_types[1] = PE_PMUIRQ;
> -	tc->con_out->used_mask = 0x7; /* sigs <0 1 2 > */
> +	bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */
>   	tc->con_out->sig_types[0] = PE_EDBGREQ;
>   	tc->con_out->sig_types[1] = PE_DBGRESTART;
>   	tc->con_out->sig_types[2] = PE_CTIIRQ;
> @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device *dev,
>   		goto of_create_v8_out;
>   
>   	/* filter pe_edbgreq - PE trigout sig <0> */
> -	drvdata->config.trig_out_filter |= 0x1;
> +	set_bit(0, drvdata->config.trig_out_filter);
>   
>   of_create_v8_out:
>   	return ret;
> @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp *tgrp,
>   	if (!err) {
>   		/* set the signal usage mask */
>   		for (idx = 0; idx < tgrp->nr_sigs; idx++)
> -			tgrp->used_mask |= BIT(values[idx]);
> +			set_bit(values[idx], tgrp->used_mask);
>   	}
>   
>   	kfree(values);
> @@ -316,23 +316,33 @@ static int cti_plat_process_filter_sigs(struct cti_drvdata *drvdata,
>   {
>   	struct cti_trig_grp *tg = NULL;
>   	int err = 0, nr_filter_sigs;
> +	int nr_trigs = drvdata->config.nr_trig_max;
>   
>   	nr_filter_sigs = cti_plat_count_sig_elements(fwnode,
>   						     CTI_DT_FILTER_OUT_SIGS);
>   	if (nr_filter_sigs == 0)
>   		return 0;
>   
> -	if (nr_filter_sigs > drvdata->config.nr_trig_max)
> +	if (nr_filter_sigs > nr_trigs)
>   		return -EINVAL;
>   
>   	tg = kzalloc_obj(*tg);
>   	if (!tg)
>   		return -ENOMEM;
>   
> +	tg->used_mask = bitmap_zalloc(nr_trigs, GFP_KERNEL);
> +	if (!tg->used_mask) {
> +		kfree(tg);
> +		return -ENOMEM;
> +	}
> +
>   	err = cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS);
>   	if (!err)
> -		drvdata->config.trig_out_filter |= tg->used_mask;
> +		bitmap_or(drvdata->config.trig_out_filter,
> +			  drvdata->config.trig_out_filter,
> +			  tg->used_mask, nr_trigs);

The error may be silently ignored when a memory allocation error 
occured. I think it's better to add a log print to tell user what happened.

Thanks,
Jie

>   
> +	bitmap_free(tg->used_mask);
>   	kfree(tg);
>   	return err;
>   }
> diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> index 3fe2c916d228..2bbfa405cb6b 100644
> --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> @@ -719,12 +719,12 @@ static ssize_t trigout_filtered_show(struct device *dev,
>   	struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
>   	struct cti_config *cfg = &drvdata->config;
>   	int nr_trig_max = cfg->nr_trig_max;
> -	unsigned long mask = cfg->trig_out_filter;
> +	unsigned long *mask = cfg->trig_out_filter;
>   
> -	if (mask == 0)
> +	if (bitmap_empty(mask, nr_trig_max))
>   		return 0;
>   
> -	return sysfs_emit(buf, "%*pbl\n", nr_trig_max, &mask);
> +	return sysfs_emit(buf, "%*pbl\n", nr_trig_max, mask);
>   }
>   static DEVICE_ATTR_RO(trigout_filtered);
>   
> @@ -931,9 +931,9 @@ static ssize_t trigin_sig_show(struct device *dev,
>   	struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
>   	struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
>   	struct cti_config *cfg = &drvdata->config;
> -	unsigned long mask = con->con_in->used_mask;
> +	unsigned long *mask = con->con_in->used_mask;
>   
> -	return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask);
> +	return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask);
>   }
>   
>   static ssize_t trigout_sig_show(struct device *dev,
> @@ -945,9 +945,9 @@ static ssize_t trigout_sig_show(struct device *dev,
>   	struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
>   	struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
>   	struct cti_config *cfg = &drvdata->config;
> -	unsigned long mask = con->con_out->used_mask;
> +	unsigned long *mask = con->con_out->used_mask;
>   
> -	return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask);
> +	return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask);
>   }
>   
>   /* convert a sig type id to a name */
> diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h
> index c5f9e79fabc6..ef079fc18b72 100644
> --- a/drivers/hwtracing/coresight/coresight-cti.h
> +++ b/drivers/hwtracing/coresight/coresight-cti.h
> @@ -68,7 +68,7 @@ struct fwnode_handle;
>    */
>   struct cti_trig_grp {
>   	int nr_sigs;
> -	u32 used_mask;
> +	unsigned long *used_mask;
>   	int sig_types[];
>   };
>   
> @@ -145,17 +145,17 @@ struct cti_config {
>   	int enable_req_count;
>   
>   	/* registered triggers and filtering */
> -	u32 trig_in_use;
> -	u32 trig_out_use;
> -	u32 trig_out_filter;
> +	unsigned long *trig_in_use;
> +	unsigned long *trig_out_use;
> +	unsigned long *trig_out_filter;
>   	bool trig_filter_enable;
>   	u8 xtrig_rchan_sel;
>   
>   	/* cti cross trig programmable regs */
>   	u32 ctiappset;
>   	u8 ctiinout_sel;
> -	u32 ctiinen[CTIINOUTEN_MAX];
> -	u32 ctiouten[CTIINOUTEN_MAX];
> +	u32 *ctiinen;
> +	u32 *ctiouten;
>   	u32 ctigate;
>   	u32 asicctl;
>   };
> 

Re: [PATCH v8 1/4] coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays

[Jie Gan]

On 4/27/2026 9:48 AM, Jie Gan wrote:
> 
> 
> On 4/26/2026 5:44 PM, Yingchao Deng wrote:
>> Replace the fixed-size u32 fields in the cti_config and cti_trig_grp
>> structure with dynamically allocated bitmaps and arrays. This allows
>> memory to be allocated based on the actual number of triggers during 
>> probe
>> time, reducing memory footprint and improving scalability for platforms
>> with varying trigger counts.
>>
>> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-cti-core.c   | 59 ++++++++++++ 
>> +++++-----
>>   .../hwtracing/coresight/coresight-cti-platform.c   | 26 +++++++---
>>   drivers/hwtracing/coresight/coresight-cti-sysfs.c  | 14 ++---
>>   drivers/hwtracing/coresight/coresight-cti.h        | 12 ++---
>>   4 files changed, 76 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/ 
>> drivers/hwtracing/coresight/coresight-cti-core.c
>> index 2f4c9362709a..4e7d12bd2d3e 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-cti-core.c
>> @@ -161,8 +161,8 @@ void cti_write_intack(struct device *dev, u32 ackval)
>>   /* DEVID[19:16] - number of CTM channels */
>>   #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 
>> 19))
>> -static void cti_set_default_config(struct device *dev,
>> -                   struct cti_drvdata *drvdata)
>> +static int cti_set_default_config(struct device *dev,
>> +                  struct cti_drvdata *drvdata)
>>   {
>>       struct cti_config *config = &drvdata->config;
>>       u32 devid;
>> @@ -181,6 +181,26 @@ static void cti_set_default_config(struct device 
>> *dev,
>>           config->nr_trig_max = CTIINOUTEN_MAX;
>>       }
>> +    config->trig_in_use = devm_bitmap_zalloc(dev, config- 
>> >nr_trig_max, GFP_KERNEL);
>> +    if (!config->trig_in_use)
>> +        return -ENOMEM;
>> +
>> +    config->trig_out_use = devm_bitmap_zalloc(dev, config- 
>> >nr_trig_max, GFP_KERNEL);
>> +    if (!config->trig_out_use)
>> +        return -ENOMEM;
>> +
>> +    config->trig_out_filter = devm_bitmap_zalloc(dev, config- 
>> >nr_trig_max, GFP_KERNEL);
>> +    if (!config->trig_out_filter)
>> +        return -ENOMEM;
>> +
>> +    config->ctiinen = devm_kcalloc(dev, config->nr_trig_max, 
>> sizeof(u32), GFP_KERNEL);
>> +    if (!config->ctiinen)
>> +        return -ENOMEM;
>> +
>> +    config->ctiouten = devm_kcalloc(dev, config->nr_trig_max, 
>> sizeof(u32), GFP_KERNEL);
>> +    if (!config->ctiouten)
>> +        return -ENOMEM;
>> +
>>       config->nr_ctm_channels = CTI_DEVID_CTMCHANNELS(devid);
>>       /* Most regs default to 0 as zalloc'ed except...*/
>> @@ -189,6 +209,7 @@ static void cti_set_default_config(struct device 
>> *dev,
>>       config->enable_req_count = 0;
>>       config->asicctl_impl = !!FIELD_GET(GENMASK(4, 0), devid);
>> +    return 0;
>>   }
>>   /*
>> @@ -219,8 +240,10 @@ int cti_add_connection_entry(struct device *dev, 
>> struct cti_drvdata *drvdata,
>>       cti_dev->nr_trig_con++;
>>       /* add connection usage bit info to overall info */
>> -    drvdata->config.trig_in_use |= tc->con_in->used_mask;
>> -    drvdata->config.trig_out_use |= tc->con_out->used_mask;
>> +    bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use,
>> +          tc->con_in->used_mask, drvdata->config.nr_trig_max);
>> +    bitmap_or(drvdata->config.trig_out_use, drvdata- 
>> >config.trig_out_use,
>> +          tc->con_out->used_mask, drvdata->config.nr_trig_max);
>>       return 0;
>>   }
>> @@ -231,6 +254,8 @@ struct cti_trig_con *cti_allocate_trig_con(struct 
>> device *dev, int in_sigs,
>>   {
>>       struct cti_trig_con *tc = NULL;
>>       struct cti_trig_grp *in = NULL, *out = NULL;
>> +    struct cti_drvdata *drvdata = dev_get_drvdata(dev);
>> +    int n_trigs = drvdata->config.nr_trig_max;
>>       tc = devm_kzalloc(dev, sizeof(struct cti_trig_con), GFP_KERNEL);
>>       if (!tc)
>> @@ -242,12 +267,20 @@ struct cti_trig_con 
>> *cti_allocate_trig_con(struct device *dev, int in_sigs,
>>       if (!in)
>>           return NULL;
>> +    in->used_mask = devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL);
>> +    if (!in->used_mask)
>> +        return NULL;
>> +
>>       out = devm_kzalloc(dev,
>>                  offsetof(struct cti_trig_grp, sig_types[out_sigs]),
>>                  GFP_KERNEL);
>>       if (!out)
>>           return NULL;
>> +    out->used_mask = devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL);
>> +    if (!out->used_mask)
>> +        return NULL;
>> +
>>       tc->con_in = in;
>>       tc->con_out = out;
>>       tc->con_in->nr_sigs = in_sigs;
>> @@ -263,7 +296,6 @@ int cti_add_default_connection(struct device *dev, 
>> struct cti_drvdata *drvdata)
>>   {
>>       int ret = 0;
>>       int n_trigs = drvdata->config.nr_trig_max;
>> -    u32 n_trig_mask = GENMASK(n_trigs - 1, 0);
>>       struct cti_trig_con *tc = NULL;
>>       /*
>> @@ -274,8 +306,8 @@ int cti_add_default_connection(struct device *dev, 
>> struct cti_drvdata *drvdata)
>>       if (!tc)
>>           return -ENOMEM;
>> -    tc->con_in->used_mask = n_trig_mask;
>> -    tc->con_out->used_mask = n_trig_mask;
>> +    bitmap_fill(tc->con_in->used_mask, n_trigs);
>> +    bitmap_fill(tc->con_out->used_mask, n_trigs);
>>       ret = cti_add_connection_entry(dev, drvdata, tc, NULL, "default");
>>       return ret;
>>   }
>> @@ -288,7 +320,6 @@ int cti_channel_trig_op(struct device *dev, enum 
>> cti_chan_op op,
>>   {
>>       struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
>>       struct cti_config *config = &drvdata->config;
>> -    u32 trig_bitmask;
>>       u32 chan_bitmask;
>>       u32 reg_value;
>>       int reg_offset;
>> @@ -298,18 +329,16 @@ int cti_channel_trig_op(struct device *dev, enum 
>> cti_chan_op op,
>>          (trigger_idx >= config->nr_trig_max))
>>           return -EINVAL;
>> -    trig_bitmask = BIT(trigger_idx);
>> -
>>       /* ensure registered triggers and not out filtered */
>>       if (direction == CTI_TRIG_IN)    {
>> -        if (!(trig_bitmask & config->trig_in_use))
>> +        if (!(test_bit(trigger_idx, config->trig_in_use)))
>>               return -EINVAL;
>>       } else {
>> -        if (!(trig_bitmask & config->trig_out_use))
>> +        if (!(test_bit(trigger_idx, config->trig_out_use)))
>>               return -EINVAL;
>>           if ((config->trig_filter_enable) &&
>> -            (config->trig_out_filter & trig_bitmask))
>> +            test_bit(trigger_idx, config->trig_out_filter))
>>               return -EINVAL;
>>       }
>> @@ -687,7 +716,9 @@ static int cti_probe(struct amba_device *adev, 
>> const struct amba_id *id)
>>       raw_spin_lock_init(&drvdata->spinlock);
>>       /* initialise CTI driver config values */
>> -    cti_set_default_config(dev, drvdata);
>> +    ret = cti_set_default_config(dev, drvdata);
>> +    if (ret)
>> +        return ret;
>>       pdata = coresight_cti_get_platform_data(dev);
>>       if (IS_ERR(pdata)) {
>> diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/ 
>> drivers/hwtracing/coresight/coresight-cti-platform.c
>> index 4eff96f48594..557debbc8ca4 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti-platform.c
>> +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c
>> @@ -136,8 +136,8 @@ static int 
>> cti_plat_create_v8_etm_connection(struct device *dev,
>>           goto create_v8_etm_out;
>>       /* build connection data */
>> -    tc->con_in->used_mask = 0xF0; /* sigs <4,5,6,7> */
>> -    tc->con_out->used_mask = 0xF0; /* sigs <4,5,6,7> */
>> +    bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */
>> +    bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */
>>       /*
>>        * The EXTOUT type signals from the ETM are connected to a set 
>> of input
>> @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct 
>> device *dev,
>>           goto of_create_v8_out;
>>       /* Set the v8 PE CTI connection data */
>> -    tc->con_in->used_mask = 0x3; /* sigs <0 1> */
>> +    bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */
>>       tc->con_in->sig_types[0] = PE_DBGTRIGGER;
>>       tc->con_in->sig_types[1] = PE_PMUIRQ;
>> -    tc->con_out->used_mask = 0x7; /* sigs <0 1 2 > */
>> +    bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */
>>       tc->con_out->sig_types[0] = PE_EDBGREQ;
>>       tc->con_out->sig_types[1] = PE_DBGRESTART;
>>       tc->con_out->sig_types[2] = PE_CTIIRQ;
>> @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct 
>> device *dev,
>>           goto of_create_v8_out;
>>       /* filter pe_edbgreq - PE trigout sig <0> */
>> -    drvdata->config.trig_out_filter |= 0x1;
>> +    set_bit(0, drvdata->config.trig_out_filter);
>>   of_create_v8_out:
>>       return ret;
>> @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct 
>> cti_trig_grp *tgrp,
>>       if (!err) {
>>           /* set the signal usage mask */
>>           for (idx = 0; idx < tgrp->nr_sigs; idx++)
>> -            tgrp->used_mask |= BIT(values[idx]);
>> +            set_bit(values[idx], tgrp->used_mask);
>>       }
>>       kfree(values);
>> @@ -316,23 +316,33 @@ static int cti_plat_process_filter_sigs(struct 
>> cti_drvdata *drvdata,
>>   {
>>       struct cti_trig_grp *tg = NULL;
>>       int err = 0, nr_filter_sigs;
>> +    int nr_trigs = drvdata->config.nr_trig_max;
>>       nr_filter_sigs = cti_plat_count_sig_elements(fwnode,
>>                                CTI_DT_FILTER_OUT_SIGS);
>>       if (nr_filter_sigs == 0)
>>           return 0;
>> -    if (nr_filter_sigs > drvdata->config.nr_trig_max)
>> +    if (nr_filter_sigs > nr_trigs)
>>           return -EINVAL;
>>       tg = kzalloc_obj(*tg);
>>       if (!tg)
>>           return -ENOMEM;
>> +    tg->used_mask = bitmap_zalloc(nr_trigs, GFP_KERNEL);
>> +    if (!tg->used_mask) {
>> +        kfree(tg);
>> +        return -ENOMEM;
>> +    }
>> +
>>       err = cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS);
>>       if (!err)
>> -        drvdata->config.trig_out_filter |= tg->used_mask;
>> +        bitmap_or(drvdata->config.trig_out_filter,
>> +              drvdata->config.trig_out_filter,
>> +              tg->used_mask, nr_trigs);
> 
> The error may be silently ignored when a memory allocation error 
> occured. I think it's better to add a log print to tell user what happened.

My fault here, please ignore this comment.
This error will be handled by probe fail process.

Thanks,
Jie


> 
> Thanks,
> Jie
> 
>> +    bitmap_free(tg->used_mask);
>>       kfree(tg);
>>       return err;
>>   }
>> diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/ 
>> drivers/hwtracing/coresight/coresight-cti-sysfs.c
>> index 3fe2c916d228..2bbfa405cb6b 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c
>> +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
>> @@ -719,12 +719,12 @@ static ssize_t trigout_filtered_show(struct 
>> device *dev,
>>       struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
>>       struct cti_config *cfg = &drvdata->config;
>>       int nr_trig_max = cfg->nr_trig_max;
>> -    unsigned long mask = cfg->trig_out_filter;
>> +    unsigned long *mask = cfg->trig_out_filter;
>> -    if (mask == 0)
>> +    if (bitmap_empty(mask, nr_trig_max))
>>           return 0;
>> -    return sysfs_emit(buf, "%*pbl\n", nr_trig_max, &mask);
>> +    return sysfs_emit(buf, "%*pbl\n", nr_trig_max, mask);
>>   }
>>   static DEVICE_ATTR_RO(trigout_filtered);
>> @@ -931,9 +931,9 @@ static ssize_t trigin_sig_show(struct device *dev,
>>       struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
>>       struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
>>       struct cti_config *cfg = &drvdata->config;
>> -    unsigned long mask = con->con_in->used_mask;
>> +    unsigned long *mask = con->con_in->used_mask;
>> -    return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask);
>> +    return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask);
>>   }
>>   static ssize_t trigout_sig_show(struct device *dev,
>> @@ -945,9 +945,9 @@ static ssize_t trigout_sig_show(struct device *dev,
>>       struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var;
>>       struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
>>       struct cti_config *cfg = &drvdata->config;
>> -    unsigned long mask = con->con_out->used_mask;
>> +    unsigned long *mask = con->con_out->used_mask;
>> -    return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask);
>> +    return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask);
>>   }
>>   /* convert a sig type id to a name */
>> diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/ 
>> hwtracing/coresight/coresight-cti.h
>> index c5f9e79fabc6..ef079fc18b72 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti.h
>> +++ b/drivers/hwtracing/coresight/coresight-cti.h
>> @@ -68,7 +68,7 @@ struct fwnode_handle;
>>    */
>>   struct cti_trig_grp {
>>       int nr_sigs;
>> -    u32 used_mask;
>> +    unsigned long *used_mask;
>>       int sig_types[];
>>   };
>> @@ -145,17 +145,17 @@ struct cti_config {
>>       int enable_req_count;
>>       /* registered triggers and filtering */
>> -    u32 trig_in_use;
>> -    u32 trig_out_use;
>> -    u32 trig_out_filter;
>> +    unsigned long *trig_in_use;
>> +    unsigned long *trig_out_use;
>> +    unsigned long *trig_out_filter;
>>       bool trig_filter_enable;
>>       u8 xtrig_rchan_sel;
>>       /* cti cross trig programmable regs */
>>       u32 ctiappset;
>>       u8 ctiinout_sel;
>> -    u32 ctiinen[CTIINOUTEN_MAX];
>> -    u32 ctiouten[CTIINOUTEN_MAX];
>> +    u32 *ctiinen;
>> +    u32 *ctiouten;
>>       u32 ctigate;
>>       u32 asicctl;
>>   };
>>
> 

Re: [PATCH v8 1/4] coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays

[Leo Yan]

On Sun, Apr 26, 2026 at 05:44:38PM +0800, Yingchao Deng wrote:

[...]

> @@ -316,23 +316,33 @@ static int cti_plat_process_filter_sigs(struct cti_drvdata *drvdata,
>  {
>  	struct cti_trig_grp *tg = NULL;
>  	int err = 0, nr_filter_sigs;
> +	int nr_trigs = drvdata->config.nr_trig_max;
>  
>  	nr_filter_sigs = cti_plat_count_sig_elements(fwnode,
>  						     CTI_DT_FILTER_OUT_SIGS);
>  	if (nr_filter_sigs == 0)
>  		return 0;
>  
> -	if (nr_filter_sigs > drvdata->config.nr_trig_max)
> +	if (nr_filter_sigs > nr_trigs)
>  		return -EINVAL;
>  
>  	tg = kzalloc_obj(*tg);
>  	if (!tg)
>  		return -ENOMEM;
>  
> +	tg->used_mask = bitmap_zalloc(nr_trigs, GFP_KERNEL);

Here would be:

  tg->used_mask = bitmap_zalloc(nr_filter_sigs, GFP_KERNEL);

> +	if (!tg->used_mask) {
> +		kfree(tg);
> +		return -ENOMEM;
> +	}
> +

It is likely this will have merge conflict with the new patch [1].

You might need to rebase this patch on the top of [1]. We need to
give [1] priority as it is a fix.

[1] https://lore.kernel.org/linux-arm-kernel/20260426-nr_sigs-v1-1-3b9df99dab97@oss.qualcomm.com/

Otherwise, LGTM:

Reviewed-by: Leo Yan <leo.yan@arm.com>

[PATCH v8 2/4] coresight: cti: encode trigger register index in register offsets

[Yingchao Deng]

Introduce a small encoding to carry the register index together with the
base offset in a single u32, and use a common helper to compute the final
MMIO address. This refactors register access to be based on the encoded
(reg, nr) pair, reducing duplicated arithmetic and making it easier to
support variants that bank or relocate trigger-indexed registers.

Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
---
 drivers/hwtracing/coresight/coresight-cti-core.c  | 31 +++++++++++++++--------
 drivers/hwtracing/coresight/coresight-cti-sysfs.c |  4 +--
 drivers/hwtracing/coresight/coresight-cti.h       | 16 ++++++++++--
 3 files changed, 36 insertions(+), 15 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c
index 4e7d12bd2d3e..c4cbeb64365b 100644
--- a/drivers/hwtracing/coresight/coresight-cti-core.c
+++ b/drivers/hwtracing/coresight/coresight-cti-core.c
@@ -42,6 +42,14 @@ static DEFINE_MUTEX(ect_mutex);
 #define csdev_to_cti_drvdata(csdev)	\
 	dev_get_drvdata(csdev->dev.parent)
 
+static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg)
+{
+	u32 offset = CTI_REG_CLR_NR(reg);
+	u32 nr = CTI_REG_GET_NR(reg);
+
+	return drvdata->base + offset + sizeof(u32) * nr;
+}
+
 /* write set of regs to hardware - call with spinlock claimed */
 void cti_write_all_hw_regs(struct cti_drvdata *drvdata)
 {
@@ -55,16 +63,17 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata)
 
 	/* write the CTI trigger registers */
 	for (i = 0; i < config->nr_trig_max; i++) {
-		writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i));
+		writel_relaxed(config->ctiinen[i],
+			       cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIINEN, i)));
 		writel_relaxed(config->ctiouten[i],
-			       drvdata->base + CTIOUTEN(i));
+			       cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIOUTEN, i)));
 	}
 
 	/* other regs */
-	writel_relaxed(config->ctigate, drvdata->base + CTIGATE);
+	writel_relaxed(config->ctigate, cti_reg_addr(drvdata, CTIGATE));
 	if (config->asicctl_impl)
-		writel_relaxed(config->asicctl, drvdata->base + ASICCTL);
-	writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET);
+		writel_relaxed(config->asicctl, cti_reg_addr(drvdata, ASICCTL));
+	writel_relaxed(config->ctiappset, cti_reg_addr(drvdata, CTIAPPSET));
 
 	/* re-enable CTI */
 	writel_relaxed(1, drvdata->base + CTICONTROL);
@@ -127,7 +136,7 @@ u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset)
 	int val;
 
 	CS_UNLOCK(drvdata->base);
-	val = readl_relaxed(drvdata->base + offset);
+	val = readl_relaxed(cti_reg_addr(drvdata, offset));
 	CS_LOCK(drvdata->base);
 
 	return val;
@@ -136,7 +145,7 @@ u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset)
 void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value)
 {
 	CS_UNLOCK(drvdata->base);
-	writel_relaxed(value, drvdata->base + offset);
+	writel_relaxed(value, cti_reg_addr(drvdata, offset));
 	CS_LOCK(drvdata->base);
 }
 
@@ -344,8 +353,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,
 
 	/* update the local register values */
 	chan_bitmask = BIT(channel_idx);
-	reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) :
-		      CTIOUTEN(trigger_idx));
+	reg_offset = (direction == CTI_TRIG_IN ? CTIINEN : CTIOUTEN);
 
 	guard(raw_spinlock_irqsave)(&drvdata->spinlock);
 
@@ -365,8 +373,9 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,
 
 	/* write through if enabled */
 	if (cti_is_active(config))
-		cti_write_single_reg(drvdata, reg_offset, reg_value);
-
+		cti_write_single_reg(drvdata,
+				     CTI_REG_SET_NR(reg_offset, trigger_idx),
+				     reg_value);
 	return 0;
 }
 
diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
index 2bbfa405cb6b..8b70e7e38ea3 100644
--- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
@@ -386,7 +386,7 @@ static ssize_t inen_store(struct device *dev,
 
 	/* write through if enabled */
 	if (cti_is_active(config))
-		cti_write_single_reg(drvdata, CTIINEN(index), val);
+		cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIINEN, index), val);
 
 	return size;
 }
@@ -427,7 +427,7 @@ static ssize_t outen_store(struct device *dev,
 
 	/* write through if enabled */
 	if (cti_is_active(config))
-		cti_write_single_reg(drvdata, CTIOUTEN(index), val);
+		cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIOUTEN, index), val);
 
 	return size;
 }
diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h
index ef079fc18b72..dd1ba44518c4 100644
--- a/drivers/hwtracing/coresight/coresight-cti.h
+++ b/drivers/hwtracing/coresight/coresight-cti.h
@@ -7,6 +7,7 @@
 #ifndef _CORESIGHT_CORESIGHT_CTI_H
 #define _CORESIGHT_CORESIGHT_CTI_H
 
+#include <linux/bitfield.h>
 #include <linux/coresight.h>
 #include <linux/device.h>
 #include <linux/list.h>
@@ -30,8 +31,8 @@ struct fwnode_handle;
 #define CTIAPPSET		0x014
 #define CTIAPPCLEAR		0x018
 #define CTIAPPPULSE		0x01C
-#define CTIINEN(n)		(0x020 + (4 * n))
-#define CTIOUTEN(n)		(0x0A0 + (4 * n))
+#define CTIINEN			0x020
+#define CTIOUTEN		0x0A0
 #define CTITRIGINSTATUS		0x130
 #define CTITRIGOUTSTATUS	0x134
 #define CTICHINSTATUS		0x138
@@ -59,6 +60,17 @@ struct fwnode_handle;
  */
 #define CTIINOUTEN_MAX		32
 
+/*
+ * Encode CTI register offset and register index in one u32:
+ *   - bits[0:11]  : base register offset (0x000 to 0xFFF)
+ *   - bits[24:31] : register index (nr)
+ */
+#define CTI_REG_NR_MASK			GENMASK(31, 24)
+#define CTI_REG_GET_NR(reg)		FIELD_GET(CTI_REG_NR_MASK, (reg))
+#define CTI_REG_SET_NR_CONST(reg, nr)	((reg) | FIELD_PREP_CONST(CTI_REG_NR_MASK, (nr)))
+#define CTI_REG_SET_NR(reg, nr)		((reg) | FIELD_PREP(CTI_REG_NR_MASK, (nr)))
+#define CTI_REG_CLR_NR(reg)		((reg) & (~CTI_REG_NR_MASK))
+
 /**
  * Group of related trigger signals
  *

-- 
2.43.0

Re: [PATCH v8 2/4] coresight: cti: encode trigger register index in register offsets

[Jie Gan]

On 4/26/2026 5:44 PM, Yingchao Deng wrote:
> Introduce a small encoding to carry the register index together with the
> base offset in a single u32, and use a common helper to compute the final
> MMIO address. This refactors register access to be based on the encoded
> (reg, nr) pair, reducing duplicated arithmetic and making it easier to
> support variants that bank or relocate trigger-indexed registers.
> 
> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> ---
>   drivers/hwtracing/coresight/coresight-cti-core.c  | 31 +++++++++++++++--------
>   drivers/hwtracing/coresight/coresight-cti-sysfs.c |  4 +--
>   drivers/hwtracing/coresight/coresight-cti.h       | 16 ++++++++++--
>   3 files changed, 36 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c
> index 4e7d12bd2d3e..c4cbeb64365b 100644
> --- a/drivers/hwtracing/coresight/coresight-cti-core.c
> +++ b/drivers/hwtracing/coresight/coresight-cti-core.c
> @@ -42,6 +42,14 @@ static DEFINE_MUTEX(ect_mutex);
>   #define csdev_to_cti_drvdata(csdev)	\
>   	dev_get_drvdata(csdev->dev.parent)
>   
> +static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg)

u32 reg would be better.

> +{
> +	u32 offset = CTI_REG_CLR_NR(reg);

No functional error but a little bit tricky here.

CTI_REG_CLR_NR(reg) will produce a offset for the bits[0:23], but in the 
comment, you mentioned the base register offset ranges from [0:11].

With my understanding, all CTI register offsets fall within the range b 
0 to 0XFAC, that's why we have bits[0:11]?

Thanks,
Jie

> +	u32 nr = CTI_REG_GET_NR(reg);
> +
> +	return drvdata->base + offset + sizeof(u32) * nr;
> +}
> +
>   /* write set of regs to hardware - call with spinlock claimed */
>   void cti_write_all_hw_regs(struct cti_drvdata *drvdata)
>   {
> @@ -55,16 +63,17 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata)
>   
>   	/* write the CTI trigger registers */
>   	for (i = 0; i < config->nr_trig_max; i++) {
> -		writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i));
> +		writel_relaxed(config->ctiinen[i],
> +			       cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIINEN, i)));
>   		writel_relaxed(config->ctiouten[i],
> -			       drvdata->base + CTIOUTEN(i));
> +			       cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIOUTEN, i)));
>   	}
>   
>   	/* other regs */
> -	writel_relaxed(config->ctigate, drvdata->base + CTIGATE);
> +	writel_relaxed(config->ctigate, cti_reg_addr(drvdata, CTIGATE));
>   	if (config->asicctl_impl)
> -		writel_relaxed(config->asicctl, drvdata->base + ASICCTL);
> -	writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET);
> +		writel_relaxed(config->asicctl, cti_reg_addr(drvdata, ASICCTL));
> +	writel_relaxed(config->ctiappset, cti_reg_addr(drvdata, CTIAPPSET));
>   
>   	/* re-enable CTI */
>   	writel_relaxed(1, drvdata->base + CTICONTROL);
> @@ -127,7 +136,7 @@ u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset)
>   	int val;
>   
>   	CS_UNLOCK(drvdata->base);
> -	val = readl_relaxed(drvdata->base + offset);
> +	val = readl_relaxed(cti_reg_addr(drvdata, offset));
>   	CS_LOCK(drvdata->base);
>   
>   	return val;
> @@ -136,7 +145,7 @@ u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset)
>   void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value)
>   {
>   	CS_UNLOCK(drvdata->base);
> -	writel_relaxed(value, drvdata->base + offset);
> +	writel_relaxed(value, cti_reg_addr(drvdata, offset));
>   	CS_LOCK(drvdata->base);
>   }
>   
> @@ -344,8 +353,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,
>   
>   	/* update the local register values */
>   	chan_bitmask = BIT(channel_idx);
> -	reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) :
> -		      CTIOUTEN(trigger_idx));
> +	reg_offset = (direction == CTI_TRIG_IN ? CTIINEN : CTIOUTEN);
>   
>   	guard(raw_spinlock_irqsave)(&drvdata->spinlock);
>   
> @@ -365,8 +373,9 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op,
>   
>   	/* write through if enabled */
>   	if (cti_is_active(config))
> -		cti_write_single_reg(drvdata, reg_offset, reg_value);
> -
> +		cti_write_single_reg(drvdata,
> +				     CTI_REG_SET_NR(reg_offset, trigger_idx),
> +				     reg_value);
>   	return 0;
>   }
>   
> diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> index 2bbfa405cb6b..8b70e7e38ea3 100644
> --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> @@ -386,7 +386,7 @@ static ssize_t inen_store(struct device *dev,
>   
>   	/* write through if enabled */
>   	if (cti_is_active(config))
> -		cti_write_single_reg(drvdata, CTIINEN(index), val);
> +		cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIINEN, index), val);
>   
>   	return size;
>   }
> @@ -427,7 +427,7 @@ static ssize_t outen_store(struct device *dev,
>   
>   	/* write through if enabled */
>   	if (cti_is_active(config))
> -		cti_write_single_reg(drvdata, CTIOUTEN(index), val);
> +		cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIOUTEN, index), val);
>   
>   	return size;
>   }
> diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h
> index ef079fc18b72..dd1ba44518c4 100644
> --- a/drivers/hwtracing/coresight/coresight-cti.h
> +++ b/drivers/hwtracing/coresight/coresight-cti.h
> @@ -7,6 +7,7 @@
>   #ifndef _CORESIGHT_CORESIGHT_CTI_H
>   #define _CORESIGHT_CORESIGHT_CTI_H
>   
> +#include <linux/bitfield.h>
>   #include <linux/coresight.h>
>   #include <linux/device.h>
>   #include <linux/list.h>
> @@ -30,8 +31,8 @@ struct fwnode_handle;
>   #define CTIAPPSET		0x014
>   #define CTIAPPCLEAR		0x018
>   #define CTIAPPPULSE		0x01C
> -#define CTIINEN(n)		(0x020 + (4 * n))
> -#define CTIOUTEN(n)		(0x0A0 + (4 * n))
> +#define CTIINEN			0x020
> +#define CTIOUTEN		0x0A0
>   #define CTITRIGINSTATUS		0x130
>   #define CTITRIGOUTSTATUS	0x134
>   #define CTICHINSTATUS		0x138
> @@ -59,6 +60,17 @@ struct fwnode_handle;
>    */
>   #define CTIINOUTEN_MAX		32
>   
> +/*
> + * Encode CTI register offset and register index in one u32:
> + *   - bits[0:11]  : base register offset (0x000 to 0xFFF)
> + *   - bits[24:31] : register index (nr)
> + */
> +#define CTI_REG_NR_MASK			GENMASK(31, 24)
> +#define CTI_REG_GET_NR(reg)		FIELD_GET(CTI_REG_NR_MASK, (reg))
> +#define CTI_REG_SET_NR_CONST(reg, nr)	((reg) | FIELD_PREP_CONST(CTI_REG_NR_MASK, (nr)))
> +#define CTI_REG_SET_NR(reg, nr)		((reg) | FIELD_PREP(CTI_REG_NR_MASK, (nr)))
> +#define CTI_REG_CLR_NR(reg)		((reg) & (~CTI_REG_NR_MASK))
> +
>   /**
>    * Group of related trigger signals
>    *
> 

Re: [PATCH v8 2/4] coresight: cti: encode trigger register index in register offsets

[Yingchao Deng (Consultant)]

On 4/27/2026 10:22 AM, Jie Gan wrote:
>
>
> On 4/26/2026 5:44 PM, Yingchao Deng wrote:
>> Introduce a small encoding to carry the register index together with the
>> base offset in a single u32, and use a common helper to compute the 
>> final
>> MMIO address. This refactors register access to be based on the encoded
>> (reg, nr) pair, reducing duplicated arithmetic and making it easier to
>> support variants that bank or relocate trigger-indexed registers.
>>
>> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-cti-core.c  | 31 
>> +++++++++++++++--------
>>   drivers/hwtracing/coresight/coresight-cti-sysfs.c |  4 +--
>>   drivers/hwtracing/coresight/coresight-cti.h       | 16 ++++++++++--
>>   3 files changed, 36 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c 
>> b/drivers/hwtracing/coresight/coresight-cti-core.c
>> index 4e7d12bd2d3e..c4cbeb64365b 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-cti-core.c
>> @@ -42,6 +42,14 @@ static DEFINE_MUTEX(ect_mutex);
>>   #define csdev_to_cti_drvdata(csdev)    \
>>       dev_get_drvdata(csdev->dev.parent)
>>   +static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int 
>> reg)
>
> u32 reg would be better.
>
>> +{
>> +    u32 offset = CTI_REG_CLR_NR(reg);
>
> No functional error but a little bit tricky here.
>
> CTI_REG_CLR_NR(reg) will produce a offset for the bits[0:23], but in 
> the comment, you mentioned the base register offset ranges from [0:11].
>
> With my understanding, all CTI register offsets fall within the range 
> b 0 to 0XFAC, that's why we have bits[0:11]?
>
> Thanks,
> Jie
   Thanks for the review.
  While current CoreSight components fit within a single 4KB
   block, IHI0029 states that a component can occupy up to 64MB (16,384
   x 4KB blocks), requiring up to 26 bits for the offset. I will change
   CTI_REG_NR_MASK to GENMASK(31, 28) to avoid any potential conflict
   with bits[24:25].


Thanks,
Yingchao
>> +    u32 nr = CTI_REG_GET_NR(reg);
>> +
>> +    return drvdata->base + offset + sizeof(u32) * nr;
>> +}
>> +
>>   /* write set of regs to hardware - call with spinlock claimed */
>>   void cti_write_all_hw_regs(struct cti_drvdata *drvdata)
>>   {
>> @@ -55,16 +63,17 @@ void cti_write_all_hw_regs(struct cti_drvdata 
>> *drvdata)
>>         /* write the CTI trigger registers */
>>       for (i = 0; i < config->nr_trig_max; i++) {
>> -        writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i));
>> +        writel_relaxed(config->ctiinen[i],
>> +                   cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIINEN, i)));
>>           writel_relaxed(config->ctiouten[i],
>> -                   drvdata->base + CTIOUTEN(i));
>> +                   cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIOUTEN, i)));
>>       }
>>         /* other regs */
>> -    writel_relaxed(config->ctigate, drvdata->base + CTIGATE);
>> +    writel_relaxed(config->ctigate, cti_reg_addr(drvdata, CTIGATE));
>>       if (config->asicctl_impl)
>> -        writel_relaxed(config->asicctl, drvdata->base + ASICCTL);
>> -    writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET);
>> +        writel_relaxed(config->asicctl, cti_reg_addr(drvdata, 
>> ASICCTL));
>> +    writel_relaxed(config->ctiappset, cti_reg_addr(drvdata, 
>> CTIAPPSET));
>>         /* re-enable CTI */
>>       writel_relaxed(1, drvdata->base + CTICONTROL);
>> @@ -127,7 +136,7 @@ u32 cti_read_single_reg(struct cti_drvdata 
>> *drvdata, int offset)
>>       int val;
>>         CS_UNLOCK(drvdata->base);
>> -    val = readl_relaxed(drvdata->base + offset);
>> +    val = readl_relaxed(cti_reg_addr(drvdata, offset));
>>       CS_LOCK(drvdata->base);
>>         return val;
>> @@ -136,7 +145,7 @@ u32 cti_read_single_reg(struct cti_drvdata 
>> *drvdata, int offset)
>>   void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, 
>> u32 value)
>>   {
>>       CS_UNLOCK(drvdata->base);
>> -    writel_relaxed(value, drvdata->base + offset);
>> +    writel_relaxed(value, cti_reg_addr(drvdata, offset));
>>       CS_LOCK(drvdata->base);
>>   }
>>   @@ -344,8 +353,7 @@ int cti_channel_trig_op(struct device *dev, 
>> enum cti_chan_op op,
>>         /* update the local register values */
>>       chan_bitmask = BIT(channel_idx);
>> -    reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) :
>> -              CTIOUTEN(trigger_idx));
>> +    reg_offset = (direction == CTI_TRIG_IN ? CTIINEN : CTIOUTEN);
>>         guard(raw_spinlock_irqsave)(&drvdata->spinlock);
>>   @@ -365,8 +373,9 @@ int cti_channel_trig_op(struct device *dev, 
>> enum cti_chan_op op,
>>         /* write through if enabled */
>>       if (cti_is_active(config))
>> -        cti_write_single_reg(drvdata, reg_offset, reg_value);
>> -
>> +        cti_write_single_reg(drvdata,
>> +                     CTI_REG_SET_NR(reg_offset, trigger_idx),
>> +                     reg_value);
>>       return 0;
>>   }
>>   diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c 
>> b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
>> index 2bbfa405cb6b..8b70e7e38ea3 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c
>> +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
>> @@ -386,7 +386,7 @@ static ssize_t inen_store(struct device *dev,
>>         /* write through if enabled */
>>       if (cti_is_active(config))
>> -        cti_write_single_reg(drvdata, CTIINEN(index), val);
>> +        cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIINEN, 
>> index), val);
>>         return size;
>>   }
>> @@ -427,7 +427,7 @@ static ssize_t outen_store(struct device *dev,
>>         /* write through if enabled */
>>       if (cti_is_active(config))
>> -        cti_write_single_reg(drvdata, CTIOUTEN(index), val);
>> +        cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIOUTEN, 
>> index), val);
>>         return size;
>>   }
>> diff --git a/drivers/hwtracing/coresight/coresight-cti.h 
>> b/drivers/hwtracing/coresight/coresight-cti.h
>> index ef079fc18b72..dd1ba44518c4 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti.h
>> +++ b/drivers/hwtracing/coresight/coresight-cti.h
>> @@ -7,6 +7,7 @@
>>   #ifndef _CORESIGHT_CORESIGHT_CTI_H
>>   #define _CORESIGHT_CORESIGHT_CTI_H
>>   +#include <linux/bitfield.h>
>>   #include <linux/coresight.h>
>>   #include <linux/device.h>
>>   #include <linux/list.h>
>> @@ -30,8 +31,8 @@ struct fwnode_handle;
>>   #define CTIAPPSET        0x014
>>   #define CTIAPPCLEAR        0x018
>>   #define CTIAPPPULSE        0x01C
>> -#define CTIINEN(n)        (0x020 + (4 * n))
>> -#define CTIOUTEN(n)        (0x0A0 + (4 * n))
>> +#define CTIINEN            0x020
>> +#define CTIOUTEN        0x0A0
>>   #define CTITRIGINSTATUS        0x130
>>   #define CTITRIGOUTSTATUS    0x134
>>   #define CTICHINSTATUS        0x138
>> @@ -59,6 +60,17 @@ struct fwnode_handle;
>>    */
>>   #define CTIINOUTEN_MAX        32
>>   +/*
>> + * Encode CTI register offset and register index in one u32:
>> + *   - bits[0:11]  : base register offset (0x000 to 0xFFF)
>> + *   - bits[24:31] : register index (nr)
>> + */
>> +#define CTI_REG_NR_MASK            GENMASK(31, 24)
>> +#define CTI_REG_GET_NR(reg)        FIELD_GET(CTI_REG_NR_MASK, (reg))
>> +#define CTI_REG_SET_NR_CONST(reg, nr)    ((reg) | 
>> FIELD_PREP_CONST(CTI_REG_NR_MASK, (nr)))
>> +#define CTI_REG_SET_NR(reg, nr)        ((reg) | 
>> FIELD_PREP(CTI_REG_NR_MASK, (nr)))
>> +#define CTI_REG_CLR_NR(reg)        ((reg) & (~CTI_REG_NR_MASK))
>> +
>>   /**
>>    * Group of related trigger signals
>>    *
>>
>

Re: [PATCH v8 2/4] coresight: cti: encode trigger register index in register offsets

[Leo Yan]

On Sun, Apr 26, 2026 at 05:44:39PM +0800, Yingchao Deng wrote:
> Introduce a small encoding to carry the register index together with the
> base offset in a single u32, and use a common helper to compute the final
> MMIO address. This refactors register access to be based on the encoded
> (reg, nr) pair, reducing duplicated arithmetic and making it easier to
> support variants that bank or relocate trigger-indexed registers.
> 
> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> ---
>  drivers/hwtracing/coresight/coresight-cti-core.c  | 31 +++++++++++++++--------
>  drivers/hwtracing/coresight/coresight-cti-sysfs.c |  4 +--
>  drivers/hwtracing/coresight/coresight-cti.h       | 16 ++++++++++--
>  3 files changed, 36 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c
> index 4e7d12bd2d3e..c4cbeb64365b 100644
> --- a/drivers/hwtracing/coresight/coresight-cti-core.c
> +++ b/drivers/hwtracing/coresight/coresight-cti-core.c
> @@ -42,6 +42,14 @@ static DEFINE_MUTEX(ect_mutex);
>  #define csdev_to_cti_drvdata(csdev)	\
>  	dev_get_drvdata(csdev->dev.parent)
>  
> +static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg)
> +{
> +	u32 offset = CTI_REG_CLR_NR(reg);
> +	u32 nr = CTI_REG_GET_NR(reg);
> +
> +	return drvdata->base + offset + sizeof(u32) * nr;
> +}

Could you try below change, which is more straightforward?

  static void __iomem *__reg_addr(struct cti_drvdata *drvdata, int off,
                                  int index)
  {
  	return drvdata->base + offset + sizeof(u32) * index;
  }

  #define reg_addr(drvdata, off)                 \
        __reg_addr((drvdata), (off), 0)

  #define reg_index_addr(drvdata, off, i)        \
        __reg_addr((drvdata), (off), (i))

> +
>  /* write set of regs to hardware - call with spinlock claimed */
>  void cti_write_all_hw_regs(struct cti_drvdata *drvdata)
>  {
> @@ -55,16 +63,17 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata)
>  
>  	/* write the CTI trigger registers */
>  	for (i = 0; i < config->nr_trig_max; i++) {
> -		writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i));
> +		writel_relaxed(config->ctiinen[i],
> +			       cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIINEN, i)));

                writel_relaxed(config->ctiinen[i],
                               reg_index_addr(drvdata, CTIINEN, i));

>  		writel_relaxed(config->ctiouten[i],
> -			       drvdata->base + CTIOUTEN(i));
> +			       cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIOUTEN, i)));

                writel_relaxed(config->ctiouten[i],
                               reg_index_addr(drvdata, CTIOUTEN, i));

[...]

> +/*
> + * Encode CTI register offset and register index in one u32:
> + *   - bits[0:11]  : base register offset (0x000 to 0xFFF)
> + *   - bits[24:31] : register index (nr)
> + */
> +#define CTI_REG_NR_MASK			GENMASK(31, 24)
> +#define CTI_REG_GET_NR(reg)		FIELD_GET(CTI_REG_NR_MASK, (reg))
> +#define CTI_REG_SET_NR_CONST(reg, nr)	((reg) | FIELD_PREP_CONST(CTI_REG_NR_MASK, (nr)))
> +#define CTI_REG_SET_NR(reg, nr)		((reg) | FIELD_PREP(CTI_REG_NR_MASK, (nr)))
> +#define CTI_REG_CLR_NR(reg)		((reg) & (~CTI_REG_NR_MASK))

I know this might come from my suggestion, and it is also will be
heavily used in patch 04.  We can have strightforward way to
implement this, please drop these macros.

I will reply in patch 04 separately.  Sorry my review might cause
extra effort.

Thanks,
Leo

[PATCH v8 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks

[Yingchao Deng]

Qualcomm implements an extended variant of the ARM CoreSight CTI with a
different register layout and vendor-specific behavior. While the
programming model remains largely compatible, the register offsets differ
from the standard ARM CTI and require explicit handling.

Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI
driver data. Introduce a small mapping layer to translate standard CTI
register offsets to Qualcomm-specific offsets, allowing the rest of the
driver to use a common register access path.

Additionally, handle a Qualcomm-specific quirk where the CLAIMSET
register is incorrectly initialized to a non-zero value, which can cause
tools or drivers to assume the component is already claimed. Clear the
register during probe to reflect the actual unclaimed state.

No functional change is intended for standard ARM CTI devices.

Co-developed-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
Signed-off-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
---
 drivers/hwtracing/coresight/coresight-cti-core.c | 28 +++++++++-
 drivers/hwtracing/coresight/coresight-cti.h      |  4 +-
 drivers/hwtracing/coresight/qcom-cti.h           | 65 ++++++++++++++++++++++++
 3 files changed, 95 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c
index c4cbeb64365b..b1c69a3e9b99 100644
--- a/drivers/hwtracing/coresight/coresight-cti-core.c
+++ b/drivers/hwtracing/coresight/coresight-cti-core.c
@@ -21,6 +21,7 @@
 
 #include "coresight-priv.h"
 #include "coresight-cti.h"
+#include "qcom-cti.h"
 
 /*
  * CTI devices can be associated with a PE, or be connected to CoreSight
@@ -47,6 +48,10 @@ static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg)
 	u32 offset = CTI_REG_CLR_NR(reg);
 	u32 nr = CTI_REG_GET_NR(reg);
 
+	/* convert to qcom specific offset */
+	if (unlikely(drvdata->is_qcom_cti))
+		offset = cti_qcom_reg_off(offset);
+
 	return drvdata->base + offset + sizeof(u32) * nr;
 }
 
@@ -170,6 +175,9 @@ void cti_write_intack(struct device *dev, u32 ackval)
 /* DEVID[19:16] - number of CTM channels */
 #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19))
 
+/* DEVARCH[31:21] - ARCHITECT */
+#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31))
+
 static int cti_set_default_config(struct device *dev,
 				  struct cti_drvdata *drvdata)
 {
@@ -700,6 +708,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
 	struct coresight_desc cti_desc;
 	struct coresight_platform_data *pdata = NULL;
 	struct resource *res = &adev->res;
+	u32 devarch;
 
 	/* driver data*/
 	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
@@ -724,6 +733,22 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
 
 	raw_spin_lock_init(&drvdata->spinlock);
 
+	devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH);
+	if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) {
+		drvdata->is_qcom_cti = true;
+		/*
+		 * QCOM CTI does not implement Claimtag functionality as
+		 * per CoreSight specification, but its CLAIMSET register
+		 * is incorrectly initialized to 0xF. This can mislead
+		 * tools or drivers into thinking the component is claimed.
+		 *
+		 * Reset CLAIMSET to 0 to reflect that no claims are active.
+		 */
+		CS_UNLOCK(drvdata->base);
+		writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET);
+		CS_LOCK(drvdata->base);
+	}
+
 	/* initialise CTI driver config values */
 	ret = cti_set_default_config(dev, drvdata);
 	if (ret)
@@ -780,7 +805,8 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
 
 	/* all done - dec pm refcount */
 	pm_runtime_put(&adev->dev);
-	dev_info(&drvdata->csdev->dev, "CTI initialized\n");
+	dev_info(&drvdata->csdev->dev,
+		 "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : "");
 	return 0;
 }
 
diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h
index dd1ba44518c4..2598601e7b93 100644
--- a/drivers/hwtracing/coresight/coresight-cti.h
+++ b/drivers/hwtracing/coresight/coresight-cti.h
@@ -55,10 +55,11 @@ struct fwnode_handle;
 /*
  * CTI CSSoc 600 has a max of 32 trigger signals per direction.
  * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def.
+ * QCOM CTI supports up to 128 trigger signals per direction.
  * Max of in and out defined in the DEVID register.
  * - pick up actual number used from .dts parameters if present.
  */
-#define CTIINOUTEN_MAX		32
+#define CTIINOUTEN_MAX		128
 
 /*
  * Encode CTI register offset and register index in one u32:
@@ -188,6 +189,7 @@ struct cti_drvdata {
 	raw_spinlock_t spinlock;
 	struct cti_config config;
 	struct list_head node;
+	bool is_qcom_cti;
 };
 
 /*
diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h
new file mode 100644
index 000000000000..fd1bf07d7cb4
--- /dev/null
+++ b/drivers/hwtracing/coresight/qcom-cti.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _CORESIGHT_QCOM_CTI_H
+#define _CORESIGHT_QCOM_CTI_H
+
+#include "coresight-cti.h"
+
+#define ARCHITECT_QCOM 0x477
+
+/* CTI programming registers */
+#define QCOM_CTIINTACK		0x020
+#define QCOM_CTIAPPSET		0x004
+#define QCOM_CTIAPPCLEAR	0x008
+#define QCOM_CTIAPPPULSE	0x00C
+#define QCOM_CTIINEN		0x400
+#define QCOM_CTIOUTEN		0x800
+#define QCOM_CTITRIGINSTATUS	0x040
+#define QCOM_CTITRIGOUTSTATUS	0x060
+#define QCOM_CTICHINSTATUS	0x080
+#define QCOM_CTICHOUTSTATUS	0x084
+#define QCOM_CTIGATE		0x088
+#define QCOM_ASICCTL		0x08C
+/* Integration test registers */
+#define QCOM_ITCHINACK		0xE70
+#define QCOM_ITTRIGINACK	0xE80
+#define QCOM_ITCHOUT		0xE74
+#define QCOM_ITTRIGOUT		0xEA0
+#define QCOM_ITCHOUTACK		0xE78
+#define QCOM_ITTRIGOUTACK	0xEC0
+#define QCOM_ITCHIN		0xE7C
+#define QCOM_ITTRIGIN		0xEE0
+
+static noinline u32 cti_qcom_reg_off(u32 offset)
+{
+	switch (offset) {
+	case CTIINTACK:		return QCOM_CTIINTACK;
+	case CTIAPPSET:		return QCOM_CTIAPPSET;
+	case CTIAPPCLEAR:	return QCOM_CTIAPPCLEAR;
+	case CTIAPPPULSE:	return QCOM_CTIAPPPULSE;
+	case CTIINEN:		return QCOM_CTIINEN;
+	case CTIOUTEN:		return QCOM_CTIOUTEN;
+	case CTITRIGINSTATUS:	return QCOM_CTITRIGINSTATUS;
+	case CTITRIGOUTSTATUS:	return QCOM_CTITRIGOUTSTATUS;
+	case CTICHINSTATUS:	return QCOM_CTICHINSTATUS;
+	case CTICHOUTSTATUS:	return QCOM_CTICHOUTSTATUS;
+	case CTIGATE:		return QCOM_CTIGATE;
+	case ASICCTL:		return QCOM_ASICCTL;
+	case ITCHINACK:		return QCOM_ITCHINACK;
+	case ITTRIGINACK:	return QCOM_ITTRIGINACK;
+	case ITCHOUT:		return QCOM_ITCHOUT;
+	case ITTRIGOUT:		return QCOM_ITTRIGOUT;
+	case ITCHOUTACK:	return QCOM_ITCHOUTACK;
+	case ITTRIGOUTACK:	return QCOM_ITTRIGOUTACK;
+	case ITCHIN:		return QCOM_ITCHIN;
+	case ITTRIGIN:		return QCOM_ITTRIGIN;
+
+	default:
+		return offset;
+	}
+}
+
+#endif  /* _CORESIGHT_QCOM_CTI_H */

-- 
2.43.0

Re: [PATCH v8 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks

[Jie Gan]

On 4/26/2026 5:44 PM, Yingchao Deng wrote:
> Qualcomm implements an extended variant of the ARM CoreSight CTI with a
> different register layout and vendor-specific behavior. While the
> programming model remains largely compatible, the register offsets differ
> from the standard ARM CTI and require explicit handling.
> 
> Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI
> driver data. Introduce a small mapping layer to translate standard CTI
> register offsets to Qualcomm-specific offsets, allowing the rest of the
> driver to use a common register access path.
> 
> Additionally, handle a Qualcomm-specific quirk where the CLAIMSET
> register is incorrectly initialized to a non-zero value, which can cause
> tools or drivers to assume the component is already claimed. Clear the
> register during probe to reflect the actual unclaimed state.
> 
> No functional change is intended for standard ARM CTI devices.
> 
> Co-developed-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> Signed-off-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> ---
>   drivers/hwtracing/coresight/coresight-cti-core.c | 28 +++++++++-
>   drivers/hwtracing/coresight/coresight-cti.h      |  4 +-
>   drivers/hwtracing/coresight/qcom-cti.h           | 65 ++++++++++++++++++++++++
>   3 files changed, 95 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c
> index c4cbeb64365b..b1c69a3e9b99 100644
> --- a/drivers/hwtracing/coresight/coresight-cti-core.c
> +++ b/drivers/hwtracing/coresight/coresight-cti-core.c
> @@ -21,6 +21,7 @@
>   
>   #include "coresight-priv.h"
>   #include "coresight-cti.h"
> +#include "qcom-cti.h"
>   
>   /*
>    * CTI devices can be associated with a PE, or be connected to CoreSight
> @@ -47,6 +48,10 @@ static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg)
>   	u32 offset = CTI_REG_CLR_NR(reg);
>   	u32 nr = CTI_REG_GET_NR(reg);
>   
> +	/* convert to qcom specific offset */
> +	if (unlikely(drvdata->is_qcom_cti))

I prefer to drop the unlikely here, let the cpu do the branch predictor.

> +		offset = cti_qcom_reg_off(offset);
> +
>   	return drvdata->base + offset + sizeof(u32) * nr;
>   }
>   
> @@ -170,6 +175,9 @@ void cti_write_intack(struct device *dev, u32 ackval)
>   /* DEVID[19:16] - number of CTM channels */
>   #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19))
>   
> +/* DEVARCH[31:21] - ARCHITECT */
> +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31))
> +
>   static int cti_set_default_config(struct device *dev,
>   				  struct cti_drvdata *drvdata)
>   {
> @@ -700,6 +708,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
>   	struct coresight_desc cti_desc;
>   	struct coresight_platform_data *pdata = NULL;
>   	struct resource *res = &adev->res;
> +	u32 devarch;
>   
>   	/* driver data*/
>   	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> @@ -724,6 +733,22 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
>   
>   	raw_spin_lock_init(&drvdata->spinlock);
>   
> +	devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH);
> +	if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) {
> +		drvdata->is_qcom_cti = true;
> +		/*
> +		 * QCOM CTI does not implement Claimtag functionality as
> +		 * per CoreSight specification, but its CLAIMSET register
> +		 * is incorrectly initialized to 0xF. This can mislead
> +		 * tools or drivers into thinking the component is claimed.
> +		 *
> +		 * Reset CLAIMSET to 0 to reflect that no claims are active.
> +		 */
> +		CS_UNLOCK(drvdata->base);
> +		writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET);
> +		CS_LOCK(drvdata->base);
> +	}
> +
>   	/* initialise CTI driver config values */
>   	ret = cti_set_default_config(dev, drvdata);
>   	if (ret)
> @@ -780,7 +805,8 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
>   
>   	/* all done - dec pm refcount */
>   	pm_runtime_put(&adev->dev);
> -	dev_info(&drvdata->csdev->dev, "CTI initialized\n");
> +	dev_info(&drvdata->csdev->dev,
> +		 "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : "");
>   	return 0;
>   }
>   
> diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h
> index dd1ba44518c4..2598601e7b93 100644
> --- a/drivers/hwtracing/coresight/coresight-cti.h
> +++ b/drivers/hwtracing/coresight/coresight-cti.h
> @@ -55,10 +55,11 @@ struct fwnode_handle;
>   /*
>    * CTI CSSoc 600 has a max of 32 trigger signals per direction.
>    * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def.
> + * QCOM CTI supports up to 128 trigger signals per direction.
>    * Max of in and out defined in the DEVID register.
>    * - pick up actual number used from .dts parameters if present.
>    */
> -#define CTIINOUTEN_MAX		32
> +#define CTIINOUTEN_MAX		128
>   
>   /*
>    * Encode CTI register offset and register index in one u32:
> @@ -188,6 +189,7 @@ struct cti_drvdata {
>   	raw_spinlock_t spinlock;
>   	struct cti_config config;
>   	struct list_head node;
> +	bool is_qcom_cti;

missed document.

Thanks,
Jie

>   };
>   
>   /*
> diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h
> new file mode 100644
> index 000000000000..fd1bf07d7cb4
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/qcom-cti.h
> @@ -0,0 +1,65 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef _CORESIGHT_QCOM_CTI_H
> +#define _CORESIGHT_QCOM_CTI_H
> +
> +#include "coresight-cti.h"
> +
> +#define ARCHITECT_QCOM 0x477
> +
> +/* CTI programming registers */
> +#define QCOM_CTIINTACK		0x020
> +#define QCOM_CTIAPPSET		0x004
> +#define QCOM_CTIAPPCLEAR	0x008
> +#define QCOM_CTIAPPPULSE	0x00C
> +#define QCOM_CTIINEN		0x400
> +#define QCOM_CTIOUTEN		0x800
> +#define QCOM_CTITRIGINSTATUS	0x040
> +#define QCOM_CTITRIGOUTSTATUS	0x060
> +#define QCOM_CTICHINSTATUS	0x080
> +#define QCOM_CTICHOUTSTATUS	0x084
> +#define QCOM_CTIGATE		0x088
> +#define QCOM_ASICCTL		0x08C
> +/* Integration test registers */
> +#define QCOM_ITCHINACK		0xE70
> +#define QCOM_ITTRIGINACK	0xE80
> +#define QCOM_ITCHOUT		0xE74
> +#define QCOM_ITTRIGOUT		0xEA0
> +#define QCOM_ITCHOUTACK		0xE78
> +#define QCOM_ITTRIGOUTACK	0xEC0
> +#define QCOM_ITCHIN		0xE7C
> +#define QCOM_ITTRIGIN		0xEE0
> +
> +static noinline u32 cti_qcom_reg_off(u32 offset)
> +{
> +	switch (offset) {
> +	case CTIINTACK:		return QCOM_CTIINTACK;
> +	case CTIAPPSET:		return QCOM_CTIAPPSET;
> +	case CTIAPPCLEAR:	return QCOM_CTIAPPCLEAR;
> +	case CTIAPPPULSE:	return QCOM_CTIAPPPULSE;
> +	case CTIINEN:		return QCOM_CTIINEN;
> +	case CTIOUTEN:		return QCOM_CTIOUTEN;
> +	case CTITRIGINSTATUS:	return QCOM_CTITRIGINSTATUS;
> +	case CTITRIGOUTSTATUS:	return QCOM_CTITRIGOUTSTATUS;
> +	case CTICHINSTATUS:	return QCOM_CTICHINSTATUS;
> +	case CTICHOUTSTATUS:	return QCOM_CTICHOUTSTATUS;
> +	case CTIGATE:		return QCOM_CTIGATE;
> +	case ASICCTL:		return QCOM_ASICCTL;
> +	case ITCHINACK:		return QCOM_ITCHINACK;
> +	case ITTRIGINACK:	return QCOM_ITTRIGINACK;
> +	case ITCHOUT:		return QCOM_ITCHOUT;
> +	case ITTRIGOUT:		return QCOM_ITTRIGOUT;
> +	case ITCHOUTACK:	return QCOM_ITCHOUTACK;
> +	case ITTRIGOUTACK:	return QCOM_ITTRIGOUTACK;
> +	case ITCHIN:		return QCOM_ITCHIN;
> +	case ITTRIGIN:		return QCOM_ITTRIGIN;
> +
> +	default:
> +		return offset;
> +	}
> +}
> +
> +#endif  /* _CORESIGHT_QCOM_CTI_H */
> 

Re: [PATCH v8 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks

[Yingchao Deng (Consultant)]

On 4/27/2026 3:39 PM, Jie Gan wrote:
>
>
> On 4/26/2026 5:44 PM, Yingchao Deng wrote:
>> Qualcomm implements an extended variant of the ARM CoreSight CTI with a
>> different register layout and vendor-specific behavior. While the
>> programming model remains largely compatible, the register offsets 
>> differ
>> from the standard ARM CTI and require explicit handling.
>>
>> Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI
>> driver data. Introduce a small mapping layer to translate standard CTI
>> register offsets to Qualcomm-specific offsets, allowing the rest of the
>> driver to use a common register access path.
>>
>> Additionally, handle a Qualcomm-specific quirk where the CLAIMSET
>> register is incorrectly initialized to a non-zero value, which can cause
>> tools or drivers to assume the component is already claimed. Clear the
>> register during probe to reflect the actual unclaimed state.
>>
>> No functional change is intended for standard ARM CTI devices.
>>
>> Co-developed-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
>> Signed-off-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
>> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-cti-core.c | 28 +++++++++-
>>   drivers/hwtracing/coresight/coresight-cti.h      |  4 +-
>>   drivers/hwtracing/coresight/qcom-cti.h           | 65 
>> ++++++++++++++++++++++++
>>   3 files changed, 95 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c 
>> b/drivers/hwtracing/coresight/coresight-cti-core.c
>> index c4cbeb64365b..b1c69a3e9b99 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-cti-core.c
>> @@ -21,6 +21,7 @@
>>     #include "coresight-priv.h"
>>   #include "coresight-cti.h"
>> +#include "qcom-cti.h"
>>     /*
>>    * CTI devices can be associated with a PE, or be connected to 
>> CoreSight
>> @@ -47,6 +48,10 @@ static void __iomem *cti_reg_addr(struct 
>> cti_drvdata *drvdata, int reg)
>>       u32 offset = CTI_REG_CLR_NR(reg);
>>       u32 nr = CTI_REG_GET_NR(reg);
>>   +    /* convert to qcom specific offset */
>> +    if (unlikely(drvdata->is_qcom_cti))
>
> I prefer to drop the unlikely here, let the cpu do the branch predictor.
>
>> +        offset = cti_qcom_reg_off(offset);
>> +
>>       return drvdata->base + offset + sizeof(u32) * nr;
>>   }
>>   @@ -170,6 +175,9 @@ void cti_write_intack(struct device *dev, u32 
>> ackval)
>>   /* DEVID[19:16] - number of CTM channels */
>>   #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 
>> 16, 19))
>>   +/* DEVARCH[31:21] - ARCHITECT */
>> +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 
>> 21, 31))
>> +
>>   static int cti_set_default_config(struct device *dev,
>>                     struct cti_drvdata *drvdata)
>>   {
>> @@ -700,6 +708,7 @@ static int cti_probe(struct amba_device *adev, 
>> const struct amba_id *id)
>>       struct coresight_desc cti_desc;
>>       struct coresight_platform_data *pdata = NULL;
>>       struct resource *res = &adev->res;
>> +    u32 devarch;
>>         /* driver data*/
>>       drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>> @@ -724,6 +733,22 @@ static int cti_probe(struct amba_device *adev, 
>> const struct amba_id *id)
>>         raw_spin_lock_init(&drvdata->spinlock);
>>   +    devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH);
>> +    if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) {
>> +        drvdata->is_qcom_cti = true;
>> +        /*
>> +         * QCOM CTI does not implement Claimtag functionality as
>> +         * per CoreSight specification, but its CLAIMSET register
>> +         * is incorrectly initialized to 0xF. This can mislead
>> +         * tools or drivers into thinking the component is claimed.
>> +         *
>> +         * Reset CLAIMSET to 0 to reflect that no claims are active.
>> +         */
>> +        CS_UNLOCK(drvdata->base);
>> +        writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET);
>> +        CS_LOCK(drvdata->base);
>> +    }
>> +
>>       /* initialise CTI driver config values */
>>       ret = cti_set_default_config(dev, drvdata);
>>       if (ret)
>> @@ -780,7 +805,8 @@ static int cti_probe(struct amba_device *adev, 
>> const struct amba_id *id)
>>         /* all done - dec pm refcount */
>>       pm_runtime_put(&adev->dev);
>> -    dev_info(&drvdata->csdev->dev, "CTI initialized\n");
>> +    dev_info(&drvdata->csdev->dev,
>> +         "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : "");
>>       return 0;
>>   }
>>   diff --git a/drivers/hwtracing/coresight/coresight-cti.h 
>> b/drivers/hwtracing/coresight/coresight-cti.h
>> index dd1ba44518c4..2598601e7b93 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti.h
>> +++ b/drivers/hwtracing/coresight/coresight-cti.h
>> @@ -55,10 +55,11 @@ struct fwnode_handle;
>>   /*
>>    * CTI CSSoc 600 has a max of 32 trigger signals per direction.
>>    * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def.
>> + * QCOM CTI supports up to 128 trigger signals per direction.
>>    * Max of in and out defined in the DEVID register.
>>    * - pick up actual number used from .dts parameters if present.
>>    */
>> -#define CTIINOUTEN_MAX        32
>> +#define CTIINOUTEN_MAX        128
>>     /*
>>    * Encode CTI register offset and register index in one u32:
>> @@ -188,6 +189,7 @@ struct cti_drvdata {
>>       raw_spinlock_t spinlock;
>>       struct cti_config config;
>>       struct list_head node;
>> +    bool is_qcom_cti;
>
> missed document.
>
> Thanks,
> Jie
>
will update.

Thanks,
Yingchao
>>   };
>>     /*
>> diff --git a/drivers/hwtracing/coresight/qcom-cti.h 
>> b/drivers/hwtracing/coresight/qcom-cti.h
>> new file mode 100644
>> index 000000000000..fd1bf07d7cb4
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/qcom-cti.h
>> @@ -0,0 +1,65 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +#ifndef _CORESIGHT_QCOM_CTI_H
>> +#define _CORESIGHT_QCOM_CTI_H
>> +
>> +#include "coresight-cti.h"
>> +
>> +#define ARCHITECT_QCOM 0x477
>> +
>> +/* CTI programming registers */
>> +#define QCOM_CTIINTACK        0x020
>> +#define QCOM_CTIAPPSET        0x004
>> +#define QCOM_CTIAPPCLEAR    0x008
>> +#define QCOM_CTIAPPPULSE    0x00C
>> +#define QCOM_CTIINEN        0x400
>> +#define QCOM_CTIOUTEN        0x800
>> +#define QCOM_CTITRIGINSTATUS    0x040
>> +#define QCOM_CTITRIGOUTSTATUS    0x060
>> +#define QCOM_CTICHINSTATUS    0x080
>> +#define QCOM_CTICHOUTSTATUS    0x084
>> +#define QCOM_CTIGATE        0x088
>> +#define QCOM_ASICCTL        0x08C
>> +/* Integration test registers */
>> +#define QCOM_ITCHINACK        0xE70
>> +#define QCOM_ITTRIGINACK    0xE80
>> +#define QCOM_ITCHOUT        0xE74
>> +#define QCOM_ITTRIGOUT        0xEA0
>> +#define QCOM_ITCHOUTACK        0xE78
>> +#define QCOM_ITTRIGOUTACK    0xEC0
>> +#define QCOM_ITCHIN        0xE7C
>> +#define QCOM_ITTRIGIN        0xEE0
>> +
>> +static noinline u32 cti_qcom_reg_off(u32 offset)
>> +{
>> +    switch (offset) {
>> +    case CTIINTACK:        return QCOM_CTIINTACK;
>> +    case CTIAPPSET:        return QCOM_CTIAPPSET;
>> +    case CTIAPPCLEAR:    return QCOM_CTIAPPCLEAR;
>> +    case CTIAPPPULSE:    return QCOM_CTIAPPPULSE;
>> +    case CTIINEN:        return QCOM_CTIINEN;
>> +    case CTIOUTEN:        return QCOM_CTIOUTEN;
>> +    case CTITRIGINSTATUS:    return QCOM_CTITRIGINSTATUS;
>> +    case CTITRIGOUTSTATUS:    return QCOM_CTITRIGOUTSTATUS;
>> +    case CTICHINSTATUS:    return QCOM_CTICHINSTATUS;
>> +    case CTICHOUTSTATUS:    return QCOM_CTICHOUTSTATUS;
>> +    case CTIGATE:        return QCOM_CTIGATE;
>> +    case ASICCTL:        return QCOM_ASICCTL;
>> +    case ITCHINACK:        return QCOM_ITCHINACK;
>> +    case ITTRIGINACK:    return QCOM_ITTRIGINACK;
>> +    case ITCHOUT:        return QCOM_ITCHOUT;
>> +    case ITTRIGOUT:        return QCOM_ITTRIGOUT;
>> +    case ITCHOUTACK:    return QCOM_ITCHOUTACK;
>> +    case ITTRIGOUTACK:    return QCOM_ITTRIGOUTACK;
>> +    case ITCHIN:        return QCOM_ITCHIN;
>> +    case ITTRIGIN:        return QCOM_ITTRIGIN;
>> +
>> +    default:
>> +        return offset;
>> +    }
>> +}
>> +
>> +#endif  /* _CORESIGHT_QCOM_CTI_H */
>>
>

[PATCH v8 4/4] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI

[Yingchao Deng]

Qualcomm extended CTI implements banked trigger status and integration
registers, where each bank covers 32 triggers. Multiple instances of
these registers are required to expose the full trigger space.

Add static sysfs entries for the banked CTI registers and control their
visibility based on the underlying hardware configuration. Numbered
sysfs nodes are hidden on standard ARM CTIs, preserving the existing ABI.
On Qualcomm CTIs, only banked registers backed by hardware are exposed,
with the number of visible banks derived from nr_trig_max.

This ensures that userspace only sees registers that are actually
implemented, while maintaining compatibility with existing CTI tooling.

Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
---
 drivers/hwtracing/coresight/coresight-cti-sysfs.c | 58 +++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
index 8b70e7e38ea3..046757e4e9b6 100644
--- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
@@ -512,18 +512,36 @@ static struct attribute *coresight_cti_regs_attrs[] = {
 	&dev_attr_appclear.attr,
 	&dev_attr_apppulse.attr,
 	coresight_cti_reg(triginstatus, CTITRIGINSTATUS),
+	coresight_cti_reg(triginstatus1, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 1)),
+	coresight_cti_reg(triginstatus2, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 2)),
+	coresight_cti_reg(triginstatus3, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 3)),
 	coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS),
+	coresight_cti_reg(trigoutstatus1, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 1)),
+	coresight_cti_reg(trigoutstatus2, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 2)),
+	coresight_cti_reg(trigoutstatus3, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 3)),
 	coresight_cti_reg(chinstatus, CTICHINSTATUS),
 	coresight_cti_reg(choutstatus, CTICHOUTSTATUS),
 #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS
 	coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL),
 	coresight_cti_reg(ittrigin, ITTRIGIN),
+	coresight_cti_reg(ittrigin1, CTI_REG_SET_NR_CONST(ITTRIGIN, 1)),
+	coresight_cti_reg(ittrigin2, CTI_REG_SET_NR_CONST(ITTRIGIN, 2)),
+	coresight_cti_reg(ittrigin3, CTI_REG_SET_NR_CONST(ITTRIGIN, 3)),
 	coresight_cti_reg(itchin, ITCHIN),
 	coresight_cti_reg_rw(ittrigout, ITTRIGOUT),
+	coresight_cti_reg_rw(ittrigout1, CTI_REG_SET_NR_CONST(ITTRIGOUT, 1)),
+	coresight_cti_reg_rw(ittrigout2, CTI_REG_SET_NR_CONST(ITTRIGOUT, 2)),
+	coresight_cti_reg_rw(ittrigout3, CTI_REG_SET_NR_CONST(ITTRIGOUT, 3)),
 	coresight_cti_reg_rw(itchout, ITCHOUT),
 	coresight_cti_reg(itchoutack, ITCHOUTACK),
 	coresight_cti_reg(ittrigoutack, ITTRIGOUTACK),
+	coresight_cti_reg(ittrigoutack1, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 1)),
+	coresight_cti_reg(ittrigoutack2, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 2)),
+	coresight_cti_reg(ittrigoutack3, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 3)),
 	coresight_cti_reg_wo(ittriginack, ITTRIGINACK),
+	coresight_cti_reg_wo(ittriginack1, CTI_REG_SET_NR_CONST(ITTRIGINACK, 1)),
+	coresight_cti_reg_wo(ittriginack2, CTI_REG_SET_NR_CONST(ITTRIGINACK, 2)),
+	coresight_cti_reg_wo(ittriginack3, CTI_REG_SET_NR_CONST(ITTRIGINACK, 3)),
 	coresight_cti_reg_wo(itchinack, ITCHINACK),
 #endif
 	NULL,
@@ -534,10 +552,50 @@ static umode_t coresight_cti_regs_is_visible(struct kobject *kobj,
 {
 	struct device *dev = kobj_to_dev(kobj);
 	struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
+	static const char * const qcom_suffix_registers[] = {
+		"triginstatus",
+		"trigoutstatus",
+#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS
+		"ittrigin",
+		"ittrigout",
+		"ittriginack",
+		"ittrigoutack",
+#endif
+	};
+	int i, nr, max_bank;
+	size_t len;
 
 	if (attr == &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl)
 		return 0;
 
+	/*
+	 * Banked regs are exposed as <qcom_suffix_registers><nr> (nr = 1..3).
+	 * - Hide them on standard CTIs.
+	 * - On QCOM CTIs, hide suffixes beyond the number of banks implied
+	 *   by nr_trig_max (32 triggers per bank).
+	 */
+	for (i = 0; i < ARRAY_SIZE(qcom_suffix_registers); i++) {
+		len = strlen(qcom_suffix_registers[i]);
+
+		if (strncmp(attr->name, qcom_suffix_registers[i], len))
+			continue;
+
+		if (kstrtoint(attr->name + len, 10, &nr))
+			continue;
+
+		if (!drvdata->is_qcom_cti)
+			return 0;
+
+		if (nr < 1 || nr > 3)
+			return 0;
+
+		max_bank = DIV_ROUND_UP(drvdata->config.nr_trig_max, 32) - 1;
+		if (nr > max_bank)
+			return 0;
+
+		break;
+	}
+
 	return attr->mode;
 }
 

-- 
2.43.0

Re: [PATCH v8 4/4] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI

[Leo Yan]

On Sun, Apr 26, 2026 at 05:44:41PM +0800, Yingchao Deng wrote:
> Qualcomm extended CTI implements banked trigger status and integration
> registers, where each bank covers 32 triggers. Multiple instances of
> these registers are required to expose the full trigger space.
> 
> Add static sysfs entries for the banked CTI registers and control their
> visibility based on the underlying hardware configuration. Numbered
> sysfs nodes are hidden on standard ARM CTIs, preserving the existing ABI.
> On Qualcomm CTIs, only banked registers backed by hardware are exposed,
> with the number of visible banks derived from nr_trig_max.
> 
> This ensures that userspace only sees registers that are actually
> implemented, while maintaining compatibility with existing CTI tooling.
> 
> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> ---
>  drivers/hwtracing/coresight/coresight-cti-sysfs.c | 58 +++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> index 8b70e7e38ea3..046757e4e9b6 100644
> --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c
> @@ -512,18 +512,36 @@ static struct attribute *coresight_cti_regs_attrs[] = {
>  	&dev_attr_appclear.attr,
>  	&dev_attr_apppulse.attr,
>  	coresight_cti_reg(triginstatus, CTITRIGINSTATUS),
> +	coresight_cti_reg(triginstatus1, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 1)),

How about extend the cs_off_attribute struct:

  struct cs_off_attribute {
        struct device_attribute attr;
        u32 off;
        u32 index;
  };

  // by default, the index is 0
  #define coresight_cti_reg(name, offset)                               \
        (&((struct cs_off_attribute[]) {                                \
           {                                                            \
                __ATTR(name, 0444, coresight_cti_reg_show, NULL),       \
                offset                                                  \
                0                                                       \
           }                                                            \
  })[0].attr.attr)

  // For the register with index
  #define coresight_cti_reg_index(name, offset, index)                  \
        (&((struct cs_off_attribute[]) {                                \
           {                                                            \
                __ATTR(name, 0444, coresight_cti_reg_show, NULL),       \
                offset                                                  \
                index                                                   \
           }                                                            \
  })[0].attr.attr)

  coresight_cti_reg_index(triginstatus1, CTITRIGINSTATUS, 1),

> +	coresight_cti_reg(triginstatus2, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 2)),
> +	coresight_cti_reg(triginstatus3, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 3)),
>  	coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS),
> +	coresight_cti_reg(trigoutstatus1, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 1)),
> +	coresight_cti_reg(trigoutstatus2, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 2)),
> +	coresight_cti_reg(trigoutstatus3, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 3)),
>  	coresight_cti_reg(chinstatus, CTICHINSTATUS),
>  	coresight_cti_reg(choutstatus, CTICHOUTSTATUS),
>  #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS
>  	coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL),
>  	coresight_cti_reg(ittrigin, ITTRIGIN),
> +	coresight_cti_reg(ittrigin1, CTI_REG_SET_NR_CONST(ITTRIGIN, 1)),
> +	coresight_cti_reg(ittrigin2, CTI_REG_SET_NR_CONST(ITTRIGIN, 2)),
> +	coresight_cti_reg(ittrigin3, CTI_REG_SET_NR_CONST(ITTRIGIN, 3)),
>  	coresight_cti_reg(itchin, ITCHIN),
>  	coresight_cti_reg_rw(ittrigout, ITTRIGOUT),
> +	coresight_cti_reg_rw(ittrigout1, CTI_REG_SET_NR_CONST(ITTRIGOUT, 1)),
> +	coresight_cti_reg_rw(ittrigout2, CTI_REG_SET_NR_CONST(ITTRIGOUT, 2)),
> +	coresight_cti_reg_rw(ittrigout3, CTI_REG_SET_NR_CONST(ITTRIGOUT, 3)),
>  	coresight_cti_reg_rw(itchout, ITCHOUT),
>  	coresight_cti_reg(itchoutack, ITCHOUTACK),
>  	coresight_cti_reg(ittrigoutack, ITTRIGOUTACK),
> +	coresight_cti_reg(ittrigoutack1, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 1)),
> +	coresight_cti_reg(ittrigoutack2, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 2)),
> +	coresight_cti_reg(ittrigoutack3, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 3)),
>  	coresight_cti_reg_wo(ittriginack, ITTRIGINACK),
> +	coresight_cti_reg_wo(ittriginack1, CTI_REG_SET_NR_CONST(ITTRIGINACK, 1)),
> +	coresight_cti_reg_wo(ittriginack2, CTI_REG_SET_NR_CONST(ITTRIGINACK, 2)),
> +	coresight_cti_reg_wo(ittriginack3, CTI_REG_SET_NR_CONST(ITTRIGINACK, 3)),
>  	coresight_cti_reg_wo(itchinack, ITCHINACK),
>  #endif
>  	NULL,
> @@ -534,10 +552,50 @@ static umode_t coresight_cti_regs_is_visible(struct kobject *kobj,
>  {
>  	struct device *dev = kobj_to_dev(kobj);
>  	struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +	static const char * const qcom_suffix_registers[] = {
> +		"triginstatus",
> +		"trigoutstatus",
> +#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS
> +		"ittrigin",
> +		"ittrigout",
> +		"ittriginack",
> +		"ittrigoutack",
> +#endif
> +	};
> +	int i, nr, max_bank;
> +	size_t len;
>  
>  	if (attr == &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl)
>  		return 0;
>  
> +	/*
> +	 * Banked regs are exposed as <qcom_suffix_registers><nr> (nr = 1..3).
> +	 * - Hide them on standard CTIs.
> +	 * - On QCOM CTIs, hide suffixes beyond the number of banks implied
> +	 *   by nr_trig_max (32 triggers per bank).
> +	 */
> +	for (i = 0; i < ARRAY_SIZE(qcom_suffix_registers); i++) {

This can be general for a register with index?  Like:

  for (i = 0; i < ARRAY_SIZE(registers_with_index); i++) {

> +		len = strlen(qcom_suffix_registers[i]);
> +
> +		if (strncmp(attr->name, qcom_suffix_registers[i], len))
> +			continue;
> +
> +		if (kstrtoint(attr->name + len, 10, &nr))
> +			continue;
> +
> +		if (!drvdata->is_qcom_cti)
> +			return 0;
> +
> +		if (nr < 1 || nr > 3)
> +			return 0;
> +
> +		max_bank = DIV_ROUND_UP(drvdata->config.nr_trig_max, 32) - 1;
> +		if (nr > max_bank)
> +			return 0;

Directly check the attr's index here?

  struct cs_off_attribute *cti_attr =
                container_of(attr, struct cs_off_attribute, attr);

  max_bank = DIV_ROUND_UP(drvdata->config.nr_trig_max, 32);
  if (cti_attr->index >= max_bank)
      return 0;

Thanks,
Leo