[PATCH v2 0/8] PCI: Add common helper for 100 ms delay after link training

[Hans Zhang <18255117159@163.com>]

PCIe r6.0, sec 6.6.1 (Conventional Reset) states:

- For a Downstream Port that supports Link speeds greater than 5.0 GT/s,
  software must wait a minimum of 100 ms **after Link training completes**
  before sending a Configuration Request to the device immediately below
  that Port.

Several PCIe host controller drivers currently omit this 100 ms delay
when the negotiated link speed is Gen3 (8 GT/s) or higher. Only the DWC
driver already implements it. The missing delay can lead to violations
of the PCIe specification.

To fix this consistently and avoid code duplication, this series:

  1. Adds a static inline helper `pcie_wait_after_link_train()` in
     drivers/pci/pci.h. The helper checks the given max_link_speed
     (or negotiated speed) and calls msleep(100) if the speed is > 5 GT/s.

  2. Converts the DWC driver to use this helper.

  3. Adds the missing 100 ms delay to the Cadence PCIe controller
     (both LGA - Legacy Architecture IP - and HPA - High Performance
     Architecture IP) after introducing a `max_link_speed` field in
     struct cdns_pcie.

  4. Adds the delay to the Aardvark, MediaTek Gen3, and Renesas RZ/G3S
     host drivers, reusing their existing link speed fields.

All changes are placed exactly where the driver has just finished
waiting for the link to come up, i.e., immediately after link training
completes and before any Configuration Request would be issued.

---
Our company's product is based on the HPA IP from Cadence. When connecting
to different devices, we encountered issues with the enumeration failure
when connecting to the NVIDIA RTX5070 GPU and the NVMe SSD with PCIe 5.0
interface. Our code is based on: 80dc18a0cba8d ("PCI: dwc: Ensure that
dw_pcie_wait_for_link() waits 100 ms after link up").
---
Changes since v2:
- Add pcie_wait_after_link_train() helper
- Reduce repetitive code comments and have each Root Port driver use the
  helper function instead.
- Increase the delay to 100ms after enabling the link-up that distinguishes
  between Cadence LGA and HPA IPs.
- Add the Aardvark, MediaTek Gen3, and Renesas RZ/G3S Root Port driver. When
  the speed is greater than GEN2, a delay of 100ms should be applied.

v1:
https://patchwork.kernel.org/project/linux-pci/patch/20260501153553.66382-1-18255117159@163.com/
---
Hans Zhang (8):
  PCI: Add pcie_wait_after_link_train() helper
  PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after
    link training
  PCI: cadence: HPA: Add 100 ms delay after link training
  PCI: j721e: Set max_link_speed to enable 100 ms delay after link up
  PCI: dwc: Use common pcie_wait_after_link_train() helper
  PCI: aardvark: Add 100 ms delay after link training
  PCI: mediatek-gen3: Add 100 ms delay after link training
  PCI: rzg3s-host: Add 100 ms delay after link training

 drivers/pci/controller/cadence/pci-j721e.c          |  1 +
 .../controller/cadence/pcie-cadence-host-common.c   |  4 ++++
 .../pci/controller/cadence/pcie-cadence-host-hpa.c  |  3 +++
 drivers/pci/controller/cadence/pcie-cadence.h       |  2 ++
 drivers/pci/controller/dwc/pcie-designware.c        |  8 +-------
 drivers/pci/controller/pci-aardvark.c               |  4 +++-
 drivers/pci/controller/pcie-mediatek-gen3.c         |  2 ++
 drivers/pci/controller/pcie-rzg3s-host.c            |  2 ++
 drivers/pci/pci.h                                   | 13 +++++++++++++
 9 files changed, 31 insertions(+), 8 deletions(-)


base-commit: a293ec25d59dd96309058c70df5a4dd0f889a1e4
-- 
2.34.1