From: Ben Horgan <ben.horgan@arm.com>
To: ben.horgan@arm.com
Cc: amitsinght@marvell.com, baisheng.gao@unisoc.com,
baolin.wang@linux.alibaba.com, carl@os.amperecomputing.com,
dave.martin@arm.com, david@kernel.org, dfustini@baylibre.com,
fenghuay@nvidia.com, gshan@redhat.com, james.morse@arm.com,
jonathan.cameron@huawei.com, kobak@nvidia.com,
lcherian@marvell.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, peternewman@google.com,
punit.agrawal@oss.qualcomm.com, quic_jiles@quicinc.com,
reinette.chatre@intel.com, rohit.mathew@arm.com,
scott@os.amperecomputing.com, sdonthineni@nvidia.com,
tan.shaopeng@fujitsu.com, xhao@linux.alibaba.com,
zengheng4@huawei.com, x86@kernel.org
Subject: [PATCH v3 5/5] arm64: mpam: Add memory bandwidth usage (MBWU) documentation
Date: Mon, 11 May 2026 16:41:47 +0100 [thread overview]
Message-ID: <20260511154147.557481-6-ben.horgan@arm.com> (raw)
In-Reply-To: <20260511154147.557481-1-ben.horgan@arm.com>
Memory bandwidth monitoring make uses of MBWU monitors and is now exposed
to the user via resctrl. Add some documentation so the user knows what to
expect.
Co-developed-by: James Morse <james.morse@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
---
Documentation/arch/arm64/mpam.rst | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/arch/arm64/mpam.rst b/Documentation/arch/arm64/mpam.rst
index 570f51a8d4eb..208ff17068c4 100644
--- a/Documentation/arch/arm64/mpam.rst
+++ b/Documentation/arch/arm64/mpam.rst
@@ -65,6 +65,23 @@ The supported features are:
there is at least one CSU monitor on each MSC that makes up the L3 group.
Exposing CSU counters from other caches or devices is not supported.
+* Memory Bandwidth Usage (MBWU) on or after the L3 cache. resctrl uses the
+ L3 cache-id to identify where the memory bandwidth is measured. For this
+ reason the platform must have an L3 cache with cache-id's supplied by
+ firmware. (It doesn't need to support MPAM.)
+
+ Memory bandwidth monitoring makes use of MBWU monitors in each MSC that
+ makes up the L3 group. If the memory bandwidth monitoring is on the memory
+ rather than the L3 then there must be a single global L3 as otherwise it
+ is unknown which L3 the traffic came from.
+
+ To expose 'mbm_total_bytes', the topology of the group of MSC chosen must
+ match the topology of the L3 cache so that the cache-id's can be
+ repainted. For example: Platforms with Memory bandwidth monitors on
+ CPU-less NUMA nodes cannot expose 'mbm_total_bytes' as these nodes do not
+ have a corresponding L3 cache. 'mbm_local_bytes' is not exposed as MPAM
+ cannot distinguish local traffic from global traffic.
+
Reporting Bugs
==============
If you are not seeing the counters or controls you expect please share the
--
2.43.0
next prev parent reply other threads:[~2026-05-11 15:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 15:41 [PATCH v3 0/5] arm_mpam: resctrl: Counter Assignment (ABMC) Ben Horgan
2026-05-11 15:41 ` [PATCH v3 1/5] arm_mpam: resctrl: Pick classes for use as mbm counters Ben Horgan
2026-05-12 6:50 ` Shaopeng Tan (Fujitsu)
2026-05-12 9:21 ` Ben Horgan
2026-05-11 15:41 ` [PATCH v3 2/5] arm_mpam: resctrl: Pre-allocate assignable monitors Ben Horgan
2026-05-12 7:16 ` Shaopeng Tan (Fujitsu)
2026-05-12 9:43 ` Ben Horgan
2026-05-11 15:41 ` [PATCH v3 3/5] arm_mpam: resctrl: Add resctrl_arch_config_cntr() for ABMC use Ben Horgan
2026-05-11 15:41 ` [PATCH v3 4/5] arm_mpam: resctrl: Add resctrl_arch_cntr_read() & resctrl_arch_reset_cntr() Ben Horgan
2026-05-11 15:41 ` Ben Horgan [this message]
2026-05-11 15:51 ` [PATCH v3 0/5] arm_mpam: resctrl: Counter Assignment (ABMC) Ben Horgan
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