* [PATCH v3 0/3] pinctrl: aspeed: Add AST2700 SoC1 support
@ 2026-05-15 9:37 Billy Tsai
2026-05-15 9:37 ` [PATCH v3 1/3] dt-bindings: mfd: aspeed,ast2x00-scu: Support AST2700 SoC1 pinctrl Billy Tsai
2026-05-15 9:37 ` [PATCH v3 2/3] dt-bindings: pinctrl: Add aspeed,ast2700-soc1-pinctrl Billy Tsai
0 siblings, 2 replies; 3+ messages in thread
From: Billy Tsai @ 2026-05-15 9:37 UTC (permalink / raw)
To: Linus Walleij, Tony Lindgren, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery, Bartosz Golaszewski,
Lee Jones, Ryan Chen
Cc: patrickw3, linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
linux-aspeed, BMC-SW, openbmc, Andrew Jeffery, linux-clk,
Billy Tsai
Legacy ASPEED pin controllers have historically not had a coherent
register interface. Control fields often had no consistent mapping to
individual pins, and configuring a function frequently required
coordinating multiple control bits across several registers. As a
result, the existing ASPEED pinctrl drivers rely on complex macro
infrastructure to describe the dependencies between pins, functions,
and register fields.
The pin controller for SoC1 in the AST2700 breaks from this legacy
design.
For SoC1, each pin maps directly to a dedicated function field in the
SCU register space that determines the active mux function for that
pin. This results in a much more regular register layout compared to
previous generations.
While the behaviour is conceptually similar to pinctrl-single, the
register layout and configuration model differ enough that reusing
pinctrl-single directly is not practical. Therefore this driver is
implemented as a SoC-specific pinctrl driver using static data tables
to describe the register layout.
The binding reuses the standard pinmux and generic pin configuration
schemas and does not introduce any custom Devicetree properties.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
Changes in v3:
- Added pin configuration group support for AST2700 SoC1 by
implementing `pin_config_group_get()` and `pin_config_group_set()`.
- Restricted AST2700 SoC1 `drive-strength` settings to the supported
4/8/12/16 mA values in the pinctrl driver.
- Convert kernel-doc comment for aspeed_g7_soc1_drv_map to a regular
comment to avoid kernel-doc warning reported by kernel test robot.
- Update the AST2700 SoC1 pinctrl binding to describe the `reg`
property and require it.
- Allow standard pinconf properties in pin state nodes.
- Add a binding example for the AST2700 SoC1 pinctrl node.
- Add state-node description, function+groups dependency constraint,
and oneOf groups/pins constraint to the binding, matching the SoC0
binding style.
- Add pins enum (212 entries) to the binding to cover all physical pins
that support per-pin configuration.
- Add UART modem-line signals as independent functions/groups:
NCTS0/1/5/6, NDCD0/1/5/6, NDSR0/1/5/6, NDTR0/1/5/6,
NRI0/1/5/6, NRTS0/1/5/6; remove those pins from UART0/1/5/6 groups.
- Add LTPI_PS_I2C0/1/2/3 functions/groups for I2C-over-LTPI;
extend I2C0/1/2/3 functions with the new LTPI groups.
- Fix typo: rename RMII0RCKO/RMII1RCKO to RMII0RCLKO/RMII1RCLKO.
- Fix wrong index: rename DSGPM1 to DSGPM0.
- Kconfig: use "Aspeed G7 SoC1 pin control" to match neighbouring entries.
- pin_config_get: fix BIAS_DISABLE readback (val=!val must be skipped
for BIAS_DISABLE since hardware bit=1 means pull disabled).
- set_mux: remove dead null check on grp; propagate regmap_update_bits()
return value.
- gpio_request_enable: propagate regmap_update_bits() return value.
- Link to v2: https://lore.kernel.org/r/20260306-pinctrl-single-bit-v2-0-79918cfab641@aspeedtech.com
Changes in v2:
- Updated the series title to focus on AST2700 SoC1 support.
- Reworked implementation to use static SoC-specific layout tables
instead of a generic packed-field model.
- Dropped the generic "pinctrl-packed" driver approach.
- Removed custom Devicetree properties.
- Updated binding to reuse standard pinmux and generic pin
configuration schemas.
- Link to v1: https://lore.kernel.org/r/20260213-pinctrl-single-bit-v1-0-c60f2fb80efb@aspeedtech.com
---
Billy Tsai (3):
dt-bindings: mfd: aspeed,ast2x00-scu: Support AST2700 SoC1 pinctrl
dt-bindings: pinctrl: Add aspeed,ast2700-soc1-pinctrl
pinctrl: aspeed: Add AST2700 SoC1 support
.../bindings/mfd/aspeed,ast2x00-scu.yaml | 1 +
.../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 760 +++++++++
drivers/pinctrl/aspeed/Kconfig | 14 +
drivers/pinctrl/aspeed/Makefile | 1 +
drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c | 1732 ++++++++++++++++++++
5 files changed, 2508 insertions(+)
---
base-commit: e532a5a81d0db872acd2c0a92d2639580ca3da44
change-id: 20260211-pinctrl-single-bit-da213f282c95
Best regards,
--
Billy Tsai <billy_tsai@aspeedtech.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v3 1/3] dt-bindings: mfd: aspeed,ast2x00-scu: Support AST2700 SoC1 pinctrl
2026-05-15 9:37 [PATCH v3 0/3] pinctrl: aspeed: Add AST2700 SoC1 support Billy Tsai
@ 2026-05-15 9:37 ` Billy Tsai
2026-05-15 9:37 ` [PATCH v3 2/3] dt-bindings: pinctrl: Add aspeed,ast2700-soc1-pinctrl Billy Tsai
1 sibling, 0 replies; 3+ messages in thread
From: Billy Tsai @ 2026-05-15 9:37 UTC (permalink / raw)
To: Linus Walleij, Tony Lindgren, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery, Bartosz Golaszewski,
Lee Jones, Ryan Chen
Cc: patrickw3, linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
linux-aspeed, BMC-SW, openbmc, Andrew Jeffery, linux-clk,
Billy Tsai
The AST2700 SoC integrates two interconnected SoC instances, each
managed by its own System Control Unit (SCU).
Allow the AST2700 SoC1 pin controller to be described as a child
node of the SCU by extending the compatible strings accepted by
the SCU binding.
There is no functional change to the SCU binding beyond permitting
the aspeed,ast2700-soc1-pinctrl compatible string.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
Note: The companion AST2700 SoC0 pinctrl series modifies the same
binding and has been applied to pinctrl/for-next. Linus Walleij noted
for the equivalent SoC0 MFD patch that it should be applied through the
MFD tree by Lee Jones, providing an Acked-by in the process [1]. The
same routing applies to this patch.
[1] https://lore.kernel.org/all/CAD++jL=3p9BvDgaot3=emM4Zn5jU-ZAUKtB4UwT1HzDiyzKq4Q@mail.gmail.com/
---
Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
index a87f31fce019..b81c561d2a8c 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
@@ -87,6 +87,7 @@ patternProperties:
- aspeed,ast2400-pinctrl
- aspeed,ast2500-pinctrl
- aspeed,ast2600-pinctrl
+ - aspeed,ast2700-soc1-pinctrl
required:
- compatible
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v3 2/3] dt-bindings: pinctrl: Add aspeed,ast2700-soc1-pinctrl
2026-05-15 9:37 [PATCH v3 0/3] pinctrl: aspeed: Add AST2700 SoC1 support Billy Tsai
2026-05-15 9:37 ` [PATCH v3 1/3] dt-bindings: mfd: aspeed,ast2x00-scu: Support AST2700 SoC1 pinctrl Billy Tsai
@ 2026-05-15 9:37 ` Billy Tsai
1 sibling, 0 replies; 3+ messages in thread
From: Billy Tsai @ 2026-05-15 9:37 UTC (permalink / raw)
To: Linus Walleij, Tony Lindgren, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joel Stanley, Andrew Jeffery, Bartosz Golaszewski,
Lee Jones, Ryan Chen
Cc: patrickw3, linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
linux-aspeed, BMC-SW, openbmc, Andrew Jeffery, linux-clk,
Billy Tsai
SoC1 in the AST2700 integrates its own pin controller responsible for
pin multiplexing and pin configuration.
The controller manages various peripheral functions such as eSPI, LPC,
VPI, SD, UART, I2C, I3C, PWM and others through SCU registers.
The binding reuses the standard pinmux and generic pin configuration
schemas and does not introduce custom Devicetree properties.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
.../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 760 +++++++++++++++++++++
1 file changed, 760 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
new file mode 100644
index 000000000000..76944fd14e2c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
@@ -0,0 +1,760 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2700 SoC1 Pin Controller
+
+maintainers:
+ - Billy Tsai <billy_tsai@aspeedtech.com>
+
+description:
+ The AST2700 features a dual-SoC architecture with two interconnected SoCs,
+ each having its own System Control Unit (SCU) for independent pin control.
+ This pin controller manages the pin multiplexing for SoC1.
+
+ The SoC1 pin controller manages pin functions including eSPI, LPC and I2C,
+ among others.
+
+properties:
+ compatible:
+ const: aspeed,ast2700-soc1-pinctrl
+ reg:
+ maxItems: 1
+
+patternProperties:
+ '-state$':
+ description: |
+ Pin control state.
+
+ If `function` is present, the node describes a pinmux state and must
+ specify `groups`.
+
+ For pin configuration, exactly one of `groups` or `pins` must be
+ specified in each state node. Group-level configuration applies to all
+ pins in the group. Pin-level configuration may be supplied in a
+ separate state node for individual pins; when both group-level and
+ pin-level configuration apply to the same pin, the pin-level
+ configuration takes precedence.
+
+ type: object
+ allOf:
+ - $ref: pinmux-node.yaml#
+ - $ref: pincfg-node.yaml#
+ - if:
+ required:
+ - function
+ then:
+ required:
+ - groups
+ - oneOf:
+ - required:
+ - groups
+ - required:
+ - pins
+ additionalProperties: false
+
+ properties:
+ function:
+ enum:
+ - ADC0
+ - ADC1
+ - ADC10
+ - ADC11
+ - ADC12
+ - ADC13
+ - ADC14
+ - ADC15
+ - ADC2
+ - ADC3
+ - ADC4
+ - ADC5
+ - ADC6
+ - ADC7
+ - ADC8
+ - ADC9
+ - AUXPWRGOOD0
+ - AUXPWRGOOD1
+ - CANBUS
+ - ESPI0
+ - ESPI1
+ - FSI0
+ - FSI1
+ - FSI2
+ - FSI3
+ - FWQSPI
+ - FWSPIABR
+ - FWWPN
+ - HBLED
+ - I2C0
+ - I2C1
+ - I2C10
+ - I2C11
+ - I2C12
+ - I2C13
+ - I2C14
+ - I2C15
+ - I2C2
+ - I2C3
+ - I2C4
+ - I2C5
+ - I2C6
+ - I2C7
+ - I2C8
+ - I2C9
+ - I2CF0
+ - I2CF1
+ - I2CF2
+ - I3C0
+ - I3C1
+ - I3C10
+ - I3C11
+ - I3C12
+ - I3C13
+ - I3C14
+ - I3C15
+ - I3C2
+ - I3C3
+ - I3C4
+ - I3C5
+ - I3C6
+ - I3C7
+ - I3C8
+ - I3C9
+ - JTAGM1
+ - LPC0
+ - LPC1
+ - LTPI
+ - MACLINK0
+ - MACLINK1
+ - MACLINK2
+ - MDIO0
+ - MDIO1
+ - MDIO2
+ - NCTS0
+ - NCTS1
+ - NCTS5
+ - NCTS6
+ - NDCD0
+ - NDCD1
+ - NDCD5
+ - NDCD6
+ - NDSR0
+ - NDSR1
+ - NDSR5
+ - NDSR6
+ - NDTR0
+ - NDTR1
+ - NDTR5
+ - NDTR6
+ - NRI0
+ - NRI1
+ - NRI5
+ - NRI6
+ - NRTS0
+ - NRTS1
+ - NRTS5
+ - NRTS6
+ - OSCCLK
+ - PCIERC
+ - PWM0
+ - PWM1
+ - PWM10
+ - PWM11
+ - PWM12
+ - PWM13
+ - PWM14
+ - PWM15
+ - PWM2
+ - PWM3
+ - PWM4
+ - PWM5
+ - PWM6
+ - PWM7
+ - PWM8
+ - PWM9
+ - QSPI0
+ - QSPI1
+ - QSPI2
+ - RGMII0
+ - RGMII1
+ - RMII0
+ - RMII0RCLKO
+ - RMII1
+ - RMII1RCLKO
+ - SALT0
+ - SALT1
+ - SALT10
+ - SALT11
+ - SALT12
+ - SALT13
+ - SALT14
+ - SALT15
+ - SALT2
+ - SALT3
+ - SALT4
+ - SALT5
+ - SALT6
+ - SALT7
+ - SALT8
+ - SALT9
+ - SD
+ - SGMII
+ - SGPM0
+ - SGPM1
+ - SGPS
+ - SIOONCTRLN0
+ - SIOONCTRLN1
+ - SIOPBIN0
+ - SIOPBIN1
+ - SIOPBON0
+ - SIOPBON1
+ - SIOPWREQN0
+ - SIOPWREQN1
+ - SIOPWRGD1
+ - SIOS3N0
+ - SIOS3N1
+ - SIOS5N0
+ - SIOS5N1
+ - SIOSCIN0
+ - SIOSCIN1
+ - SMON0
+ - SMON1
+ - SPI0
+ - SPI0ABR
+ - SPI0CS1
+ - SPI0WPN
+ - SPI1
+ - SPI1ABR
+ - SPI1CS1
+ - SPI1WPN
+ - SPI2
+ - SPI2CS1
+ - TACH0
+ - TACH1
+ - TACH10
+ - TACH11
+ - TACH12
+ - TACH13
+ - TACH14
+ - TACH15
+ - TACH2
+ - TACH3
+ - TACH4
+ - TACH5
+ - TACH6
+ - TACH7
+ - TACH8
+ - TACH9
+ - THRU0
+ - THRU1
+ - THRU2
+ - THRU3
+ - UART0
+ - UART1
+ - UART10
+ - UART11
+ - UART2
+ - UART3
+ - UART5
+ - UART6
+ - UART7
+ - UART8
+ - UART9
+ - USB2C
+ - USB2D
+ - USBUART
+ - VGA
+ - VPI
+ - WDTRST0N
+ - WDTRST1N
+ - WDTRST2N
+ - WDTRST3N
+ - WDTRST4N
+ - WDTRST5N
+ - WDTRST6N
+ - WDTRST7N
+
+ groups:
+ enum:
+ - ADC0
+ - ADC1
+ - ADC10
+ - ADC11
+ - ADC12
+ - ADC13
+ - ADC14
+ - ADC15
+ - ADC2
+ - ADC3
+ - ADC4
+ - ADC5
+ - ADC6
+ - ADC7
+ - ADC8
+ - ADC9
+ - AUXPWRGOOD0
+ - AUXPWRGOOD1
+ - CANBUS
+ - DI2C0
+ - DI2C1
+ - DI2C10
+ - DI2C11
+ - DI2C12
+ - DI2C13
+ - DI2C14
+ - DI2C15
+ - DI2C2
+ - DI2C3
+ - DI2C8
+ - DI2C9
+ - DSGPM0
+ - ESPI0
+ - ESPI1
+ - FSI0
+ - FSI1
+ - FSI2
+ - FSI3
+ - FWQSPI
+ - FWSPIABR
+ - FWWPN
+ - HBLED
+ - HVI3C0
+ - HVI3C1
+ - HVI3C12
+ - HVI3C13
+ - HVI3C14
+ - HVI3C15
+ - HVI3C2
+ - HVI3C3
+ - I2C0
+ - I2C1
+ - I2C10
+ - I2C11
+ - I2C12
+ - I2C13
+ - I2C14
+ - I2C15
+ - I2C2
+ - I2C3
+ - I2C4
+ - I2C5
+ - I2C6
+ - I2C7
+ - I2C8
+ - I2C9
+ - I2CF0
+ - I2CF1
+ - I2CF2
+ - I3C10
+ - I3C11
+ - I3C4
+ - I3C5
+ - I3C6
+ - I3C7
+ - I3C8
+ - I3C9
+ - JTAGM1
+ - LPC0
+ - LPC1
+ - LTPI
+ - LTPI_PS_I2C0
+ - LTPI_PS_I2C1
+ - LTPI_PS_I2C2
+ - LTPI_PS_I2C3
+ - MACLINK0
+ - MACLINK1
+ - MACLINK2
+ - MDIO0
+ - MDIO1
+ - MDIO2
+ - NCTS0
+ - NCTS1
+ - NCTS5
+ - NCTS6
+ - NDCD0
+ - NDCD1
+ - NDCD5
+ - NDCD6
+ - NDSR0
+ - NDSR1
+ - NDSR5
+ - NDSR6
+ - NDTR0
+ - NDTR1
+ - NDTR5
+ - NDTR6
+ - NRI0
+ - NRI1
+ - NRI5
+ - NRI6
+ - NRTS0
+ - NRTS1
+ - NRTS5
+ - NRTS6
+ - OSCCLK
+ - PE2SGRSTN
+ - PWM0
+ - PWM1
+ - PWM10
+ - PWM11
+ - PWM12
+ - PWM13
+ - PWM14
+ - PWM15
+ - PWM2
+ - PWM3
+ - PWM4
+ - PWM5
+ - PWM6
+ - PWM7
+ - PWM8
+ - PWM9
+ - QSPI0
+ - QSPI1
+ - QSPI2
+ - RGMII0
+ - RGMII1
+ - RMII0
+ - RMII0RCLKO
+ - RMII1
+ - RMII1RCLKO
+ - SALT0
+ - SALT1
+ - SALT10
+ - SALT11
+ - SALT12
+ - SALT13
+ - SALT14
+ - SALT15
+ - SALT2
+ - SALT3
+ - SALT4
+ - SALT5
+ - SALT6
+ - SALT7
+ - SALT8
+ - SALT9
+ - SD
+ - SGMII
+ - SGPM0
+ - SGPM1
+ - SGPS
+ - SIOONCTRLN0
+ - SIOONCTRLN1
+ - SIOPBIN0
+ - SIOPBIN1
+ - SIOPBON0
+ - SIOPBON1
+ - SIOPWREQN0
+ - SIOPWREQN1
+ - SIOPWRGD1
+ - SIOS3N0
+ - SIOS3N1
+ - SIOS5N0
+ - SIOS5N1
+ - SIOSCIN0
+ - SIOSCIN1
+ - SMON0
+ - SMON1
+ - SPI0
+ - SPI0ABR
+ - SPI0CS1
+ - SPI0WPN
+ - SPI1
+ - SPI1ABR
+ - SPI1CS1
+ - SPI1WPN
+ - SPI2
+ - SPI2CS1
+ - TACH0
+ - TACH1
+ - TACH10
+ - TACH11
+ - TACH12
+ - TACH13
+ - TACH14
+ - TACH15
+ - TACH2
+ - TACH3
+ - TACH4
+ - TACH5
+ - TACH6
+ - TACH7
+ - TACH8
+ - TACH9
+ - THRU0
+ - THRU1
+ - THRU2
+ - THRU3
+ - UART0
+ - UART1
+ - UART10
+ - UART11
+ - UART2
+ - UART3
+ - UART5
+ - UART6
+ - UART7
+ - UART8
+ - UART9
+ - USB2CD
+ - USB2CH
+ - USB2CU
+ - USB2CUD
+ - USB2DD
+ - USB2DH
+ - USBUART
+ - VGA
+ - VPI
+ - WDTRST0N
+ - WDTRST1N
+ - WDTRST2N
+ - WDTRST3N
+ - WDTRST4N
+ - WDTRST5N
+ - WDTRST6N
+ - WDTRST7N
+
+ pins:
+ enum:
+ - A14
+ - A15
+ - A18
+ - A19
+ - A21
+ - A22
+ - A23
+ - A24
+ - A25
+ - A26
+ - A6
+ - A7
+ - A8
+ - AA12
+ - AA13
+ - AA14
+ - AA15
+ - AA16
+ - AA17
+ - AA18
+ - AA20
+ - AA21
+ - AA22
+ - AA23
+ - AA24
+ - AA25
+ - AA26
+ - AB15
+ - AB16
+ - AB17
+ - AB18
+ - AB19
+ - AB20
+ - AB21
+ - AB22
+ - AB23
+ - AB24
+ - AB25
+ - AB26
+ - AC15
+ - AC16
+ - AC17
+ - AC18
+ - AC19
+ - AC20
+ - AC22
+ - AC24
+ - AC25
+ - AC26
+ - AD15
+ - AD16
+ - AD17
+ - AD18
+ - AD19
+ - AD20
+ - AD22
+ - AD25
+ - AD26
+ - AE16
+ - AE17
+ - AE18
+ - AE19
+ - AE20
+ - AE21
+ - AE23
+ - AE25
+ - AE26
+ - AF16
+ - AF17
+ - AF18
+ - AF19
+ - AF20
+ - AF21
+ - AF23
+ - AF25
+ - AF26
+ - B10
+ - B11
+ - B12
+ - B13
+ - B14
+ - B15
+ - B16
+ - B18
+ - B19
+ - B21
+ - B22
+ - B23
+ - B24
+ - B25
+ - B26
+ - B6
+ - B7
+ - B8
+ - B9
+ - C10
+ - C11
+ - C12
+ - C13
+ - C14
+ - C15
+ - C16
+ - C17
+ - C18
+ - C19
+ - C20
+ - C23
+ - C26
+ - C6
+ - C7
+ - C8
+ - C9
+ - D10
+ - D12
+ - D14
+ - D15
+ - D19
+ - D20
+ - D24
+ - D26
+ - D7
+ - D8
+ - D9
+ - E10
+ - E11
+ - E12
+ - E13
+ - E14
+ - E26
+ - E7
+ - E8
+ - E9
+ - F10
+ - F11
+ - F12
+ - F13
+ - F14
+ - F26
+ - F7
+ - F8
+ - F9
+ - G10
+ - G11
+ - G7
+ - G8
+ - G9
+ - H10
+ - H11
+ - H7
+ - H8
+ - H9
+ - J10
+ - J11
+ - J12
+ - J13
+ - J9
+ - K12
+ - K13
+ - L12
+ - M13
+ - M14
+ - M15
+ - M16
+ - N13
+ - N14
+ - N15
+ - N25
+ - N26
+ - P13
+ - P14
+ - P25
+ - P26
+ - R14
+ - R25
+ - R26
+ - T23
+ - T24
+ - U21
+ - U22
+ - U25
+ - U26
+ - V14
+ - V16
+ - V17
+ - V18
+ - V19
+ - V20
+ - V21
+ - V22
+ - V23
+ - V24
+ - W14
+ - W16
+ - W17
+ - W18
+ - W20
+ - W21
+ - W22
+ - W25
+ - W26
+ - Y11
+ - Y15
+ - Y16
+ - Y17
+ - Y18
+ - Y20
+ - Y21
+ - Y22
+ - Y23
+ - Y24
+ - Y25
+ - Y26
+
+ drive-strength:
+ enum: [4, 8, 12, 16]
+
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-down: true
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ pinctrl@400 {
+ compatible = "aspeed,ast2700-soc1-pinctrl";
+ reg = <0x400 0x2A0>;
+ sgpm0-state {
+ function = "SGPM0";
+ groups = "SGPM0";
+ };
+ };
--
2.34.1
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2026-05-15 9:37 [PATCH v3 0/3] pinctrl: aspeed: Add AST2700 SoC1 support Billy Tsai
2026-05-15 9:37 ` [PATCH v3 1/3] dt-bindings: mfd: aspeed,ast2x00-scu: Support AST2700 SoC1 pinctrl Billy Tsai
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