From: Colin Huang via B4 Relay <devnull+u8813345.gmail.com@kernel.org>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Joel Stanley <joel@jms.id.au>,
Andrew Jeffery <andrew@codeconstruct.com.au>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
colin.huang2@amd.com, Colin Huang <u8813345@gmail.com>,
Andy Chung <Andy.Chung@amd.com>
Subject: [PATCH v3 8/9] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC
Date: Tue, 02 Jun 2026 21:25:03 +0800 [thread overview]
Message-ID: <20260602-anacapa-devlop-phase-devicetree-v3-8-7c93c5df8d9b@gmail.com> (raw)
In-Reply-To: <20260602-anacapa-devlop-phase-devicetree-v3-0-7c93c5df8d9b@gmail.com>
From: Andy Chung <Andy.Chung@amd.com>
Add the mctp-controller property to enable frontend NIC management
via PLDM over MCTP.
Also add EEPROM device for NIC FRU and reorder the I2C virtual bus
index accroding to the system silkscreen index.
Signed-off-by: Andy Chung <Andy.Chung@amd.com>
---
.../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 98 ++++++++++++++++++----
1 file changed, 80 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts
index 29df10697613..5b6ce3c556fe 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts
@@ -35,22 +35,22 @@ aliases {
i2c33 = &i2c8mux0ch1;
i2c34 = &i2c8mux0ch2;
i2c35 = &i2c8mux0ch3;
- i2c36 = &i2c10mux0ch0;
- i2c37 = &i2c10mux0ch1;
- i2c38 = &i2c10mux0ch2;
- i2c39 = &i2c10mux0ch3;
- i2c40 = &i2c10mux0ch4;
- i2c41 = &i2c10mux0ch5;
- i2c42 = &i2c10mux0ch6;
- i2c43 = &i2c10mux0ch7;
- i2c44 = &i2c11mux0ch0;
- i2c45 = &i2c11mux0ch1;
- i2c46 = &i2c11mux0ch2;
- i2c47 = &i2c11mux0ch3;
- i2c48 = &i2c11mux0ch4;
- i2c49 = &i2c11mux0ch5;
- i2c50 = &i2c11mux0ch6;
- i2c51 = &i2c11mux0ch7;
+ i2c36 = &i2c11mux0ch5;
+ i2c37 = &i2c11mux0ch6;
+ i2c38 = &i2c11mux0ch7;
+ i2c39 = &i2c11mux0ch0;
+ i2c40 = &i2c11mux0ch1;
+ i2c41 = &i2c11mux0ch2;
+ i2c42 = &i2c11mux0ch3;
+ i2c43 = &i2c11mux0ch4;
+ i2c44 = &i2c10mux0ch1;
+ i2c45 = &i2c10mux0ch2;
+ i2c46 = &i2c10mux0ch3;
+ i2c47 = &i2c10mux0ch4;
+ i2c48 = &i2c10mux0ch5;
+ i2c49 = &i2c10mux0ch6;
+ i2c50 = &i2c10mux0ch7;
+ i2c51 = &i2c10mux0ch0;
i2c52 = &i2c13mux0ch0;
i2c53 = &i2c13mux0ch1;
i2c54 = &i2c13mux0ch2;
@@ -617,13 +617,17 @@ eeprom@56 {
// R Bridge Board
&i2c10 {
status = "okay";
+ multi-master;
+ mctp@10 {
+ compatible = "mctp-i2c-controller";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ };
i2c-mux@71 {
compatible = "nxp,pca9548";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
- i2c-mux-idle-disconnect;
i2c10mux0ch0: i2c@0 {
reg = <0>;
@@ -634,21 +638,45 @@ i2c10mux0ch1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c10mux0ch2: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c10mux0ch3: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c10mux0ch4: i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c10mux0ch5: i2c@5 {
reg = <5>;
@@ -694,38 +722,72 @@ i2c10mux0ch7: i2c@7 {
// L Bridge Board
&i2c11 {
status = "okay";
+ multi-master;
+ mctp@10 {
+ compatible = "mctp-i2c-controller";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ };
i2c-mux@71 {
compatible = "nxp,pca9548";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
- i2c-mux-idle-disconnect;
i2c11mux0ch0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // FE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c11mux0ch1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c11mux0ch2: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c11mux0ch3: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c11mux0ch4: i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
+ mctp-controller;
+ // BE NIC FRU
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
};
i2c11mux0ch5: i2c@5 {
reg = <5>;
--
2.34.1
next prev parent reply other threads:[~2026-06-02 13:25 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-02 13:24 [PATCH v3 0/9] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang via B4 Relay
2026-06-02 13:24 ` [PATCH v3 1/9] dt-bindings: arm: aspeed: add Anacapa EVT1 EVT2 DVT board Colin Huang via B4 Relay
2026-06-02 16:20 ` Conor Dooley
2026-06-02 13:24 ` [PATCH v3 2/9] ARM: dts: aspeed: anacapa: add EVT1 devicetree and point wrapper to it Colin Huang via B4 Relay
2026-06-02 13:24 ` [PATCH v3 3/9] ARM: dts: aspeed: anacapa: add EVT2 devicetree inheriting EVT1 Colin Huang via B4 Relay
2026-06-02 13:24 ` [PATCH v3 4/9] ARM: dts: aspeed: anacapa: add DVT devicetree inheriting EVT2 Colin Huang via B4 Relay
2026-06-02 13:25 ` [PATCH v3 5/9] ARM: dts: aspeed: anacapa: add additional EEPROM node for SCM Colin Huang via B4 Relay
2026-06-02 13:25 ` [PATCH v3 6/9] ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board Colin Huang via B4 Relay
2026-06-02 13:25 ` [PATCH v3 7/9] ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering Colin Huang via B4 Relay
2026-06-02 13:25 ` Colin Huang via B4 Relay [this message]
2026-06-02 13:25 ` [PATCH v3 9/9] ARM: dts: aspeed: anacapa: evt2: add shunt resistor values for HSC monitors Colin Huang via B4 Relay
2026-06-10 13:04 ` [PATCH v3 0/9] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Andrew Jeffery
2026-06-10 15:16 ` Colin Huang
2026-06-11 4:06 ` Andrew Jeffery
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