[PATCH 0/3] arm64: errata: Mitigate TLBI errata on various Arm CPUs

[Mark Rutland <mark.rutland@arm.com>]

A number of CPUs developed by Arm suffer from errata whereby a broadcast
TLBI;DSB sequence may complete before the global observation of writes
which are translated by an affected TLB entry.

The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate
the issue. This series enables the workaround on affected parts,
requiring the addition of MIDR values for C1-Ultra and C1-Premium.

I've based the series on the arm64 for-next/core branch to avoid
conflicts with the recent formatting changes to
Documentation/arch/arm64/silicon-errata.rst.

This issue has been assigned CVE ID CVE-2025-10263, and Arm have
published a security bulletin:

  https://developer.arm.com/documentation/112137/latest/

This will require manual backporting, so I haven't CC'd stable
explicitly. Once this is queueud I'll push out branches with backports
to the active stable trees.

Thanks,
Mark.

Mark Rutland (3):
  arm64: cputype: Add C1-Ultra definitions
  arm64: cputype: Add C1-Premium definitions
  arm64: errata: Mitigate TLBI errata on various Arm CPUs

 Documentation/arch/arm64/silicon-errata.rst | 42 +++++++++++++++++++++
 arch/arm64/Kconfig                          | 36 ++++++++++++++++++
 arch/arm64/include/asm/cputype.h            |  4 ++
 arch/arm64/kernel/cpu_errata.c              | 32 +++++++++++++++-
 4 files changed, 112 insertions(+), 2 deletions(-)

-- 
2.30.2