[PATCH_v2 0/3] clock-wizard fixups

[PATCH_v2 0/3] clock-wizard fixups

[Colin Foster]

The clock-wizard driver had a hard-coded 20KHz minimum accuracy. This
led to out-of-tree drivers silently failing to set clock rates instead
of dealing with the best-effort.

Remove this 20KHz restriction to match the Versal clock wizard driver.
There also was a bug in the difference calculation that is addressed in
the first patch.

The second patch optimizes the search if an exact match is found.

The third removes the restriction.

v2:
 * Rebase to apply cleanly
 * Add signoffs

Colin Foster (3):
  clk: clocking-wizard: fix clock difference detection
  clk: clocking-wizard: optimize clock search
  clk: clocking-wizard: remove 20kHz restriction

 drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

-- 
2.43.0

[PATCH_v2 1/3] clk: clocking-wizard: fix clock difference detection

[Colin Foster]

The diff calculation didn't take into account rollover. As such, a
target clock frequency below the requested rate would not be considered.

Before this change, bogus diffs would be used to determine the closest
possible clock:

8<--------
clk-wizard-test: requesting 133312500 Hz on output 0 (clock NOT enabled)
*** Clock wizard - Matching for rate 133312500 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 18446744073708237796
m = 34, d = 1, o = 26, freq = 130767923, diff = 18446744073707007039
m = 35, d = 1, o = 26, freq = 134614038, diff = 1301538
m = 36, d = 1, o = 27, freq = 133332000, diff = 19500
8<--------

After this change:

8<--------
clk-wizard-test: requesting 133312500 Hz on output 0 (clock NOT enabled)
*** Clock wizard - Matching for rate 133312500 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1313820
m = 35, d = 1, o = 26, freq = 134614038, diff = 1301538
m = 36, d = 1, o = 27, freq = 133332000, diff = 19500
8<--------

Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
---
 drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
index 4a0136349f71a..77c9d025ca8cf 100644
--- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
@@ -406,7 +406,7 @@ static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,
 			if (o < omin || o > omax)
 				continue;
 			freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o);
-			diff = freq - rate;
+			diff = abs(freq - rate);
 			if (diff < best_diff) {
 				best_diff = diff;
 				divider->m = m >> 3;
-- 
2.43.0

[PATCH_v2 2/3] clk: clocking-wizard: optimize clock search

[Colin Foster]

When an exact clock match is found, there is no need to continue
searching. This process was optimized for versal as part of
'commit e0a94c6bb5b4 ("clk: xilinx: Optimize divisor search in
clk_wzrd_get_divisors_ver()")' but that logic wasn't applied to
the non-versal driver.

Apply this fast-exit logic to the non-versal driver.

Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
---
 drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
index 77c9d025ca8cf..c7e8010afae52 100644
--- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
@@ -414,6 +414,9 @@ static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,
 				divider->d = d;
 				divider->o = o >> 3;
 				divider->o_frac = (o - (divider->o << 3)) * 125;
+
+				if (!diff)
+					return 0;
 			}
 		}
 	}
-- 
2.43.0

[PATCH_v2 3/3] clk: clocking-wizard: remove 20kHz restriction

[Colin Foster]

There is a 20KHz minimum target for clock difference that was baked into
the driver. This is unnecessary, and causes target clock frequencies to
be rejected that should otherwise succeed.

The discrepancy existed in versal drivers as well, but was removed as
part of 'commit e0a94c6bb5b4 ("clk: xilinx: Optimize divisor search in
clk_wzrd_get_divisors_ver()")'

Apply the change to allow differences >= 20kHz.

Before the change:

8<--------
clk-wizard-test: requesting 133312000 Hz on output 0 (clock NOT enabled)
*** Clock wizard - Matching for rate 133312000 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1313320
m = 35, d = 1, o = 26, freq = 134614038, diff = 1302038
m = 36, d = 1, o = 27, freq = 133332000, diff = 20000
*** Clock wizard - Matching for rate 133312000 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1313320
m = 35, d = 1, o = 26, freq = 134614038, diff = 1302038
m = 36, d = 1, o = 27, freq = 133332000, diff = 20000
clk-wizard-test: clk_set_rate(133312000) failed: -22
8<--------

After the change:

8<--------
clk-wizard-test: requesting 133312000 Hz on output 0 (clock NOT enabled)
*** Clock wizard - Matching for rate 133312000 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1313320
m = 35, d = 1, o = 26, freq = 134614038, diff = 1302038
m = 36, d = 1, o = 27, freq = 133332000, diff = 20000
*** Clock wizard - Matching for rate 133312000 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1313320
m = 35, d = 1, o = 26, freq = 134614038, diff = 1302038
m = 36, d = 1, o = 27, freq = 133332000, diff = 20000
*** Clock wizard - Matching for rate 133332000 parent rate 99999000
m = 33, d = 1, o = 25, freq = 131998680, diff = 1333320
m = 35, d = 1, o = 26, freq = 134614038, diff = 1282038
m = 36, d = 1, o = 27, freq = 133332000, diff = 0
clk-wizard-test: success -- actual rate: 133332000 Hz (requested 133312000 Hz, error 20000 Hz)
8<--------

Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
---
 drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
index c7e8010afae52..a8decb3ec40f4 100644
--- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
@@ -105,7 +105,6 @@
 #define VER_WZRD_VCO_MAX		4320000000ULL
 #define VER_WZRD_O_MIN			2
 #define VER_WZRD_O_MAX			511
-#define WZRD_MIN_ERR			20000
 #define WZRD_FRAC_POINTS		1000
 
 /* Get the mask from width */
@@ -420,7 +419,7 @@ static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,
 			}
 		}
 	}
-	return best_diff < WZRD_MIN_ERR ? 0 : -EBUSY;
+	return best_diff != -1ULL ? 0 : -EBUSY;
 }
 
 static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr)
-- 
2.43.0