From: Paul Louvel <paul.louvel@bootlin.com>
To: Qiang Zhao <qiang.zhao@nxp.com>,
"Christophe Leroy (CS GROUP)" <chleroy@kernel.org>,
Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
Madhavan Srinivasan <maddy@linux.ibm.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Nicholas Piggin <npiggin@gmail.com>
Cc: linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org,
Paul Louvel <paul.louvel@bootlin.com>,
Herve Codina <herve.codina@bootlin.com>
Subject: [PATCH v2 10/10] soc: fsl: qe: Add support of IRQs in QE GPIO
Date: Wed, 08 Jul 2026 12:15:23 +0200 [thread overview]
Message-ID: <20260708-qe-pic-gpios-v2-10-1972044cfbd1@bootlin.com> (raw)
In-Reply-To: <20260708-qe-pic-gpios-v2-0-1972044cfbd1@bootlin.com>
Some QE GPIO pins have an associated interrupt line in the QE PIC to
signal state changes on the pin.
Because the GPIO controller does not perform any interrupt handling
itself, a nexus node (interrupt-map) is used to map each GPIO line
supporting IRQ to the parent QE PIC interrupt domain.
Add the to_irq() method in the corresponding GPIO controller driver,
that uses the nexus node to perform the translation.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/soc/fsl/qe/gpio.c | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index 66828f2a3577..f8919642f40d 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -16,6 +16,7 @@
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/export.h>
+#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <soc/fsl/qe/qe.h>
@@ -23,6 +24,7 @@
#define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio)))
struct qe_gpio_chip {
+ struct device_node *np;
struct gpio_chip gc;
void __iomem *regs;
spinlock_t lock;
@@ -135,6 +137,29 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
return 0;
}
+static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
+ struct of_phandle_args oirq;
+ struct irq_domain *domain;
+ int ret;
+
+ oirq.np = qe_gc->np;
+ oirq.args_count = 2;
+ oirq.args[0] = gpio;
+ oirq.args[1] = 0;
+
+ ret = of_irq_parse_raw(NULL, &oirq);
+ if (ret)
+ return ret;
+
+ domain = irq_find_host(oirq.np);
+ if (!domain)
+ return -EPROBE_DEFER;
+
+ return irq_create_of_mapping(&oirq);
+}
+
struct qe_pin {
/*
* The qe_gpio_chip name is unfortunate, we should change that to
@@ -299,7 +324,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL);
if (!qe_gc)
return -ENOMEM;
-
+ qe_gc->np = np;
spin_lock_init(&qe_gc->lock);
gc = &qe_gc->gc;
@@ -311,6 +336,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
gc->get = qe_gpio_get;
gc->set = qe_gpio_set;
gc->set_multiple = qe_gpio_set_multiple;
+ gc->to_irq = qe_gpio_to_irq;
gc->parent = dev;
gc->owner = THIS_MODULE;
--
2.55.0
next prev parent reply other threads:[~2026-07-08 10:16 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-08 10:15 [PATCH v2 00/10] soc: fsl: qe: QE PIC improvement and add support of IRQs to QUICC ENGINE GPIOs Paul Louvel
2026-07-08 10:15 ` [PATCH v2 01/10] soc: fsl: qe: Add chained_irq_{enter,exit}() calls in cascade handler Paul Louvel
2026-07-08 10:15 ` [PATCH v2 02/10] dt-bindings: soc: fsl: qe: Set #interrupt-cells to 2 to support interrupt type encoding Paul Louvel
2026-07-08 10:15 ` [PATCH v2 03/10] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema Paul Louvel
2026-07-10 10:28 ` Krzysztof Kozlowski
2026-07-08 10:15 ` [PATCH v2 04/10] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO Paul Louvel
2026-07-10 10:28 ` Krzysztof Kozlowski
2026-07-08 10:15 ` [PATCH v2 05/10] soc: fsl: qe: Use generic_handle_domain_irq() Paul Louvel
2026-07-08 10:15 ` [PATCH v2 06/10] soc: fsl: qe: Iterate over all pending interrupts in cascade handler Paul Louvel
2026-07-08 10:15 ` [PATCH v2 07/10] soc: fsl: qe: Handle spurious interrupts Paul Louvel
2026-07-08 10:15 ` [PATCH v2 08/10] soc: fsl: qe: Convert to generic IRQ chip Paul Louvel
2026-07-08 10:15 ` [PATCH v2 09/10] soc: fsl: qe: Rename irq variable to parent_irq Paul Louvel
2026-07-08 10:15 ` Paul Louvel [this message]
2026-07-09 16:47 ` [PATCH v2 00/10] soc: fsl: qe: QE PIC improvement and add support of IRQs to QUICC ENGINE GPIOs Christophe Leroy (CS GROUP)
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