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From: Paul Louvel <paul.louvel@bootlin.com>
To: Qiang Zhao <qiang.zhao@nxp.com>,
	 "Christophe Leroy (CS GROUP)" <chleroy@kernel.org>,
	 Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Linus Walleij <linusw@kernel.org>,
	 Bartosz Golaszewski <brgl@kernel.org>,
	 Madhavan Srinivasan <maddy@linux.ibm.com>,
	 Michael Ellerman <mpe@ellerman.id.au>,
	Nicholas Piggin <npiggin@gmail.com>
Cc: linuxppc-dev@lists.ozlabs.org,
	linux-arm-kernel@lists.infradead.org,
	 linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	 linux-gpio@vger.kernel.org,
	Paul Louvel <paul.louvel@bootlin.com>,
	 Herve Codina <herve.codina@bootlin.com>
Subject: [PATCH v2 07/10] soc: fsl: qe: Handle spurious interrupts
Date: Wed, 08 Jul 2026 12:15:20 +0200	[thread overview]
Message-ID: <20260708-qe-pic-gpios-v2-7-1972044cfbd1@bootlin.com> (raw)
In-Reply-To: <20260708-qe-pic-gpios-v2-0-1972044cfbd1@bootlin.com>

When no interrupt bits are set in the event register, call
handle_bad_irq() to account for the spurious interrupt before
exiting the cascade handler.

Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
 drivers/soc/fsl/qe/qe_ports_ic.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports_ic.c
index bc8b68e5d1a9..29f4334db5a0 100644
--- a/drivers/soc/fsl/qe/qe_ports_ic.c
+++ b/drivers/soc/fsl/qe/qe_ports_ic.c
@@ -80,9 +80,15 @@ static void qepic_cascade(struct irq_desc *desc)
 	chained_irq_enter(chip, desc);
 
 	event = ioread32be(data->reg + CEPIER);
+	if (!event) {
+		handle_bad_irq(desc);
+		goto out;
+	}
+
 	for_each_set_bit(bit, &event, 32)
 		generic_handle_domain_irq(data->host, 31 - bit);
 
+out:
 	chained_irq_exit(chip, desc);
 }
 

-- 
2.55.0



  parent reply	other threads:[~2026-07-08 10:16 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-08 10:15 [PATCH v2 00/10] soc: fsl: qe: QE PIC improvement and add support of IRQs to QUICC ENGINE GPIOs Paul Louvel
2026-07-08 10:15 ` [PATCH v2 01/10] soc: fsl: qe: Add chained_irq_{enter,exit}() calls in cascade handler Paul Louvel
2026-07-08 10:15 ` [PATCH v2 02/10] dt-bindings: soc: fsl: qe: Set #interrupt-cells to 2 to support interrupt type encoding Paul Louvel
2026-07-08 10:15 ` [PATCH v2 03/10] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema Paul Louvel
2026-07-10 10:28   ` Krzysztof Kozlowski
2026-07-08 10:15 ` [PATCH v2 04/10] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO Paul Louvel
2026-07-10 10:28   ` Krzysztof Kozlowski
2026-07-08 10:15 ` [PATCH v2 05/10] soc: fsl: qe: Use generic_handle_domain_irq() Paul Louvel
2026-07-08 10:15 ` [PATCH v2 06/10] soc: fsl: qe: Iterate over all pending interrupts in cascade handler Paul Louvel
2026-07-08 10:15 ` Paul Louvel [this message]
2026-07-08 10:15 ` [PATCH v2 08/10] soc: fsl: qe: Convert to generic IRQ chip Paul Louvel
2026-07-08 10:15 ` [PATCH v2 09/10] soc: fsl: qe: Rename irq variable to parent_irq Paul Louvel
2026-07-08 10:15 ` [PATCH v2 10/10] soc: fsl: qe: Add support of IRQs in QE GPIO Paul Louvel
2026-07-09 16:47 ` [PATCH v2 00/10] soc: fsl: qe: QE PIC improvement and add support of IRQs to QUICC ENGINE GPIOs Christophe Leroy (CS GROUP)

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