From: Jason Gunthorpe <jgg@nvidia.com>
To: Mostafa Saleh <smostafa@google.com>
Cc: iommu@lists.linux.dev, "Joerg Roedel (AMD)" <joro@8bytes.org>,
Jean-Philippe Brucker <jpb@kernel.org>,
linux-arm-kernel@lists.infradead.org,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>,
David Matlack <dmatlack@google.com>,
Pasha Tatashin <pasha.tatashin@soleen.com>,
patches@lists.linux.dev, Pranjal Shrivastava <praan@google.com>,
Samiullah Khawaja <skhawaja@google.com>
Subject: Re: [PATCH v2 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency
Date: Tue, 7 Jul 2026 21:10:58 -0300 [thread overview]
Message-ID: <20260708001058.GA422027@nvidia.com> (raw)
In-Reply-To: <akzm5BoV0rToJ7ij@google.com>
On Tue, Jul 07, 2026 at 11:45:40AM +0000, Mostafa Saleh wrote:
> > Calculate the smallest SCALE such that NUM can cover the range to minimize
> > over-invalidation. Always use a RIL command if RIL is possible working
> > around the spec limitations to form a valid one. If RIL is not possible
> > then do full invalidation.
> >
>
> That may be beneficial for servers, but I am not sure about other use
> cases, we already know that the invalidated entries are unmapped
> and not used. However, over invalidating might impact live DMA which
> would be bad for workloads sensitive to translation latency (as
> embedded cameras, displays for example).
The isochronos stuff I've seen has a latency budget for translation
lookups and has to be tolerant of an occasional full walk.
Prior to RIL you had a much bigger issue, the cap on the range ment
you'd face a full invalidation from time to time if the domain is
being used for DMA while something ischronous is ongoing. Compared to
that a RIL over invalidation is not significant.
I have been talking to people about some formal isochronos support
that could do several things to try to manage the latency of DMA, it
would be reasonable to include some alternative RIL algorithm here if
that happens someday, and it is an issue.
But otherwise, I think we should leave it. Over invalidation is
consistent with how single works, and single has a long history in the
field so I don't think RIL is any worse.
> > At least one invalidation errata is avoided by 'always use RIL'.
>
> Can you please clarify what that means?
Errata 3673557 requires using RIL if CONT is used otherwise there can
be stale entries
> > +static bool arm_smmu_cmdq_batch_add_single(struct arm_smmu_device *smmu,
> > + struct arm_smmu_cmdq_batch *cmds,
> > + struct arm_smmu_cmd *cmd,
> > + struct arm_smmu_tlbi *tlbi)
> > +{
> > + unsigned long num_ops = tlbi->size / tlbi->iopte_granule;
> > + unsigned long iova = tlbi->iova;
> > + unsigned long i;
> > +
> > + if (!num_ops || num_ops > 512)
>
> Is there a reason that was added instead of keeping the old formula?
The original was based on address range as an imperfect proxy for
number of operations, here we can compute exactly the number of
operations given the required tg and level being targetted.
Under the PAGE_SIZE condition this is equivalent. Under
something like 2M huge pages this avoids falling back to full
invalidation in more cases.
Jason
next prev parent reply other threads:[~2026-07-08 0:11 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-06 16:26 [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 1/8] iommu/arm-smmu-v3: Pass the parameters for the invalidation in a struct Jason Gunthorpe
2026-07-07 3:04 ` Nicolin Chen
2026-07-07 11:18 ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 2/8] iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv Jason Gunthorpe
2026-07-07 3:57 ` Nicolin Chen
2026-07-07 16:15 ` Jason Gunthorpe
2026-07-07 17:21 ` Nicolin Chen
2026-07-07 11:24 ` Mostafa Saleh
2026-07-07 18:08 ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency Jason Gunthorpe
2026-07-07 7:27 ` Nicolin Chen
2026-07-07 19:13 ` Jason Gunthorpe
2026-07-07 21:07 ` Nicolin Chen
2026-07-07 11:45 ` Mostafa Saleh
2026-07-08 0:10 ` Jason Gunthorpe [this message]
2026-07-06 16:26 ` [PATCH v2 4/8] iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used Jason Gunthorpe
2026-07-07 7:27 ` Nicolin Chen
2026-07-07 11:46 ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands Jason Gunthorpe
2026-07-07 11:52 ` Mostafa Saleh
2026-07-07 14:58 ` Jason Gunthorpe
2026-07-08 9:00 ` Mostafa Saleh
2026-07-08 13:15 ` Jason Gunthorpe
2026-07-07 20:31 ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 6/8] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain Jason Gunthorpe
2026-07-07 11:57 ` Mostafa Saleh
2026-07-07 21:51 ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Jason Gunthorpe
2026-07-06 18:00 ` Robin Murphy
2026-07-06 19:45 ` Jason Gunthorpe
2026-07-08 1:41 ` Nicolin Chen
2026-07-08 5:29 ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 8/8] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE Jason Gunthorpe
2026-07-07 23:20 ` Nicolin Chen
2026-07-08 0:02 ` Jason Gunthorpe
2026-07-08 2:10 ` Nicolin Chen
2026-07-08 13:05 ` Jason Gunthorpe
2026-07-07 12:25 ` [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Mostafa Saleh
2026-07-07 15:00 ` Jason Gunthorpe
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