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From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: <iommu@lists.linux.dev>, "Joerg Roedel (AMD)" <joro@8bytes.org>,
	Jean-Philippe Brucker <jpb@kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>,
	David Matlack <dmatlack@google.com>,
	"Pasha Tatashin" <pasha.tatashin@soleen.com>,
	<patches@lists.linux.dev>,
	"Pranjal Shrivastava" <praan@google.com>,
	Samiullah Khawaja <skhawaja@google.com>,
	Mostafa Saleh <smostafa@google.com>
Subject: Re: [PATCH v2 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands
Date: Tue, 7 Jul 2026 13:31:53 -0700	[thread overview]
Message-ID: <ak1iOWrvLv/6ACsP@Asurada-Nvidia> (raw)
In-Reply-To: <5-v2-43074a57a53a+fb95-smmu_tlbi_jgg@nvidia.com>

On Mon, Jul 06, 2026 at 01:26:42PM -0300, Jason Gunthorpe wrote:
> @@ -2471,10 +2451,13 @@ static bool arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu,
>  	if (num_tg == 1) {
>  		if (!ttl)
>  			ttl = 3;
> -		arm_smmu_cmdq_batch_add_ril(smmu, cmds, cmd, tlbi->leaf_only,
> -					    cur_tg << tg_lg2, 0, 0, ttl,
> -					    tg_enc);
> -		return true;
> +		tlbi->range.data0 = 0;
> +		tlbi->range.data1 =
> +			FIELD_PREP(CMDQ_TLBI_1_LEAF, tlbi->leaf_only) |
> +			FIELD_PREP(CMDQ_TLBI_1_TTL, ttl) |
> +			FIELD_PREP(CMDQ_TLBI_1_TG, tg_enc) |
> +			(cur_tg << tg_lg2);
> +		return;
>  	}
[...]
> +	tlbi->range.data0 =
> +		FIELD_PREP(CMDQ_TLBI_0_NUM,
> +			   DIV_ROUND_UP_ULL(num_tg, 1ULL << scale) - 1) |
> +		FIELD_PREP(CMDQ_TLBI_0_SCALE, scale);
> +	tlbi->range.data1 = FIELD_PREP(CMDQ_TLBI_1_LEAF, tlbi->leaf_only) |
> +			    FIELD_PREP(CMDQ_TLBI_1_TTL, ttl) |
> +			    FIELD_PREP(CMDQ_TLBI_1_TG, tg_enc) |
> +			    (cur_tg << tg_lg2);

Could this be slightly cleaner:

	unsigned int num = 0, scale = 0;
	...
	if (num_tg == 1) {
		if (!ttl)
			ttl = 3;
		goto build;
	}

	scale = fls64((num_tg - 1) / 32);
	num = DIV_ROUND_UP_ULL(num_tg, 1ULL << scale) - 1;
build:
	tlbi->range.data0 = FIELD_PREP(CMDQ_TLBI_0_NUM, num) |
			    FIELD_PREP(CMDQ_TLBI_0_SCALE, scale);
	tlbi->range.data1 = FIELD_PREP(CMDQ_TLBI_1_LEAF, tlbi->leaf_only) |
			    FIELD_PREP(CMDQ_TLBI_1_TTL, ttl) |
			    FIELD_PREP(CMDQ_TLBI_1_TG, tg_enc) |
			    (cur_tg << tg_lg2);

?

> @@ -2711,6 +2711,14 @@ void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain,
>  	rcu_read_lock();
>  	invs = rcu_dereference(smmu_domain->invs);
>  
> +	/* Only precaculate RIL if it will be used. */

precalculate

> +	if (invs->has_range_inv) {
> +		if (!tlbi.range.use_full_inv)
> +			arm_smmu_tlbi_calc_range(&tlbi);
> +	} else {
> +		tlbi.range.use_full_inv = true;

I am a bit unsure about this line since invs has no RIL entry.

Is it set for a defensive reason?

Nicolin


  parent reply	other threads:[~2026-07-07 20:32 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-06 16:26 [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 1/8] iommu/arm-smmu-v3: Pass the parameters for the invalidation in a struct Jason Gunthorpe
2026-07-07  3:04   ` Nicolin Chen
2026-07-07 11:18   ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 2/8] iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv Jason Gunthorpe
2026-07-07  3:57   ` Nicolin Chen
2026-07-07 16:15     ` Jason Gunthorpe
2026-07-07 17:21       ` Nicolin Chen
2026-07-07 11:24   ` Mostafa Saleh
2026-07-07 18:08     ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency Jason Gunthorpe
2026-07-07  7:27   ` Nicolin Chen
2026-07-07 19:13     ` Jason Gunthorpe
2026-07-07 21:07       ` Nicolin Chen
2026-07-07 11:45   ` Mostafa Saleh
2026-07-08  0:10     ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 4/8] iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used Jason Gunthorpe
2026-07-07  7:27   ` Nicolin Chen
2026-07-07 11:46   ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands Jason Gunthorpe
2026-07-07 11:52   ` Mostafa Saleh
2026-07-07 14:58     ` Jason Gunthorpe
2026-07-07 20:31   ` Nicolin Chen [this message]
2026-07-06 16:26 ` [PATCH v2 6/8] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain Jason Gunthorpe
2026-07-07 11:57   ` Mostafa Saleh
2026-07-07 21:51   ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Jason Gunthorpe
2026-07-06 18:00   ` Robin Murphy
2026-07-06 19:45     ` Jason Gunthorpe
2026-07-08  1:41   ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 8/8] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE Jason Gunthorpe
2026-07-07 23:20   ` Nicolin Chen
2026-07-08  0:02     ` Jason Gunthorpe
2026-07-08  2:10       ` Nicolin Chen
2026-07-07 12:25 ` [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Mostafa Saleh
2026-07-07 15:00   ` Jason Gunthorpe

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