From: Mark Brown <broonie@kernel.org>
To: Marc Zyngier <maz@kernel.org>, Joey Gouly <joey.gouly@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
Oliver Upton <oupton@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>, Fuad Tabba <tabba@google.com>,
Mark Rutland <mark.rutland@arm.com>,
Ben Horgan <ben.horgan@arm.com>,
Jean-Philippe Brucker <jpb@kernel.org>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Peter Maydell <peter.maydell@linaro.org>,
Eric Auger <eric.auger@redhat.com>,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v11 29/29] KVM: arm64: selftests: Add SME to set_id_regs test
Date: Thu, 09 Jul 2026 01:52:06 +0100 [thread overview]
Message-ID: <20260709-kvm-arm64-sme-v11-29-32799f66db9d@kernel.org> (raw)
In-Reply-To: <20260709-kvm-arm64-sme-v11-0-32799f66db9d@kernel.org>
Add coverage of the SME ID registers to set_id_regs, ID_AA64PFR1_EL1.SME
becomes writable and we add ID_AA64SMFR0_EL1 and it's subfields.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
tools/testing/selftests/kvm/arm64/set_id_regs.c | 30 +++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testing/selftests/kvm/arm64/set_id_regs.c
index da9349bf31ab..26db507f6e73 100644
--- a/tools/testing/selftests/kvm/arm64/set_id_regs.c
+++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c
@@ -155,6 +155,7 @@ static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = {
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, DF2, 0),
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SME, 0),
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI),
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0),
REG_FTR_END,
@@ -212,6 +213,33 @@ static const struct reg_ftr_bits ftr_id_aa64mmfr3_el1[] = {
REG_FTR_END,
};
+static const struct reg_ftr_bits ftr_id_aa64smfr0_el1[] = {
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, FA64, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, LUTv2, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SMEver, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, I16I64, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F64F64, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, I16I32, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, B16B16, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F16F16, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F8F16, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F8F32, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, I8I32, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F16F32, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, B16F32, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, BI32I32, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F32F32, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SF8FMA, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SF8DP4, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SF8DP2, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SBitPerm, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, AES, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SFEXPA, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, STMOP, 0),
+ REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SMOP4, 0),
+ REG_FTR_END,
+};
+
static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
@@ -244,6 +272,7 @@ static struct test_feature_reg test_regs[] = {
TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
TEST_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1),
+ TEST_REG(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0_el1),
TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
};
@@ -263,6 +292,7 @@ static void guest_code(void)
GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
GUEST_REG_SYNC(SYS_ID_AA64MMFR3_EL1);
+ GUEST_REG_SYNC(SYS_ID_AA64SMFR0_EL1);
GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
GUEST_REG_SYNC(SYS_MPIDR_EL1);
GUEST_REG_SYNC(SYS_CLIDR_EL1);
--
2.47.3
next prev parent reply other threads:[~2026-07-09 0:54 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-09 0:51 [PATCH v11 00/29] KVM: arm64: Implement support for SME Mark Brown
2026-07-09 0:51 ` [PATCH v11 01/29] arm64/sysreg: Define full value read/modify/write helpers Mark Brown
2026-07-09 0:51 ` [PATCH v11 02/29] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state Mark Brown
2026-07-09 0:51 ` [PATCH v11 03/29] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Mark Brown
2026-07-09 0:51 ` [PATCH v11 04/29] arm64/sve: Factor virtualizable VL discovery out of SVE specific code Mark Brown
2026-07-09 0:51 ` [PATCH v11 05/29] arm64/fpsimd: Determine maximum virtualisable SME vector length Mark Brown
2026-07-09 0:51 ` [PATCH v11 06/29] KVM: arm64: Handle FEAT_IDST for guest accesses to hidden registers Mark Brown
2026-07-09 0:51 ` [PATCH v11 07/29] KVM: arm64: Pull ctxt_has_ helpers to start of sysreg-sr.h Mark Brown
2026-07-09 0:51 ` [PATCH v11 08/29] KVM: arm64: Rename SVE finalization constants to be more general Mark Brown
2026-07-09 0:51 ` [PATCH v11 09/29] KVM: arm64: Define internal features for SME Mark Brown
2026-07-09 0:51 ` [PATCH v11 10/29] KVM: arm64: Rename sve_state_reg_region Mark Brown
2026-07-09 0:51 ` [PATCH v11 11/29] KVM: arm64: Store vector lengths in an array Mark Brown
2026-07-09 0:51 ` [PATCH v11 12/29] KVM: arm64: Factor SVE code out of fpsimd_lazy_switch_to_host() Mark Brown
2026-07-09 0:51 ` [PATCH v11 13/29] KVM: arm64: Document the KVM ABI for SME Mark Brown
2026-07-09 0:51 ` [PATCH v11 14/29] KVM: arm64: Implement SME vector length configuration Mark Brown
2026-07-09 0:51 ` [PATCH v11 15/29] KVM: arm64: Support SME control registers Mark Brown
2026-07-09 0:51 ` [PATCH v11 16/29] KVM: arm64: Support TPIDR2_EL0 Mark Brown
2026-07-09 0:51 ` [PATCH v11 17/29] KVM: arm64: Support SME identification registers for guests Mark Brown
2026-07-09 0:51 ` [PATCH v11 18/29] KVM: arm64: Support SME priority registers Mark Brown
2026-07-09 0:51 ` [PATCH v11 19/29] KVM: arm64: Support userspace access to streaming mode Z and P registers Mark Brown
2026-07-09 0:51 ` [PATCH v11 20/29] KVM: arm64: Flush register state on writes to SVCR.SM and SVCR.ZA Mark Brown
2026-07-09 0:51 ` [PATCH v11 21/29] KVM: arm64: Expose SME specific state to userspace Mark Brown
2026-07-09 0:51 ` [PATCH v11 22/29] KVM: arm64: Context switch SME state for guests Mark Brown
2026-07-09 0:52 ` [PATCH v11 23/29] KVM: arm64: Handle SME exceptions Mark Brown
2026-07-09 0:52 ` [PATCH v11 24/29] KVM: arm64: Expose SME to nested guests Mark Brown
2026-07-09 0:52 ` [PATCH v11 25/29] KVM: arm64: Provide interface for configuring and enabling SME for guests Mark Brown
2026-07-09 0:52 ` [PATCH v11 26/29] KVM: arm64: selftests: Remove spurious check for single bit safe values Mark Brown
2026-07-09 0:52 ` [PATCH v11 27/29] KVM: arm64: selftests: Skip impossible invalid value tests Mark Brown
2026-07-09 0:52 ` [PATCH v11 28/29] KVM: arm64: selftests: Add SME system registers to get-reg-list Mark Brown
2026-07-09 0:52 ` Mark Brown [this message]
2026-07-09 10:26 ` [PATCH v11 00/29] KVM: arm64: Implement support for SME Fuad Tabba
2026-07-09 11:28 ` Mark Rutland
2026-07-09 11:31 ` Fuad Tabba
2026-07-09 11:43 ` Mark Brown
2026-07-09 11:49 ` Mark Rutland
2026-07-09 12:08 ` Fuad Tabba
2026-07-09 11:36 ` Mark Brown
2026-07-09 11:49 ` Fuad Tabba
2026-07-09 12:21 ` Mark Brown
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