* [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC
@ 2026-07-11 20:59 Marek Vasut
2026-07-11 20:59 ` [PATCH 01/10] dt-bindings: arm: stm32: Document " Marek Vasut
` (9 more replies)
0 siblings, 10 replies; 19+ messages in thread
From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley,
Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree,
kernel, linux-gpio, linux-kernel, linux-stm32
This stm32mp25xx-dhcos-bb board is a stack of DHCOS SoM based on
STM32MP25xx SoC (1200MHz / crypto capabilities) populated on SoM
Breakout Board, the stm32mp255c-dhcos-dhsbc is the SoM populated
on DHSBC carrier board. The stm32mp23xx-dhcos-bb is a stack with
STM32MP23xx SoC.
The SoM contains the following peripherals:
- STPMIC (power delivery)
- 4GiB LPDDR4 memory
- eMMC and SDIO WiFi module
The Breakout Board carrier board contains the following peripherals:
- USB-C peripheral port, power supply plug
The DHSBC carrier board contains the following peripherals:
- Two RGMII Ethernet ports
- MicroSD slot
- LVDS connector
- MIPI CSI2 connector
- USB-A Host port, USB-C power supply plug
- USB-C / DP port
- Expansion connector
Marek Vasut (10):
dt-bindings: arm: stm32: Document STM32MP23xx/STM32MP25xx DHCOS SoM
and Breakout Board and DHSBC
dt-bindings: gpio: pca95xx: Document Kinetic KTS1622
arm64: dts: st: Fix SDMMC1 indent on stm32mp231
arm64: dts: st: Fix SDMMC1 indent on stm32mp251
arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp231
arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp251
arm64: dts: st: Add OMM node on stm32mp231
arm64: dts: st: Add pinmux nodes for DH electronics
STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board
arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx
DHCOS SoM and Breakout Board and DHSBC
MAINTAINERS: Add DH electronics DHCOS SoM entry and fix email address
.../devicetree/bindings/arm/stm32/stm32.yaml | 18 +
.../bindings/gpio/gpio-pca95xx.yaml | 3 +
MAINTAINERS | 3 +-
arch/arm64/boot/dts/st/Makefile | 10 +
arch/arm64/boot/dts/st/stm32mp231.dtsi | 86 ++-
arch/arm64/boot/dts/st/stm32mp23xc.dtsi | 7 +
.../boot/dts/st/stm32mp23xx-dhcos-bb.dts | 15 +
.../boot/dts/st/stm32mp23xx-dhcos-som.dtsi | 51 ++
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 564 ++++++++++++++++++
arch/arm64/boot/dts/st/stm32mp251.dtsi | 32 +-
...mp255c-dhcos-dhsbc-overlay-imx219-x10.dtso | 111 ++++
.../boot/dts/st/stm32mp255c-dhcos-dhsbc.dts | 189 ++++++
arch/arm64/boot/dts/st/stm32mp25xc.dtsi | 7 +
.../boot/dts/st/stm32mp25xx-dhcos-bb.dts | 15 +
.../boot/dts/st/stm32mp25xx-dhcos-som.dtsi | 51 ++
.../boot/dts/st/stm32mp2xxx-dhcos-som.dtsi | 442 ++++++++++++++
16 files changed, 1601 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/st/stm32mp23xc.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp23xx-dhcos-bb.dts
create mode 100644 arch/arm64/boot/dts/st/stm32mp23xx-dhcos-som.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp255c-dhcos-dhsbc-overlay-imx219-x10.dtso
create mode 100644 arch/arm64/boot/dts/st/stm32mp255c-dhcos-dhsbc.dts
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xc.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xx-dhcos-bb.dts
create mode 100644 arch/arm64/boot/dts/st/stm32mp25xx-dhcos-som.dtsi
create mode 100644 arch/arm64/boot/dts/st/stm32mp2xxx-dhcos-som.dtsi
---
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Bartosz Golaszewski <brgl@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Linus Walleij <linusw@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: kernel@dh-electronics.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
--
2.53.0
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH 01/10] dt-bindings: arm: stm32: Document STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut @ 2026-07-11 20:59 ` Marek Vasut 2026-07-13 7:48 ` Krzysztof Kozlowski 2026-07-11 20:59 ` [PATCH 02/10] dt-bindings: gpio: pca95xx: Document Kinetic KTS1622 Marek Vasut ` (8 subsequent siblings) 9 siblings, 1 reply; 19+ messages in thread From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw) To: linux-arm-kernel Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 This stm32mp25xx-dhcos-bb board is a stack of DHCOS SoM based on STM32MP25xx SoC (1200MHz / crypto capabilities) populated on SoM Breakout Board, the stm32mp255c-dhcos-dhsbc is the SoM populated on DHSBC carrier board. The stm32mp23xx-dhcos-bb is a stack with STM32MP23xx SoC. The SoM contains the following peripherals: - STPMIC (power delivery) - 4GiB LPDDR4 memory - eMMC and SDIO WiFi module The Breakout Board carrier board contains the following peripherals: - USB-C peripheral port, power supply plug The DHSBC carrier board contains the following peripherals: - Two RGMII Ethernet ports - MicroSD slot - LVDS connector - MIPI CSI2 connector - USB-A Host port, USB-C power supply plug - USB-C / DP port - Expansion connector Signed-off-by: Marek Vasut <marex@nabladev.com> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Bartosz Golaszewski <brgl@kernel.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Linus Walleij <linusw@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- .../devicetree/bindings/arm/stm32/stm32.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index c6af3a46364fc..2045dc2e54a60 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -196,6 +196,18 @@ properties: - const: ultratronik,stm32mp157c-ultra-fly-sbc - const: st,stm32mp157 + - description: DH STM32MP251 DHCOS SoM based Boards + items: + - const: dh,stm32mp251a-dhcos-bb + - const: dh,stm32mp251a-dhcos-som + - const: st,stm32mp251 + + - description: DH STM32MP255 DHCOS SoM based Boards + items: + - const: dh,stm32mp255c-dhcos-dhsbc + - const: dh,stm32mp255c-dhcos-som + - const: st,stm32mp255 + - description: ST STM32MP257 based Boards items: - enum: @@ -203,6 +215,12 @@ properties: - st,stm32mp257f-ev1 - const: st,stm32mp257 + - description: DH STM32MP231 DHCOS SoM based Boards + items: + - const: dh,stm32mp231a-dhcos-bb + - const: dh,stm32mp231a-dhcos-som + - const: st,stm32mp231 + - description: ST STM32MP235 based Boards items: - enum: -- 2.53.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 01/10] dt-bindings: arm: stm32: Document STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC 2026-07-11 20:59 ` [PATCH 01/10] dt-bindings: arm: stm32: Document " Marek Vasut @ 2026-07-13 7:48 ` Krzysztof Kozlowski 2026-07-13 10:31 ` Marek Vasut 0 siblings, 1 reply; 19+ messages in thread From: Krzysztof Kozlowski @ 2026-07-13 7:48 UTC (permalink / raw) To: Marek Vasut Cc: linux-arm-kernel, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 On Sat, Jul 11, 2026 at 10:59:30PM +0200, Marek Vasut wrote: > - description: ST STM32MP257 based Boards > items: > - enum: > @@ -203,6 +215,12 @@ properties: > - st,stm32mp257f-ev1 > - const: st,stm32mp257 > > + - description: DH STM32MP231 DHCOS SoM based Boards > + items: > + - const: dh,stm32mp231a-dhcos-bb > + - const: dh,stm32mp231a-dhcos-som > + - const: st,stm32mp231 This should be after st,stm32mp157 group and before st,stm32mp251 to be sorted by fallback compatible. Anyway, not a big deal, so: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 01/10] dt-bindings: arm: stm32: Document STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC 2026-07-13 7:48 ` Krzysztof Kozlowski @ 2026-07-13 10:31 ` Marek Vasut 0 siblings, 0 replies; 19+ messages in thread From: Marek Vasut @ 2026-07-13 10:31 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: linux-arm-kernel, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 On 7/13/26 9:48 AM, Krzysztof Kozlowski wrote: > On Sat, Jul 11, 2026 at 10:59:30PM +0200, Marek Vasut wrote: >> - description: ST STM32MP257 based Boards >> items: >> - enum: >> @@ -203,6 +215,12 @@ properties: >> - st,stm32mp257f-ev1 >> - const: st,stm32mp257 >> >> + - description: DH STM32MP231 DHCOS SoM based Boards >> + items: >> + - const: dh,stm32mp231a-dhcos-bb >> + - const: dh,stm32mp231a-dhcos-som >> + - const: st,stm32mp231 > > This should be after st,stm32mp157 group and before st,stm32mp251 to be > sorted by fallback compatible. > > Anyway, not a big deal, so: I'll send a sort patch for this schema file shortly and then a V2 of this series once I get a bit more feedback. ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 02/10] dt-bindings: gpio: pca95xx: Document Kinetic KTS1622 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut 2026-07-11 20:59 ` [PATCH 01/10] dt-bindings: arm: stm32: Document " Marek Vasut @ 2026-07-11 20:59 ` Marek Vasut 2026-07-13 7:49 ` Krzysztof Kozlowski 2026-07-13 8:36 ` Bartosz Golaszewski 2026-07-11 20:59 ` [PATCH 03/10] arm64: dts: st: Fix SDMMC1 indent on stm32mp231 Marek Vasut ` (7 subsequent siblings) 9 siblings, 2 replies; 19+ messages in thread From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw) To: linux-arm-kernel Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 The Kinetic Technologies KTS1622 is a 16-bit general-purpose I/O expander via the I2C bus for microcontrollers when additional I/Os are needed while keeping interconnections to the minimum. Datasheet comparison suggests that it is compatible with TCAL6416, add the compatible string and TCAL6416 as a fallback compatible. Signed-off-by: Marek Vasut <marex@nabladev.com> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Bartosz Golaszewski <brgl@kernel.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Linus Walleij <linusw@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml index 4f955f855e1ab..4631388a7d914 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml @@ -22,6 +22,9 @@ properties: - items: - const: diodes,pi4ioe5v6534q - const: nxp,pcal6534 + - items: + - const: kinetic,kts1622 + - const: ti,tcal6416 - items: - enum: - exar,xra1202 -- 2.53.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 02/10] dt-bindings: gpio: pca95xx: Document Kinetic KTS1622 2026-07-11 20:59 ` [PATCH 02/10] dt-bindings: gpio: pca95xx: Document Kinetic KTS1622 Marek Vasut @ 2026-07-13 7:49 ` Krzysztof Kozlowski 2026-07-13 8:36 ` Bartosz Golaszewski 1 sibling, 0 replies; 19+ messages in thread From: Krzysztof Kozlowski @ 2026-07-13 7:49 UTC (permalink / raw) To: Marek Vasut Cc: linux-arm-kernel, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 On Sat, Jul 11, 2026 at 10:59:31PM +0200, Marek Vasut wrote: > The Kinetic Technologies KTS1622 is a 16-bit general-purpose I/O > expander via the I2C bus for microcontrollers when additional I/Os > are needed while keeping interconnections to the minimum. Datasheet > comparison suggests that it is compatible with TCAL6416, add the > compatible string and TCAL6416 as a fallback compatible. Your commit msgs feel too early wrapped. https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597 > > Signed-off-by: Marek Vasut <marex@nabladev.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 02/10] dt-bindings: gpio: pca95xx: Document Kinetic KTS1622 2026-07-11 20:59 ` [PATCH 02/10] dt-bindings: gpio: pca95xx: Document Kinetic KTS1622 Marek Vasut 2026-07-13 7:49 ` Krzysztof Kozlowski @ 2026-07-13 8:36 ` Bartosz Golaszewski 2026-07-13 10:33 ` Marek Vasut 1 sibling, 1 reply; 19+ messages in thread From: Bartosz Golaszewski @ 2026-07-13 8:36 UTC (permalink / raw) To: Marek Vasut Cc: Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32, linux-arm-kernel On Sat, 11 Jul 2026 22:59:31 +0200, Marek Vasut <marex@nabladev.com> said: > The Kinetic Technologies KTS1622 is a 16-bit general-purpose I/O > expander via the I2C bus for microcontrollers when additional I/Os > are needed while keeping interconnections to the minimum. Datasheet > comparison suggests that it is compatible with TCAL6416, add the > compatible string and TCAL6416 as a fallback compatible. > > Signed-off-by: Marek Vasut <marex@nabladev.com> > --- > Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> > Cc: Bartosz Golaszewski <brgl@kernel.org> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> > Cc: Linus Walleij <linusw@kernel.org> > Cc: Rob Herring <robh@kernel.org> > Cc: devicetree@vger.kernel.org > Cc: kernel@dh-electronics.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-gpio@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-stm32@st-md-mailman.stormreply.com > --- > Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml > index 4f955f855e1ab..4631388a7d914 100644 > --- a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml > +++ b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml > @@ -22,6 +22,9 @@ properties: > - items: > - const: diodes,pi4ioe5v6534q > - const: nxp,pcal6534 > + - items: > + - const: kinetic,kts1622 > + - const: ti,tcal6416 > - items: > - enum: > - exar,xra1202 > -- > 2.53.0 > > I applied this. I would have sent a b4 notification but got this instead: $ b4 ty -all Auto-thankanating commits in gpio/for-next Found 9 of your commits since 1.week Calculating patch hashes, may take a moment... Located: [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC --- Generating 1 thank-you letters Writing: ./marex_nabladev_com_patch_00_10_arm64_dts_st_add_support_for_dh_electronics_stm32mp23xx_stm32mp25xx_dhcos_som_and_breakout_board_and_dhsbc.thanks Traceback (most recent call last): File "/usr/bin/b4", line 8, in <module> sys.exit(cmd()) ~~~^^ File "/usr/lib/python3/dist-packages/b4/command.py", line 417, in cmd cmdargs.func(cmdargs) ~~~~~~~~~~~~^^^^^^^^^ File "/usr/lib/python3/dist-packages/b4/command.py", line 113, in cmd_ty b4.ty.main(cmdargs) ~~~~~~~~~~^^^^^^^^^ File "/usr/lib/python3/dist-packages/b4/ty.py", line 681, in main auto_thankanator(cmdargs) ~~~~~~~~~~~~~~~~^^^^^^^^^ File "/usr/lib/python3/dist-packages/b4/ty.py", line 386, in auto_thankanator send_messages(applied, wantbranch, cmdargs) ~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ File "/usr/lib/python3/dist-packages/b4/ty.py", line 452, in send_messages with open(outfile, 'wb') as fh: ~~~~^^^^^^^^^^^^^^^ OSError: [Errno 36] File name too long: './marex_nabladev_com_patch_00_10_arm64_dts_st_add_support_for_dh_electronics_stm32mp23xx_stm32mp25xx_dhcos_som_and_breakout_board_and_dhsbc.thanks' Bart ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 02/10] dt-bindings: gpio: pca95xx: Document Kinetic KTS1622 2026-07-13 8:36 ` Bartosz Golaszewski @ 2026-07-13 10:33 ` Marek Vasut 0 siblings, 0 replies; 19+ messages in thread From: Marek Vasut @ 2026-07-13 10:33 UTC (permalink / raw) To: Bartosz Golaszewski Cc: Alexandre Torgue, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32, linux-arm-kernel On 7/13/26 10:36 AM, Bartosz Golaszewski wrote: > On Sat, 11 Jul 2026 22:59:31 +0200, Marek Vasut <marex@nabladev.com> said: >> The Kinetic Technologies KTS1622 is a 16-bit general-purpose I/O >> expander via the I2C bus for microcontrollers when additional I/Os >> are needed while keeping interconnections to the minimum. Datasheet >> comparison suggests that it is compatible with TCAL6416, add the >> compatible string and TCAL6416 as a fallback compatible. >> >> Signed-off-by: Marek Vasut <marex@nabladev.com> >> --- >> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> >> Cc: Bartosz Golaszewski <brgl@kernel.org> >> Cc: Conor Dooley <conor+dt@kernel.org> >> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> >> Cc: Linus Walleij <linusw@kernel.org> >> Cc: Rob Herring <robh@kernel.org> >> Cc: devicetree@vger.kernel.org >> Cc: kernel@dh-electronics.com >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-gpio@vger.kernel.org >> Cc: linux-kernel@vger.kernel.org >> Cc: linux-stm32@st-md-mailman.stormreply.com >> --- >> Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml >> index 4f955f855e1ab..4631388a7d914 100644 >> --- a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml >> +++ b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml >> @@ -22,6 +22,9 @@ properties: >> - items: >> - const: diodes,pi4ioe5v6534q >> - const: nxp,pcal6534 >> + - items: >> + - const: kinetic,kts1622 >> + - const: ti,tcal6416 >> - items: >> - enum: >> - exar,xra1202 >> -- >> 2.53.0 >> >> > > I applied this. I would have sent a b4 notification but got this instead: > > $ b4 ty -all > Auto-thankanating commits in gpio/for-next > Found 9 of your commits since 1.week > Calculating patch hashes, may take a moment... > Located: [PATCH 00/10] arm64: dts: st: Add support for DH > electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and > DHSBC > --- > Generating 1 thank-you letters > Writing: ./marex_nabladev_com_patch_00_10_arm64_dts_st_add_support_for_dh_electronics_stm32mp23xx_stm32mp25xx_dhcos_som_and_breakout_board_and_dhsbc.thanks > Traceback (most recent call last): > File "/usr/bin/b4", line 8, in <module> > sys.exit(cmd()) > ~~~^^ > File "/usr/lib/python3/dist-packages/b4/command.py", line 417, in cmd > cmdargs.func(cmdargs) > ~~~~~~~~~~~~^^^^^^^^^ > File "/usr/lib/python3/dist-packages/b4/command.py", line 113, in cmd_ty > b4.ty.main(cmdargs) > ~~~~~~~~~~^^^^^^^^^ > File "/usr/lib/python3/dist-packages/b4/ty.py", line 681, in main > auto_thankanator(cmdargs) > ~~~~~~~~~~~~~~~~^^^^^^^^^ > File "/usr/lib/python3/dist-packages/b4/ty.py", line 386, in auto_thankanator > send_messages(applied, wantbranch, cmdargs) > ~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > File "/usr/lib/python3/dist-packages/b4/ty.py", line 452, in send_messages > with open(outfile, 'wb') as fh: > ~~~~^^^^^^^^^^^^^^^ > OSError: [Errno 36] File name too long: > './marex_nabladev_com_patch_00_10_arm64_dts_st_add_support_for_dh_electronics_stm32mp23xx_stm32mp25xx_dhcos_som_and_breakout_board_and_dhsbc.thanks' B4 bug ? ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 03/10] arm64: dts: st: Fix SDMMC1 indent on stm32mp231 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut 2026-07-11 20:59 ` [PATCH 01/10] dt-bindings: arm: stm32: Document " Marek Vasut 2026-07-11 20:59 ` [PATCH 02/10] dt-bindings: gpio: pca95xx: Document Kinetic KTS1622 Marek Vasut @ 2026-07-11 20:59 ` Marek Vasut 2026-07-11 20:59 ` [PATCH 04/10] arm64: dts: st: Fix SDMMC1 indent on stm32mp251 Marek Vasut ` (6 subsequent siblings) 9 siblings, 0 replies; 19+ messages in thread From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw) To: linux-arm-kernel Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 Drop bogus space. No functional change. Signed-off-by: Marek Vasut <marex@nabladev.com> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Bartosz Golaszewski <brgl@kernel.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Linus Walleij <linusw@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 9e1d240888ff2..a9de9fc5eb411 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -720,7 +720,7 @@ sdmmc1: mmc@48220000 { reg = <0x48220000 0x400>, <0x44230400 0x8>; arm,primecell-periphid = <0x00353180>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CK_KER_SDMMC1 >; + clocks = <&rcc CK_KER_SDMMC1>; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; cap-sd-highspeed; -- 2.53.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 04/10] arm64: dts: st: Fix SDMMC1 indent on stm32mp251 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut ` (2 preceding siblings ...) 2026-07-11 20:59 ` [PATCH 03/10] arm64: dts: st: Fix SDMMC1 indent on stm32mp231 Marek Vasut @ 2026-07-11 20:59 ` Marek Vasut 2026-07-11 20:59 ` [PATCH 05/10] arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp231 Marek Vasut ` (5 subsequent siblings) 9 siblings, 0 replies; 19+ messages in thread From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw) To: linux-arm-kernel Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 Drop bogus space. No functional change. Signed-off-by: Marek Vasut <marex@nabladev.com> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Bartosz Golaszewski <brgl@kernel.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Linus Walleij <linusw@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 9c63fdb5a885a..66f3f83b8731f 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1657,7 +1657,7 @@ sdmmc1: mmc@48220000 { arm,primecell-periphid = <0x00353180>; reg = <0x48220000 0x400>, <0x44230400 0x8>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CK_KER_SDMMC1 >; + clocks = <&rcc CK_KER_SDMMC1>; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; cap-sd-highspeed; -- 2.53.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 05/10] arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp231 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut ` (3 preceding siblings ...) 2026-07-11 20:59 ` [PATCH 04/10] arm64: dts: st: Fix SDMMC1 indent on stm32mp251 Marek Vasut @ 2026-07-11 20:59 ` Marek Vasut 2026-07-11 20:59 ` [PATCH 06/10] arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp251 Marek Vasut ` (4 subsequent siblings) 9 siblings, 0 replies; 19+ messages in thread From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw) To: linux-arm-kernel Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 Add DT nodes for the remaining SDMMC controllers 2 and 3. Signed-off-by: Marek Vasut <marex@nabladev.com> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Bartosz Golaszewski <brgl@kernel.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Linus Walleij <linusw@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index a9de9fc5eb411..d70812f094142 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -730,6 +730,36 @@ sdmmc1: mmc@48220000 { status = "disabled"; }; + sdmmc2: mmc@48230000 { + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00353180>; + reg = <0x48230000 0x400>, <0x44230800 0x8>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SDMMC2>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <166000000>; + access-controllers = <&rifsc 77>; + status = "disabled"; + }; + + sdmmc3: mmc@48240000 { + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00353180>; + reg = <0x48240000 0x400>, <0x44230c00 0x8>; + interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SDMMC3>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC3_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <166000000>; + access-controllers = <&rifsc 78>; + status = "disabled"; + }; + ethernet1: ethernet@482c0000 { compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg = <0x482c0000 0x4000>; -- 2.53.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 06/10] arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp251 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut ` (4 preceding siblings ...) 2026-07-11 20:59 ` [PATCH 05/10] arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp231 Marek Vasut @ 2026-07-11 20:59 ` Marek Vasut 2026-07-11 20:59 ` [PATCH 07/10] arm64: dts: st: Add OMM node on stm32mp231 Marek Vasut ` (3 subsequent siblings) 9 siblings, 0 replies; 19+ messages in thread From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw) To: linux-arm-kernel Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 Add DT nodes for the remaining SDMMC controllers 2 and 3. Signed-off-by: Marek Vasut <marex@nabladev.com> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Bartosz Golaszewski <brgl@kernel.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Linus Walleij <linusw@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 66f3f83b8731f..6e985f115b195 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1667,6 +1667,36 @@ sdmmc1: mmc@48220000 { status = "disabled"; }; + sdmmc2: mmc@48230000 { + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00353180>; + reg = <0x48230000 0x400>, <0x44230800 0x8>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SDMMC2>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <166000000>; + access-controllers = <&rifsc 77>; + status = "disabled"; + }; + + sdmmc3: mmc@48240000 { + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00353180>; + reg = <0x48240000 0x400>, <0x44230c00 0x8>; + interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_SDMMC3>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC3_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <166000000>; + access-controllers = <&rifsc 78>; + status = "disabled"; + }; + ethernet1: ethernet@482c0000 { compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg = <0x482c0000 0x4000>; -- 2.53.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 07/10] arm64: dts: st: Add OMM node on stm32mp231 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut ` (5 preceding siblings ...) 2026-07-11 20:59 ` [PATCH 06/10] arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp251 Marek Vasut @ 2026-07-11 20:59 ` Marek Vasut 2026-07-11 20:59 ` [PATCH 08/10] arm64: dts: st: Add pinmux nodes for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board Marek Vasut ` (2 subsequent siblings) 9 siblings, 0 replies; 19+ messages in thread From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw) To: linux-arm-kernel Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 Add Octo Memory Manager (OMM) entry on stm32mp231 and its two OSPI instance. Signed-off-by: Marek Vasut <marex@nabladev.com> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Bartosz Golaszewski <brgl@kernel.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Linus Walleij <linusw@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 54 ++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index d70812f094142..4505fc0e3b537 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -222,6 +222,60 @@ hpdma3: dma-controller@40420000 { #dma-cells = <3>; }; + ommanager: ommanager@40500000 { + compatible = "st,stm32mp25-omm"; + reg = <0x40500000 0x400>, <0x60000000 0x10000000>; + reg-names = "regs", "memory_map"; + ranges = <0 0 0x40430000 0x400>, + <1 0 0x40440000 0x400>; + clocks = <&rcc CK_BUS_OSPIIOM>, + <&scmi_clk CK_SCMI_OSPI1>, + <&scmi_clk CK_SCMI_OSPI2>; + clock-names = "omm", "ospi1", "ospi2"; + resets = <&rcc OSPIIOM_R>, + <&scmi_reset RST_SCMI_OSPI1>, + <&scmi_reset RST_SCMI_OSPI2>; + reset-names = "omm", "ospi1", "ospi2"; + access-controllers = <&rifsc 111>; + power-domains = <&cluster_pd>; + #address-cells = <2>; + #size-cells = <1>; + st,syscfg-amcr = <&syscfg 0x2c00 0x7>; + status = "disabled"; + + ospi1: spi@0 { + compatible = "st,stm32mp25-ospi"; + reg = <0 0 0x400>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&hpdma 2 0x62 0x3121>, + <&hpdma 2 0x42 0x3112>; + dma-names = "tx", "rx"; + clocks = <&scmi_clk CK_SCMI_OSPI1>; + resets = <&scmi_reset RST_SCMI_OSPI1>, + <&scmi_reset RST_SCMI_OSPI1DLL>; + access-controllers = <&rifsc 74>; + power-domains = <&cluster_pd>; + st,syscfg-dlyb = <&syscfg 0x1000>; + status = "disabled"; + }; + + ospi2: spi@1 { + compatible = "st,stm32mp25-ospi"; + reg = <1 0 0x400>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&hpdma 3 0x62 0x3121>, + <&hpdma 3 0x42 0x3112>; + dma-names = "tx", "rx"; + clocks = <&scmi_clk CK_SCMI_OSPI2>; + resets = <&scmi_reset RST_SCMI_OSPI2>, + <&scmi_reset RST_SCMI_OSPI2DLL>; + access-controllers = <&rifsc 75>; + power-domains = <&cluster_pd>; + st,syscfg-dlyb = <&syscfg 0x1400>; + status = "disabled"; + }; + }; + rifsc: bus@42080000 { compatible = "st,stm32mp25-rifsc", "simple-bus"; reg = <0x42080000 0x1000>; -- 2.53.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 08/10] arm64: dts: st: Add pinmux nodes for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut ` (6 preceding siblings ...) 2026-07-11 20:59 ` [PATCH 07/10] arm64: dts: st: Add OMM node on stm32mp231 Marek Vasut @ 2026-07-11 20:59 ` Marek Vasut 2026-07-11 20:59 ` [PATCH 09/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut 2026-07-11 20:59 ` [PATCH 10/10] MAINTAINERS: Add DH electronics DHCOS SoM entry and fix email address Marek Vasut 9 siblings, 0 replies; 19+ messages in thread From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw) To: linux-arm-kernel Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 Add new pinmux nodes for DH electronics STM32MP2 DHCOS SoM and BB board. The following pinmux nodes are added: - ETH2 pins - I2C8 pins - MCO1 pins - SDMMC1,2,3 pins - SPI1,8 pins - UART8,9 pins - USART1,2,6 pins Signed-off-by: Marek Vasut <marex@nabladev.com> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Bartosz Golaszewski <brgl@kernel.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Linus Walleij <linusw@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 564 ++++++++++++++++++ 1 file changed, 564 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 456ece7f8ebc3..1aadbc6b47da9 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -182,6 +182,30 @@ pins5 { }; }; + /omit-if-no-ref/ + eth2_mdio_pins_a: eth2-mdio-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 4, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 5, AF10)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + eth2_mdio_sleep_pins_a: eth2-mdio-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 5, ANALOG)>; /* ETH_MDIO */ + }; + }; + /omit-if-no-ref/ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { pins { @@ -203,6 +227,68 @@ pins { }; }; + /omit-if-no-ref/ + eth2_rgmii_pins_b: eth2-rgmii-1 { + pins1 { + pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 8, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 9, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('C', 10, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('C', 4, AF10)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('F', 7, AF10)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = <STM32_PINMUX('G', 0, AF10)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 12, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('F', 9, AF10)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins4 { + pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + eth2_rgmii_sleep_pins_b: eth2-rgmii-sleep-1 { + pins { + pinmux = <STM32_PINMUX('C', 7, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 8, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('F', 8, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 0, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('F', 9, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('C', 3, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('F', 6, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + + /omit-if-no-ref/ + mco1_pins_a: mco1-0 { + pins { + pinmux = <STM32_PINMUX('I', 6, AF1)>; /* MCO1 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { @@ -394,6 +480,26 @@ pins2 { }; }; + /omit-if-no-ref/ + sdmmc1_b4_pins_b: sdmmc1-b4-1 { + pins1 { + pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */ + <STM32_PINMUX('E', 5, AF10)>, /* SDMMC1_D1 */ + <STM32_PINMUX('E', 0, AF10)>, /* SDMMC1_D2 */ + <STM32_PINMUX('E', 1, AF10)>, /* SDMMC1_D3 */ + <STM32_PINMUX('E', 2, AF10)>; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + /omit-if-no-ref/ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { pins1 { @@ -419,6 +525,31 @@ pins3 { }; }; + /omit-if-no-ref/ + sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 { + pins1 { + pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */ + <STM32_PINMUX('E', 5, AF10)>, /* SDMMC1_D1 */ + <STM32_PINMUX('E', 0, AF10)>, /* SDMMC1_D2 */ + <STM32_PINMUX('E', 1, AF10)>; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = <STM32_PINMUX('E', 2, AF10)>; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + /omit-if-no-ref/ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { @@ -431,6 +562,187 @@ pins { }; }; + /omit-if-no-ref/ + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 13, AF12)>, /* SDMMC2_D0 */ + <STM32_PINMUX('E', 11, AF12)>, /* SDMMC2_D1 */ + <STM32_PINMUX('E', 8, AF12)>, /* SDMMC2_D2 */ + <STM32_PINMUX('E', 12, AF12)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 15, AF12)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 14, AF12)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 13, AF12)>, /* SDMMC2_D0 */ + <STM32_PINMUX('E', 11, AF12)>, /* SDMMC2_D1 */ + <STM32_PINMUX('E', 8, AF12)>, /* SDMMC2_D2 */ + <STM32_PINMUX('E', 12, AF12)>; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 14, AF12)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = <STM32_PINMUX('E', 15, AF12)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 13, ANALOG)>, /* SDMMC2_D0 */ + <STM32_PINMUX('E', 11, ANALOG)>, /* SDMMC2_D1 */ + <STM32_PINMUX('E', 8, ANALOG)>, /* SDMMC2_D2 */ + <STM32_PINMUX('E', 12, ANALOG)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC2_CK */ + <STM32_PINMUX('E', 15, ANALOG)>; /* SDMMC2_CMD */ + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux = <STM32_PINMUX('E', 10, AF12)>, /* SDMMC2_D4 */ + <STM32_PINMUX('E', 9, AF12)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 6, AF12)>, /* SDMMC2_D6 */ + <STM32_PINMUX('E', 7, AF12)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 10, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('E', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('E', 7, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_pins_a: sdmmc3-b4-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 13, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('B', 12, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('I', 11, AF10)>, /* SDMMC3_D3 */ + <STM32_PINMUX('D', 12, AF10)>; /* SDMMC3_CMD */ + slew-rate = <0>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 13, AF10)>; /* SDMMC3_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_pins_b: sdmmc3-b4-1 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 13, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('B', 12, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 14, AF12)>, /* SDMMC3_D3 */ + <STM32_PINMUX('D', 12, AF10)>; /* SDMMC3_CMD */ + slew-rate = <0>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 13, AF10)>; /* SDMMC3_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 13, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('B', 12, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 14, AF10)>; /* SDMMC3_D3 */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 13, AF10)>; /* SDMMC3_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = <STM32_PINMUX('D', 12, AF10)>; /* SDMMC3_CMD */ + slew-rate = <2>; + drive-open-drain; + bias-disable; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 13, ANALOG)>, /* SDMMC3_D1 */ + <STM32_PINMUX('B', 12, ANALOG)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 14, ANALOG)>, /* SDMMC3_D3 */ + <STM32_PINMUX('B', 13, ANALOG)>, /* SDMMC3_CK */ + <STM32_PINMUX('D', 12, ANALOG)>; /* SDMMC3_CMD */ + }; + }; + + /omit-if-no-ref/ + spi1_pins_a: spi1-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 6, AF3)>, /* SPI1_SCK */ + <STM32_PINMUX('H', 7, AF2)>; /* SPI1_MOSI */ + drive-push-pull; + bias-disable; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 8, AF2)>; /* SPI1_MISO */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + spi1_sleep_pins_a: spi1-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 6, ANALOG)>, /* SPI1_SCK */ + <STM32_PINMUX('H', 7, ANALOG)>, /* SPI1_MOSI */ + <STM32_PINMUX('H', 8, ANALOG)>; /* SPI1_MISO */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { @@ -471,6 +783,50 @@ pins { }; }; + /omit-if-no-ref/ + usart1_pins_a: usart1-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 3, AF6)>, /* USART1_TX */ + <STM32_PINMUX('A', 1, AF5)>; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 2, AF6)>, /* USART1_RX */ + <STM32_PINMUX('A', 7, AF6)>; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 3, ANALOG)>, /* USART1_TX */ + <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('A', 1, AF5)>; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('A', 2, AF6)>; /* USART1_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 3, ANALOG)>, /* USART1_TX */ + <STM32_PINMUX('A', 1, ANALOG)>, /* USART1_RTS */ + <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */ + <STM32_PINMUX('A', 2, ANALOG)>; /* USART1_RX */ + }; + }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { @@ -504,6 +860,50 @@ pins { }; }; + /omit-if-no-ref/ + usart2_pins_b: usart2-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, AF6)>, /* USART2_TX */ + <STM32_PINMUX('A', 5, AF6)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF8)>, /* USART2_RX */ + <STM32_PINMUX('A', 9, AF6)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart2_idle_pins_b: usart2-idle-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 9, ANALOG)>; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('A', 5, AF6)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 5, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('A', 9, ANALOG)>, /* USART2_CTS_NSS */ + <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */ + }; + }; + /omit-if-no-ref/ usart6_pins_a: usart6-0 { pins1 { @@ -547,6 +947,127 @@ pins { <STM32_PINMUX('F', 14, ANALOG)>; /* USART6_RX */ }; }; + + /omit-if-no-ref/ + usart6_pins_b: usart6-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, AF6)>; /* USART6_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF6)>; /* USART6_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart6_idle_pins_b: usart6-idle-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, ANALOG)>; /* USART6_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF6)>; /* USART6_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart6_sleep_pins_b: usart6-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART6_TX */ + <STM32_PINMUX('F', 4, ANALOG)>; /* USART6_RX */ + }; + }; + + /omit-if-no-ref/ + uart8_pins_a: uart8-0 { + pins1 { + pinmux = <STM32_PINMUX('I', 11, AF5)>, /* UART8_TX */ + <STM32_PINMUX('B', 15, AF3)>; /* UART8_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 11, AF6)>, /* UART8_RX */ + <STM32_PINMUX('H', 5, AF6)>; /* UART8_CTS_NSS */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + uart8_idle_pins_a: uart8-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('I', 11, ANALOG)>, /* UART8_TX */ + <STM32_PINMUX('H', 5, ANALOG)>; /* UART8_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 15, AF3)>; /* UART8_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 11, AF6)>; /* UART8_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + uart8_sleep_pins_a: uart8-sleep-0 { + pins { + pinmux = <STM32_PINMUX('I', 11, ANALOG)>, /* UART8_TX */ + <STM32_PINMUX('B', 15, ANALOG)>, /* UART8_RTS */ + <STM32_PINMUX('H', 5, ANALOG)>, /* UART8_CTS_NSS */ + <STM32_PINMUX('F', 11, ANALOG)>; /* UART8_RX */ + }; + }; + + /omit-if-no-ref/ + uart9_pins_a: uart9-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 8, AF6)>, /* UART9_TX */ + <STM32_PINMUX('F', 12, AF6)>; /* UART9_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('I', 5, AF6)>, /* UART9_RX */ + <STM32_PINMUX('G', 7, AF6)>; /* UART9_CTS_NSS */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + uart9_idle_pins_a: uart9-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 8, ANALOG)>, /* UART9_TX */ + <STM32_PINMUX('G', 7, ANALOG)>; /* UART9_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('F', 12, AF6)>; /* UART9_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('I', 5, AF6)>; /* UART9_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + uart9_sleep_pins_a: uart9-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 8, ANALOG)>, /* UART9_TX */ + <STM32_PINMUX('F', 12, ANALOG)>, /* UART9_RTS */ + <STM32_PINMUX('G', 7, ANALOG)>, /* UART9_CTS_NSS */ + <STM32_PINMUX('I', 5, ANALOG)>; /* UART9_RX */ + }; + }; }; &pinctrl_z { @@ -569,6 +1090,25 @@ pins { }; }; + /omit-if-no-ref/ + i2c8_pins_b: i2c8-1 { + pins { + pinmux = <STM32_PINMUX('Z', 4, AF8)>, /* I2C1_SCL */ + <STM32_PINMUX('Z', 9, AF8)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c8_sleep_pins_b: i2c8-sleep-1 { + pins { + pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('Z', 9, ANALOG)>; /* I2C1_SDA */ + }; + }; + /omit-if-no-ref/ spi8_pins_a: spi8-0 { pins1 { @@ -592,4 +1132,28 @@ pins1 { <STM32_PINMUX('Z', 1, ANALOG)>; /* SPI8_MISO */ }; }; + + /omit-if-no-ref/ + spi8_pins_b: spi8-1 { + pins1 { + pinmux = <STM32_PINMUX('Z', 5, AF3)>, /* SPI8_SCK */ + <STM32_PINMUX('Z', 7, AF3)>; /* SPI8_MOSI */ + drive-push-pull; + bias-disable; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('Z', 8, AF3)>; /* SPI8_MISO */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + spi8_sleep_pins_b: spi8-sleep-1 { + pins1 { + pinmux = <STM32_PINMUX('Z', 5, ANALOG)>, /* SPI8_SCK */ + <STM32_PINMUX('Z', 7, ANALOG)>, /* SPI8_MOSI */ + <STM32_PINMUX('Z', 8, ANALOG)>; /* SPI8_MISO */ + }; + }; }; -- 2.53.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 09/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut ` (7 preceding siblings ...) 2026-07-11 20:59 ` [PATCH 08/10] arm64: dts: st: Add pinmux nodes for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board Marek Vasut @ 2026-07-11 20:59 ` Marek Vasut 2026-07-11 20:59 ` [PATCH 10/10] MAINTAINERS: Add DH electronics DHCOS SoM entry and fix email address Marek Vasut 9 siblings, 0 replies; 19+ messages in thread From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw) To: linux-arm-kernel Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 This stm32mp25xx-dhcos-bb board is a stack of DHCOS SoM based on STM32MP25xx SoC (1200MHz / crypto capabilities) populated on SoM Breakout Board, the stm32mp255c-dhcos-dhsbc is the SoM populated on DHSBC carrier board. The stm32mp23xx-dhcos-bb is a stack with STM32MP23xx SoC. The SoM contains the following peripherals: - STPMIC (power delivery) - 4GiB LPDDR4 memory - eMMC and SDIO WiFi module The Breakout Board carrier board contains the following peripherals: - USB-C peripheral port, power supply plug The DHSBC carrier board contains the following peripherals: - Two RGMII Ethernet ports - MicroSD slot - LVDS connector - MIPI CSI2 connector - USB-A Host port, USB-C power supply plug - USB-C / DP port - Expansion connector Signed-off-by: Marek Vasut <marex@nabladev.com> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Bartosz Golaszewski <brgl@kernel.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Linus Walleij <linusw@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- arch/arm64/boot/dts/st/Makefile | 10 + arch/arm64/boot/dts/st/stm32mp23xc.dtsi | 7 + .../boot/dts/st/stm32mp23xx-dhcos-bb.dts | 15 + .../boot/dts/st/stm32mp23xx-dhcos-som.dtsi | 51 ++ ...mp255c-dhcos-dhsbc-overlay-imx219-x10.dtso | 111 +++++ .../boot/dts/st/stm32mp255c-dhcos-dhsbc.dts | 189 ++++++++ arch/arm64/boot/dts/st/stm32mp25xc.dtsi | 7 + .../boot/dts/st/stm32mp25xx-dhcos-bb.dts | 15 + .../boot/dts/st/stm32mp25xx-dhcos-som.dtsi | 51 ++ .../boot/dts/st/stm32mp2xxx-dhcos-som.dtsi | 442 ++++++++++++++++++ 10 files changed, 898 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp23xc.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp23xx-dhcos-bb.dts create mode 100644 arch/arm64/boot/dts/st/stm32mp23xx-dhcos-som.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp255c-dhcos-dhsbc-overlay-imx219-x10.dtso create mode 100644 arch/arm64/boot/dts/st/stm32mp255c-dhcos-dhsbc.dts create mode 100644 arch/arm64/boot/dts/st/stm32mp25xc.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp25xx-dhcos-bb.dts create mode 100644 arch/arm64/boot/dts/st/stm32mp25xx-dhcos-som.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp2xxx-dhcos-som.dtsi diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile index 63908113ae36b..8614554caedd3 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -1,6 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only + +stm32mp255c-dhcos-dhsbc-overlay-imx219-x10-dtbs := \ + stm32mp255c-dhcos-dhsbc.dtb \ + stm32mp255c-dhcos-dhsbc-overlay-imx219-x10.dtbo + dtb-$(CONFIG_ARCH_STM32) += \ stm32mp215f-dk.dtb \ stm32mp235f-dk.dtb \ + stm32mp23xx-dhcos-bb.dtb \ + stm32mp25xx-dhcos-bb.dtb \ + stm32mp255c-dhcos-dhsbc.dtb \ + stm32mp255c-dhcos-dhsbc-overlay-imx219-x10.dtb \ + stm32mp255c-dhcos-dhsbc-overlay-imx219-x10.dtbo \ stm32mp257f-dk.dtb \ stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi new file mode 100644 index 0000000000000..56872fb1deeb0 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2026 Marek Vasut <marex@nabladev.com> + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp23xx-dhcos-bb.dts b/arch/arm64/boot/dts/st/stm32mp23xx-dhcos-bb.dts new file mode 100644 index 0000000000000..125c76fe3e7be --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp23xx-dhcos-bb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2026 Marek Vasut <marex@nabladev.com> + */ + +/dts-v1/; + +#include "stm32mp235.dtsi" +#include "stm32mp23xc.dtsi" +#include "stm32mp23xx-dhcos-som.dtsi" + +/ { + model = "DH electronics STM32MP23xx DHCOS Breakout Board"; + compatible = "dh,stm32mp231a-dhcos-bb", "dh,stm32mp231a-dhcos-som", "st,stm32mp231"; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp23xx-dhcos-som.dtsi b/arch/arm64/boot/dts/st/stm32mp23xx-dhcos-som.dtsi new file mode 100644 index 0000000000000..ffdcceb2fa237 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp23xx-dhcos-som.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2025-2026 Marek Vasut <marex@nabladev.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" +#include "stm32mp2xxx-dhcos-som.dtsi" + +/ { + model = "DH electronics STM32MP23xx DHCOS SoM"; + compatible = "dh,stm32mp231a-dhcos-som", "st,stm32mp231"; + + aliases { + serial1 = &usart1; + serial2 = &usart2; + }; +}; + +&rv3032 { + interrupts-extended = <&gpiod 10 IRQ_TYPE_EDGE_FALLING>; +}; + +/* Bluetooth */ +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_a>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw55572-bt"; + brcm,requires-autobaud-mode; + max-speed = <3000000>; + shutdown-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_b>; + pinctrl-1 = <&usart2_sleep_pins_b>; + pinctrl-2 = <&usart2_idle_pins_b>; + uart-has-rtscts; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp255c-dhcos-dhsbc-overlay-imx219-x10.dtso b/arch/arm64/boot/dts/st/stm32mp255c-dhcos-dhsbc-overlay-imx219-x10.dtso new file mode 100644 index 0000000000000..fbec84eb7720f --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp255c-dhcos-dhsbc-overlay-imx219-x10.dtso @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2026 Marek Vasut <marex@nabladev.com> + * + * Set up pipeline for raw bayer capture: + * $ media-ctl -d platform:48030000.dcmipp -r + * $ media-ctl -d platform:48030000.dcmipp -l '"48020000.csi":1->"dcmipp_input":0[1]' + * $ media-ctl -d platform:48030000.dcmipp -l "'dcmipp_input':1->'dcmipp_dump_postproc':0[1]" + * $ media-ctl -d platform:48030000.dcmipp --set-v4l2 "'imx219 0-0010':0[fmt:SRGGB8_1X8/1920x1080]" + * $ media-ctl -d platform:48030000.dcmipp --set-v4l2 "'48020000.csi':1[fmt:SRGGB8_1X8/1920x1080]" + * $ media-ctl -d platform:48030000.dcmipp --set-v4l2 "'dcmipp_input':1[fmt:SRGGB8_1X8/1920x1080 field:none]" + * $ media-ctl -d platform:48030000.dcmipp --set-v4l2 "'dcmipp_dump_postproc':0[compose:(0,0)/1920x1080]" + * $ media-ctl -d platform:48030000.dcmipp --set-v4l2 "'dcmipp_dump_postproc':1[fmt:SRGGB8_1X8/1920x1080]" + * $ v4l2-ctl -d /dev/video0 --set-fmt-video=width=1920,height=1080,pixelformat=RGGB + * + * Capture frame using v4l2-ctl: + * $ v4l2-ctl -d /dev/video0 --stream-mmap --stream-count=1 --stream-to=/frame.raw + * + * Capture frame using gstreamer: + * $ gst-launch-1.0 v4l2src device=/dev/video0 num-buffers=1 ! \ + * video/x-bayer,width=1920,height=1080,format=rggb ! \ + * bayer2rgb ! jpegenc ! filesink location=/test.jpg + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +&{/} { + clk_cam_x10: clk-cam-j1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + /* Page 29 / CSI_IF_CN / J1 */ + reg_cam_x10: reg-cam-j1 { + compatible = "regulator-fixed"; + regulator-name = "cam-X10"; + enable-active-high; + gpios = <&ioexp 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&csi { + vdd-supply = <&scmi_vddcore>; + vdda18-supply = <&scmi_v1v8>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi_sink: endpoint { + remote-endpoint = <&imx219_x10_out>; + data-lanes = <1 2>; + bus-type = <4>; + }; + }; + port@1 { + reg = <1>; + + csi_source: endpoint { + remote-endpoint = <&dcmipp_0>; + }; + }; + }; +}; + +&dcmipp { + status = "okay"; + + port { + dcmipp_0: endpoint { + remote-endpoint = <&csi_source>; + bus-type = <4>; + }; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + cam@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_x10>; + + VANA-supply = <®_cam_x10>; + VDIG-supply = <®_cam_x10>; + VDDL-supply = <®_cam_x10>; + + orientation = <2>; + rotation = <0>; + + port { + imx219_x10_out: endpoint { + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + data-lanes = <1 2>; + remote-endpoint = <&csi_sink>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp255c-dhcos-dhsbc.dts b/arch/arm64/boot/dts/st/stm32mp255c-dhcos-dhsbc.dts new file mode 100644 index 0000000000000..1d750d2787d6f --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp255c-dhcos-dhsbc.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2025-2026 Marek Vasut <marex@nabladev.com> + */ + +/dts-v1/; + +#include "stm32mp255.dtsi" +#include "stm32mp25xc.dtsi" +#include "stm32mp25xx-dhcos-som.dtsi" + +/ { + model = "DH electronics STM32MP255C DHCOS DHSBC"; + compatible = "dh,stm32mp255c-dhcos-dhsbc", "dh,stm32mp255c-dhcos-som", "st,stm32mp255"; + + aliases { + ethernet0 = ðernet1; + ethernet1 = ðernet2; + }; +}; + +ðernet1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <ð1_mdio_pins_a ð1_rgmii_pins_a>; + pinctrl-1 = <ð1_mdio_sleep_pins_a ð1_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethphy1: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + interrupt-parent = <&gpioc>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + realtek,clkout-disable; + realtek,clkout-ssc-enable; + realtek,rxc-ssc-enable; + realtek,sysclk-ssc-enable; + reset-assert-us = <15000>; + reset-deassert-us = <55000>; + reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_WAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +ðernet2 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <ð2_mdio_pins_a ð2_rgmii_pins_b>; + pinctrl-1 = <ð2_mdio_sleep_pins_a ð2_rgmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethphy2: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + interrupt-parent = <&gpiog>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + realtek,clkout-disable; + realtek,clkout-ssc-enable; + realtek,rxc-ssc-enable; + realtek,sysclk-ssc-enable; + reset-assert-us = <15000>; + reset-deassert-us = <55000>; + reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +&gpioa { + gpio-line-names = "DHSBC_HW-CODE_0", "DHSBC_HW-CODE_1", "DHSBC_HW-CODE_2", "", + "DHCOS-E", "DHCOS-J", "", "", + "DHCOS-D", "", "", "", + "", "", "", ""; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns = <57>; + i2c-scl-falling-time-ns = <7>; + clock-frequency = <400000>; + status = "okay"; +}; + +&scmi_vddio1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-settling-time-up-us = <1000>; + regulator-settling-time-down-us = <100000>; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&ioexp 8 GPIO_ACTIVE_HIGH>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_v3v3>; + vqmmc-supply = <&scmi_vddio1>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_a>; + pinctrl-1 = <&spi1_sleep_pins_a>; + cs-gpios = <&gpioh 3 0>; + status = "okay"; + + st33htph: tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + interrupt-parent = <&gpioa>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioh 2 GPIO_ACTIVE_LOW>; + spi-max-frequency = <24000000>; + }; +}; + +&spi8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi8_pins_b>; + pinctrl-1 = <&spi8_sleep_pins_b>; + cs-gpios = <&gpioz 6 0>; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xc.dtsi b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi new file mode 100644 index 0000000000000..56872fb1deeb0 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2026 Marek Vasut <marex@nabladev.com> + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xx-dhcos-bb.dts b/arch/arm64/boot/dts/st/stm32mp25xx-dhcos-bb.dts new file mode 100644 index 0000000000000..cf66e8e48c99a --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xx-dhcos-bb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2025-2026 Marek Vasut <marex@nabladev.com> + */ + +/dts-v1/; + +#include "stm32mp255.dtsi" +#include "stm32mp25xc.dtsi" +#include "stm32mp25xx-dhcos-som.dtsi" + +/ { + model = "DH electronics STM32MP25xx DHCOS Breakout Board"; + compatible = "dh,stm32mp251a-dhcos-bb", "dh,stm32mp251a-dhcos-som", "st,stm32mp251"; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xx-dhcos-som.dtsi b/arch/arm64/boot/dts/st/stm32mp25xx-dhcos-som.dtsi new file mode 100644 index 0000000000000..23c25ea086445 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp25xx-dhcos-som.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2025-2026 Marek Vasut <marex@nabladev.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" +#include "stm32mp2xxx-dhcos-som.dtsi" + +/ { + model = "DH electronics STM32MP25xx DHCOS SoM"; + compatible = "dh,stm32mp251a-dhcos-som", "st,stm32mp251"; + + aliases { + serial1 = &uart8; + serial2 = &uart9; + }; +}; + +&rv3032 { + interrupts-extended = <&gpioi 10 IRQ_TYPE_EDGE_FALLING>; +}; + +/* Bluetooth */ +&uart8 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart8_pins_a>; + pinctrl-1 = <&uart8_sleep_pins_a>; + pinctrl-2 = <&uart8_idle_pins_a>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw55572-bt"; + brcm,requires-autobaud-mode; + max-speed = <3000000>; + shutdown-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart9 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart9_pins_a>; + pinctrl-1 = <&uart9_sleep_pins_a>; + pinctrl-2 = <&uart9_idle_pins_a>; + uart-has-rtscts; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp2xxx-dhcos-som.dtsi b/arch/arm64/boot/dts/st/stm32mp2xxx-dhcos-som.dtsi new file mode 100644 index 0000000000000..330c7c6768b6c --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp2xxx-dhcos-som.dtsi @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2025-2026 Marek Vasut <marex@nabladev.com> + */ + +/ { + aliases { + mmc0 = &sdmmc2; + mmc1 = &sdmmc3; + serial0 = &usart6; + serial1 = &uart8; + eeprom0 = &eeprom0; + eeprom0wl = &eeprom0wl; + rtc0 = &rv3032; + rtc1 = &rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Internal RAM reserved memory declaration */ + tfa_bl31: tfa-bl31@a000000 { + reg = <0x0 0xa000000 0x0 0x20000>; + no-map; + }; + + hpdma1_lli: hpdma1-lli@a020000 { + reg = <0x0 0xa020000 0x0 0xf0f0>; + no-map; + }; + + hpdma2_lli: hpdma2-lli@a02f0f0 { + reg = <0x0 0xa02f0f0 0x0 0xf0f0>; + no-map; + }; + + hpdma3_lli: hpdma3-lli@a03e1e0 { + reg = <0x0 0xa03e1e0 0x0 0x1e20>; + no-map; + }; + + bsec_mirror: bsec-mirror@a040000 { + reg = <0x0 0xa040000 0x0 0x1000>; + no-map; + }; + + scmi_cid2_s: scmi-cid2-s@a041000 { + reg = <0x0 0xa041000 0x0 0x1000>; + no-map; + }; + + scmi_cid2_ns: scmi-cid2-ns@a042000 { + reg = <0x0 0xa042000 0x0 0x1000>; + no-map; + }; + + cm33_sram1: cm33-sram1@a043000 { + reg = <0x0 0xa043000 0x0 0x1d000>; + no-map; + }; + + cm33_sram2: cm33-sram2@a060000 { + reg = <0x0 0xa060000 0x0 0x20000>; + no-map; + }; + + cm33_retram: cm33-retram@a080000 { + reg = <0x0 0xa080000 0x0 0x1f000>; + no-map; + }; + + ddr_param: ddr-param@a09f000 { + reg = <0x0 0xa09f000 0x0 0x1000>; + no-map; + }; + + cm0_cube_fw: cm0-cube-fw@200C0000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x200C0000 0x0 0x4000>; + no-map; + }; + + cm0_cube_data: cm0-cube-data@200C4000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x200C4000 0x0 0x2000>; + no-map; + }; + + ipc_shmem_2: ipc-shmem-2@200C6000{ + compatible = "shared-dma-pool"; + reg = <0x0 0x200C6000 0x0 0x2000>; + no-map; + }; + + /* Backup RAM reserved memory declaration */ + bl31_lowpower: bl31-lowpower@42000000 { + reg = <0x0 0x42000000 0x0 0x1000>; + no-map; + }; + + tfm_its: tfm-its@42001000 { + reg = <0x0 0x42001000 0x0 0x1000>; + no-map; + }; + + /* Octo Memory Manager reserved memory declaration */ + mm_ospi1: mm-ospi@60000000 { + reg = <0x0 0x60000000 0x0 0x10000000>; + no-map; + }; + + /* DDR reserved memory declaration */ + tfm_code: tfm-code@80000000 { + reg = <0x0 0x80000000 0x0 0x100000>; + no-map; + }; + + cm33_cube_fw: cm33-cube-fw@80100000 { + reg = <0x0 0x80100000 0x0 0x800000>; + no-map; + }; + + tfm_data: tfm-data@80900000 { + reg = <0x0 0x80900000 0x0 0x100000>; + no-map; + }; + + cm33_cube_data: cm33-cube-data@80a00000 { + reg = <0x0 0x80a00000 0x0 0x800000>; + no-map; + }; + + ipc_shmem_1: ipc-shmem-1@81200000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x81200000 0x0 0xf8000>; + no-map; + }; + + vdev0vring0: vdev0vring0@812f8000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x812f8000 0x0 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@812f9000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x812f9000 0x0 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@812fa000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x812fa000 0x0 0x6000>; + no-map; + }; + + spare1: spare1@81300000 { + reg = <0x0 0x81300000 0x0 0xcc0000>; + no-map; + }; + + bl31_context: bl31-context@81fc0000 { + reg = <0x0 0x81fc0000 0x0 0x40000>; + no-map; + }; + + op_tee: op-tee@82000000 { + reg = <0x0 0x82000000 0x0 0x2000000>; + no-map; + }; + + gpu_reserved: gpu-reserved@fa800000 { + reg = <0x0 0xfa800000 0x0 0x4000000>; + no-map; + }; + + ltdc_sec_layer: ltdc-sec-layer@fe800000 { + reg = <0x0 0xfe800000 0x0 0x800000>; + no-map; + }; + + ltdc_sec_rotation: ltdc-sec-rotation@ff000000 { + reg = <0x0 0xff000000 0x0 0x1000000>; + no-map; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x80000000>; + size = <0x0 0x8000000>; + alignment = <0x0 0x2000>; + linux,cma-default; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <50>; + reset-gpios = <&ioexp 3 GPIO_ACTIVE_LOW>; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&gpioa { + gpio-line-names = "", "DHCOS-M", "DHCOS-K", "DHCOS-L", + "DHCOS-E", "DHCOS-J", "", "", + "DHCOS-D", "", "", "", + "", "", "", ""; +}; + +&gpiof { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "DHCOS_RAM-CODE_2"; +}; + +&gpiog { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "DHCOS_RAM-CODE_0", "DHCOS_RAM-CODE_1", "", + "", "", "DHCOS-F", "DHCOS_HW-CODE_0"; +}; + +&gpioh { + gpio-line-names = "", "", "DHCOS-I", "DHCOS-N", + "", "", "DHCOS-O", "DHCOS-H", + "DHCOS-G", "", "", "", + "", "", "", ""; +}; + +&gpioi { + gpio-line-names = "DHCOS_HW-CODE_1", "DHCOS_HW-CODE_2", "", "", + "", "", "", "", + "", "DHCOS-C", "", "", + "", "", "", ""; +}; + +&gpioz { + gpio-line-names = "", "", "DHCOS-A", "DHCOS-B", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_pins_b>; + pinctrl-1 = <&i2c8_sleep_pins_b>; + i2c-scl-rising-time-ns = <57>; + i2c-scl-falling-time-ns = <7>; + clock-frequency = <400000>; + status = "okay"; + + ioexp: gpio@20 { + compatible = "kinetic,kts1622", "ti,tcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupts-extended = <&gpiod 11 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-source; + + gpio-line-names = + "#ETH1_RST_P0_0", "#ETH0_RST_P0_1", + "BT_REG_ON_P0_2", "WL_REG_ON_P0_3", + "USB1_PWR_EN_P0_4", "USB1_PWR_STAT_P0_5", + "USB0_PWR_EN_P0_6", "USB0_PWR_STAT_P0_7", + "SDIO0_CD_P1_0", "USB0_SS_SEL_P1_1", + "#PCIe_RST_1_2", "#PCIe_Wake_P1_3", + "#QSPI_RST_P1_4", "#CSI0_PWDN_P1_5", + "#CSI0_RST_P1_6", "#ETH3_RST_P1_7"; + }; + + eeprom0: eeprom@50 { + compatible = "atmel,24c256"; /* ST M24256 */ + reg = <0x50>; + pagesize = <64>; + }; + + rv3032: rtc@51 { + compatible = "microcrystal,rv3032"; + reg = <0x51>; + wakeup-source; + }; + + eeprom0wl: eeprom@58 { + compatible = "st,24256e-wl"; /* ST M24256E WL page of 0x50 */ + pagesize = <64>; + reg = <0x58>; + }; +}; + +&ommanager { + memory-region = <&mm_ospi1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ospi_port1_clk_pins_a + &ospi_port1_io03_pins_a + &ospi_port1_cs0_pins_a>; + pinctrl-1 = <&ospi_port1_clk_sleep_pins_a + &ospi_port1_io03_sleep_pins_a + &ospi_port1_cs0_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + +&ospi1 { + #address-cells = <1>; + #size-cells = <0>; + memory-region = <&mm_ospi1>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <100000000>; + }; +}; + +&rtc { + status = "okay"; +}; + +&scmi_regu { + scmi_vddcore: regulator@b { + reg = <VOLTD_SCMI_STPMIC2_BUCK2>; + regulator-name = "vddcore"; + }; + + regulator@c { + reg = <VOLTD_SCMI_STPMIC2_BUCK3>; + regulator-name = "vddgpu"; + regulator-always-on; + }; + + scmi_v1v8: regulator@e { + reg = <VOLTD_SCMI_STPMIC2_BUCK5>; + regulator-name = "v1v8"; + regulator-always-on; + }; + + scmi_v3v3: regulator@10 { + reg = <VOLTD_SCMI_STPMIC2_BUCK7>; + regulator-name = "v3v3"; + regulator-always-on; + }; + + scmi_vdd_emmc: regulator@12 { + reg = <VOLTD_SCMI_STPMIC2_LDO2>; + regulator-name = "vdd_emmc"; + }; + + scmi_vdd3v3_usb: regulator@14 { + reg = <VOLTD_SCMI_STPMIC2_LDO4>; + regulator-name = "vdd3v3_usb"; + }; + + scmi_vdd_sdcard: regulator@17 { + reg = <VOLTD_SCMI_STPMIC2_LDO7>; + regulator-name = "vdd_sdcard"; + }; +}; + +&scmi_vddio3 { + regulator-always-on; +}; + +&scmi_vddio4 { + regulator-always-on; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&scmi_vdd_emmc>; + vqmmc-supply = <&scmi_vddio2>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + no-sd; + no-mmc; + st,neg-edge; + vmmc-supply = <&scmi_v3v3>; + vqmmc-supply = <&scmi_v1v8>; + mmc-pwrseq = <&sdio_pwrseq>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { /* muRata 2FY */ + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usart6 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart6_pins_b>; + pinctrl-1 = <&usart6_idle_pins_b>; + pinctrl-2 = <&usart6_sleep_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; -- 2.53.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 10/10] MAINTAINERS: Add DH electronics DHCOS SoM entry and fix email address 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut ` (8 preceding siblings ...) 2026-07-11 20:59 ` [PATCH 09/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut @ 2026-07-11 20:59 ` Marek Vasut 2026-07-13 7:51 ` Krzysztof Kozlowski 9 siblings, 1 reply; 19+ messages in thread From: Marek Vasut @ 2026-07-11 20:59 UTC (permalink / raw) To: linux-arm-kernel Cc: Marek Vasut, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 Add another SoM type N: match and update email address to an up to date one in the process. Signed-off-by: Marek Vasut <marex@nabladev.com> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Bartosz Golaszewski <brgl@kernel.org> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Linus Walleij <linusw@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8729cea57c3dd..3532d425e41f1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7518,11 +7518,12 @@ F: drivers/iio/chemical/sen0322.c DH ELECTRONICS DHSOM SOM AND BOARD SUPPORT M: Christoph Niedermaier <cniedermaier@dh-electronics.com> -M: Marek Vasut <marex@denx.de> +M: Marek Vasut <marex@nabladev.com> L: kernel@dh-electronics.com S: Maintained N: dhcom N: dhcor +N: dhcos N: dhsom DIALOG SEMICONDUCTOR DRIVERS -- 2.53.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 10/10] MAINTAINERS: Add DH electronics DHCOS SoM entry and fix email address 2026-07-11 20:59 ` [PATCH 10/10] MAINTAINERS: Add DH electronics DHCOS SoM entry and fix email address Marek Vasut @ 2026-07-13 7:51 ` Krzysztof Kozlowski 2026-07-13 13:25 ` Marek Vasut 0 siblings, 1 reply; 19+ messages in thread From: Krzysztof Kozlowski @ 2026-07-13 7:51 UTC (permalink / raw) To: Marek Vasut Cc: linux-arm-kernel, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 On Sat, Jul 11, 2026 at 10:59:39PM +0200, Marek Vasut wrote: > Add another SoM type N: match and update email address to an > up to date one in the process. > > Signed-off-by: Marek Vasut <marex@nabladev.com> > --- > Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> > Cc: Bartosz Golaszewski <brgl@kernel.org> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> > Cc: Linus Walleij <linusw@kernel.org> > Cc: Rob Herring <robh@kernel.org> > Cc: devicetree@vger.kernel.org > Cc: kernel@dh-electronics.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-gpio@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-stm32@st-md-mailman.stormreply.com > --- > MAINTAINERS | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 8729cea57c3dd..3532d425e41f1 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -7518,11 +7518,12 @@ F: drivers/iio/chemical/sen0322.c > > DH ELECTRONICS DHSOM SOM AND BOARD SUPPORT > M: Christoph Niedermaier <cniedermaier@dh-electronics.com> > -M: Marek Vasut <marex@denx.de> > +M: Marek Vasut <marex@nabladev.com> > L: kernel@dh-electronics.com > S: Maintained Commit is fine, but, assuming old address stops working, please send a patch changing address in other MAINTAINERS entry + mailmap entry, and in all of dt-bindings (one patch for DT is enough) Best regards, Krzysztof ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 10/10] MAINTAINERS: Add DH electronics DHCOS SoM entry and fix email address 2026-07-13 7:51 ` Krzysztof Kozlowski @ 2026-07-13 13:25 ` Marek Vasut 2026-07-13 13:45 ` Krzysztof Kozlowski 0 siblings, 1 reply; 19+ messages in thread From: Marek Vasut @ 2026-07-13 13:25 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: linux-arm-kernel, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 On 7/13/26 9:51 AM, Krzysztof Kozlowski wrote: > On Sat, Jul 11, 2026 at 10:59:39PM +0200, Marek Vasut wrote: >> Add another SoM type N: match and update email address to an >> up to date one in the process. >> >> Signed-off-by: Marek Vasut <marex@nabladev.com> >> --- >> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> >> Cc: Bartosz Golaszewski <brgl@kernel.org> >> Cc: Conor Dooley <conor+dt@kernel.org> >> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> >> Cc: Linus Walleij <linusw@kernel.org> >> Cc: Rob Herring <robh@kernel.org> >> Cc: devicetree@vger.kernel.org >> Cc: kernel@dh-electronics.com >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-gpio@vger.kernel.org >> Cc: linux-kernel@vger.kernel.org >> Cc: linux-stm32@st-md-mailman.stormreply.com >> --- >> MAINTAINERS | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 8729cea57c3dd..3532d425e41f1 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -7518,11 +7518,12 @@ F: drivers/iio/chemical/sen0322.c >> >> DH ELECTRONICS DHSOM SOM AND BOARD SUPPORT >> M: Christoph Niedermaier <cniedermaier@dh-electronics.com> >> -M: Marek Vasut <marex@denx.de> >> +M: Marek Vasut <marex@nabladev.com> >> L: kernel@dh-electronics.com >> S: Maintained > > Commit is fine, but, assuming old address stops working, please send a > patch changing address in other MAINTAINERS entry + mailmap entry, and > in all of dt-bindings (one patch for DT is enough) There is one more DRM entry, I will fix that up in a separate patch. But since you brought this up -- what about the mail address used in copyright headers (comments) in various drivers, shall I simply remove it and be done with it (I think yes, but again, separate patchset) ? ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 10/10] MAINTAINERS: Add DH electronics DHCOS SoM entry and fix email address 2026-07-13 13:25 ` Marek Vasut @ 2026-07-13 13:45 ` Krzysztof Kozlowski 0 siblings, 0 replies; 19+ messages in thread From: Krzysztof Kozlowski @ 2026-07-13 13:45 UTC (permalink / raw) To: Marek Vasut Cc: linux-arm-kernel, Alexandre Torgue, Bartosz Golaszewski, Conor Dooley, Krzysztof Kozlowski, Linus Walleij, Rob Herring, devicetree, kernel, linux-gpio, linux-kernel, linux-stm32 On 13/07/2026 15:25, Marek Vasut wrote: > But since you brought this up -- what about the mail address used in > copyright headers (comments) in various drivers, shall I simply remove > it and be done with it (I think yes, but again, separate patchset) ? 1. In non-personal copyright headers: tricky to say, maybe using company email gave some attributions which now could be changed. I don't know... but I did update mine to @korg back in 2016 :) 2. In personal copyright headers, comments, MODULE_AUTHOR() etc: up to you, it's perfectly fine to update it so people can reach you with questions. Therefore some people update it, some people don't. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2026-07-13 23:27 UTC | newest] Thread overview: 19+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-07-11 20:59 [PATCH 00/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut 2026-07-11 20:59 ` [PATCH 01/10] dt-bindings: arm: stm32: Document " Marek Vasut 2026-07-13 7:48 ` Krzysztof Kozlowski 2026-07-13 10:31 ` Marek Vasut 2026-07-11 20:59 ` [PATCH 02/10] dt-bindings: gpio: pca95xx: Document Kinetic KTS1622 Marek Vasut 2026-07-13 7:49 ` Krzysztof Kozlowski 2026-07-13 8:36 ` Bartosz Golaszewski 2026-07-13 10:33 ` Marek Vasut 2026-07-11 20:59 ` [PATCH 03/10] arm64: dts: st: Fix SDMMC1 indent on stm32mp231 Marek Vasut 2026-07-11 20:59 ` [PATCH 04/10] arm64: dts: st: Fix SDMMC1 indent on stm32mp251 Marek Vasut 2026-07-11 20:59 ` [PATCH 05/10] arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp231 Marek Vasut 2026-07-11 20:59 ` [PATCH 06/10] arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp251 Marek Vasut 2026-07-11 20:59 ` [PATCH 07/10] arm64: dts: st: Add OMM node on stm32mp231 Marek Vasut 2026-07-11 20:59 ` [PATCH 08/10] arm64: dts: st: Add pinmux nodes for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board Marek Vasut 2026-07-11 20:59 ` [PATCH 09/10] arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC Marek Vasut 2026-07-11 20:59 ` [PATCH 10/10] MAINTAINERS: Add DH electronics DHCOS SoM entry and fix email address Marek Vasut 2026-07-13 7:51 ` Krzysztof Kozlowski 2026-07-13 13:25 ` Marek Vasut 2026-07-13 13:45 ` Krzysztof Kozlowski
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