[RFC PATCH 09/22] arm64: dts: ti: k3-j7200: Add DDR node for j7200

[RFC PATCH 09/22] arm64: dts: ti: k3-j7200: Add DDR node for j7200

[MANNURU VENKATESWARLU]

From: Gandhar Deshpande <g-deshpande@ti.com>

Add device tree node for the DDR controller on the j7200 device.
This defines the memory controller with its register regions, interrupts,
power domains, and clock requirements.

This enables proper DDR controller temperature monitoring.

Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 67fde5667b8d9..db519239129a0 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -1556,4 +1556,36 @@ main_esm: esm@700000 {
 		bootph-pre-ram;
 		ti,esm-pins = <656>, <657>;
 	};
+
+	memorycontroller: memorycontroller@2980000 {
+		compatible = "ti,j721e-ddrss";
+		reg = <0x0 0x02990000 0x0 0x4000>,
+		      <0x0 0x0114000 0x0 0x100>;
+		reg-names = "cfg", "ctrl_mmr_lp4";
+		power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>,
+				<&k3_pds 90 TI_SCI_PD_SHARED>;
+		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+		ti,ddr-freq1   = <0>;
+		ti,ddr-freq2   = <0>;
+		ti,ddr-fhs-cnt = <0>;
+		clocks = <&k3_clks 47 2>, <&k3_clks 30 9>;
+		bootph-pre-ram;
+
+		ddr: ddr@0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x72c>,
+			      <0x00 0x2000 0x00 0x4b0>,
+			      <0x00 0x4000 0x00 0x163c>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+			bootph-pre-ram;
+		};
+
+		ddr_pmu0: ddr-pmu@100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
-- 
2.34.1

[RFC PATCH 10/22] arm64: dts: ti: k3-j721e: Add DDR and controller node

[MANNURU VENKATESWARLU]

From: Neha Malcom Francis <n-francis@ti.com>

Add DDR Controller and LPDDR4 node for J721E device. This defines the
memory controller with its register regions, interrupts, power domains
and clock requirements.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index d5fd30a01032f..67f1bb700f9a9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -2928,4 +2928,36 @@ main_esm: esm@700000 {
 		bootph-pre-ram;
 		ti,esm-pins = <344>, <345>;
 	};
+
+	memorycontroller: memorycontroller@2980000 {
+		compatible = "ti,j721e-ddrss";
+		reg = <0x0 0x02990000 0x0 0x4000>,
+		      <0x0 0x0114000 0x0 0x100>;
+		reg-names = "cfg", "ctrl_mmr_lp4";
+		power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>,
+				<&k3_pds 90 TI_SCI_PD_SHARED>;
+		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+		ti,ddr-freq1   = <0>;
+		ti,ddr-freq2   = <0>;
+		ti,ddr-fhs-cnt = <0>;
+		clocks = <&k3_clks 47 2>, <&k3_clks 30 9>;
+		bootph-pre-ram;
+
+		ddr: ddr@0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x72c>,
+			      <0x00 0x2000 0x00 0x4b0>,
+			      <0x00 0x4000 0x00 0x163c>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+			bootph-pre-ram;
+		};
+
+		ddr_pmu0: ddr-pmu@100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
-- 
2.34.1

[RFC PATCH 11/22] arm64: dts: ti: k3-j721s2-main: Add DDR nodes for J721S2

[MANNURU VENKATESWARLU]

From: Neha Malcom Francis <n-francis@ti.com>

Add DT nodes for the 2 DDR controllers on the J721S2 device. These define
the memory controller with its register regions, interrupts, power
domains, and clock requirements.

This allows for DDR controller temperature monitoring.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 84 ++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 1228ac5711bf0..c8de5b74b97b6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -37,6 +37,89 @@ l3cache-sram@200000 {
 		};
 	};
 
+	msmc0: msmc {
+		compatible = "ti,j721s2-msmc", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		intrlv-gran = <0>;
+		intrlv-size = <0>;
+		ecc-enable  = <0>;
+		emif-config = <0>;
+		emif-active = <0>;
+		bootph-pre-ram;
+
+		memorycontroller0: memorycontroller@2980000 {
+			compatible = "ti,j721s2-ddrss";
+			reg = <0x0 0x02990000 0x0 0x4000>,
+			      <0x0 0x0114000 0x0 0x100>,
+			      <0x0 0x02980000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+			power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
+					<&k3_pds 96 TI_SCI_PD_SHARED>;
+			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+			ti,ddr-freq0   = <0>;
+			ti,ddr-freq1   = <0>;
+			ti,ddr-freq2   = <0>;
+			ti,ddr-fhs-cnt = <0>;
+			clocks = <&k3_clks 138 0>, <&k3_clks 43 2>;
+			instance = <0>;
+			bootph-pre-ram;
+
+			ddr0: ddr@0 {
+				compatible = "cdns,k3-ddr";
+				reg = <0x00 0x0000 0x00 0x72c>,
+				      <0x00 0x2000 0x00 0x4b0>,
+				      <0x00 0x4000 0x00 0x163c>;
+				reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+				bootph-pre-ram;
+			};
+
+			ddr_pmu0: ddr-pmu@100 {
+				compatible = "ti,k3-ddr-pmu";
+				reg = <0x00 0x100 0x00 0x14>;
+			};
+		};
+
+		memorycontroller1: memorycontroller@29a0000 {
+			compatible = "ti,j721s2-ddrss";
+			reg = <0x0 0x029b0000 0x0 0x4000>,
+			      <0x0 0x0114000 0x0 0x100>,
+			      <0x0 0x029a0000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+			power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>,
+					<&k3_pds 97 TI_SCI_PD_SHARED>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x0000 0x00 0x029b0000 0x00 0x4000>;
+			ti,ddr-freq0   = <0>;
+			ti,ddr-freq1   = <0>;
+			ti,ddr-freq2   = <0>;
+			ti,ddr-fhs-cnt = <0>;
+			clocks = <&k3_clks 139 0>, <&k3_clks 43 2>;
+			instance = <1>;
+			bootph-pre-ram;
+
+			ddr1: ddr@0 {
+				compatible = "cdns,k3-ddr";
+				reg = <0x00 0x0000 0x00 0x72c>,
+				      <0x00 0x2000 0x00 0x4b0>,
+				      <0x00 0x4000 0x00 0x163c>;
+				reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+				bootph-pre-ram;
+			};
+
+			ddr_pmu1: ddr-pmu@100 {
+				compatible = "ti,k3-ddr-pmu";
+				reg = <0x00 0x100 0x00 0x14>;
+			};
+		};
+	};
+
 	scm_conf: bus@104000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -2247,4 +2330,5 @@ mcasp4: mcasp@2b40000 {
 		power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>;
 		status = "disabled";
 	};
+
 };
-- 
2.34.1

[RFC PATCH 12/22] arm64: dts: ti: k3-j784s4-main: Add DDR nodes for J784S4

[MANNURU VENKATESWARLU]

From: Neha Malcom Francis <n-francis@ti.com>

Add DT nodes for the 4 DDR controllers on the J784S4 device. These define
the memory controller with its register regions, interrupts, power
domains, and clock requirements.

This allows for DDR controller temperature monitoring.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 .../dts/ti/k3-j784s4-j742s2-main-common.dtsi  | 83 +++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi    | 73 ++++++++++++++++
 2 files changed, 156 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index c2636e624f18b..65bd68de989f2 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -2712,4 +2712,87 @@ bist_main14: bist@33c0000 {
 		bootph-pre-ram;
 		ti,sci-dev-id = <234>;
 	};
+
+	msmc0: msmc {
+		compatible = "ti,j721s2-msmc", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		intrlv-gran = <0>;
+		intrlv-size = <0>;
+		ecc-enable  = <0>;
+		emif-config = <0>;
+		emif-active = <0>;
+		bootph-pre-ram;
+
+		memorycontroller0: memorycontroller@2980000 {
+			compatible = "ti,j721s2-ddrss";
+			reg = <0x0 0x02990000 0x0 0x4000>,
+			      <0x0 0x0114000 0x0 0x100>,
+			      <0x0 0x02980000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+			power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
+					<&k3_pds 131 TI_SCI_PD_SHARED>;
+			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+			ti,ddr-freq0   = <0>;
+			ti,ddr-freq1   = <0>;
+			ti,ddr-freq2   = <0>;
+			ti,ddr-fhs-cnt = <0>;
+			clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
+			instance = <0>;
+			bootph-pre-ram;
+
+			ddr0: ddr@0 {
+				compatible = "cdns,k3-ddr";
+				reg = <0x00 0x0000 0x00 0x72c>,
+				      <0x00 0x2000 0x00 0x4b0>,
+				      <0x00 0x4000 0x00 0x163c>;
+				reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+				bootph-pre-ram;
+			};
+
+			ddr_pmu0: ddr-pmu@100 {
+				compatible = "ti,k3-ddr-pmu";
+				reg = <0x00 0x100 0x00 0x14>;
+			};
+		};
+
+		memorycontroller1: memorycontroller@29a0000 {
+			compatible = "ti,j721s2-ddrss";
+			reg = <0x0 0x029b0000 0x0 0x4000>,
+			      <0x0 0x0114000 0x0 0x100>,
+			      <0x0 0x029a0000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+			power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
+					<&k3_pds 132 TI_SCI_PD_SHARED>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x0000 0x00 0x029b0000 0x00 0x4000>;
+			ti,ddr-freq0   = <0>;
+			ti,ddr-freq1   = <0>;
+			ti,ddr-freq2   = <0>;
+			ti,ddr-fhs-cnt = <0>;
+			clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
+			instance = <1>;
+			bootph-pre-ram;
+
+			ddr1: ddr@0 {
+				compatible = "cdns,k3-ddr";
+				reg = <0x00 0x0000 0x00 0x72c>,
+				      <0x00 0x2000 0x00 0x4b0>,
+				      <0x00 0x4000 0x00 0x163c>;
+				reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+				bootph-pre-ram;
+			};
+
+			ddr_pmu1: ddr-pmu@100 {
+				compatible = "ti,k3-ddr-pmu";
+				reg = <0x00 0x100 0x00 0x14>;
+			};
+		};
+	};
 };
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 78fcd0c40abcf..6c19bda71565f 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -149,6 +149,79 @@ c71_3: dsp@67800000 {
 		ti,sci-proc-ids = <0x33 0xff>;
 		status = "disabled";
 	};
+
+};
+
+&msmc0 {
+	memorycontroller2: memorycontroller@29c0000 {
+		compatible = "ti,j721s2-ddrss";
+		reg = <0x0 0x029d0000 0x0 0x4000>,
+		      <0x0 0x0114000 0x0 0x100>,
+		      <0x0 0x029c0000 0x0 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+		power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
+				<&k3_pds 133 TI_SCI_PD_SHARED>;
+		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x0000 0x00 0x029d0000 0x00 0x4000>;
+		ti,ddr-freq0   = <0>;
+		ti,ddr-freq1   = <0>;
+		ti,ddr-freq2   = <0>;
+		ti,ddr-fhs-cnt = <0>;
+		clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
+		instance = <2>;
+		bootph-pre-ram;
+
+		ddr2: ddr@0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x72c>,
+			      <0x00 0x2000 0x00 0x4b0>,
+			      <0x00 0x4000 0x00 0x163c>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+			bootph-pre-ram;
+		};
+
+		ddr_pmu2: ddr-pmu@100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
+
+	memorycontroller3: memorycontroller@29e0000 {
+		compatible = "ti,j721s2-ddrss";
+		reg = <0x0 0x029f0000 0x0 0x4000>,
+		      <0x0 0x0114000 0x0 0x100>,
+		      <0x0 0x029e0000 0x0 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+		power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
+				<&k3_pds 139 TI_SCI_PD_SHARED>;
+		interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x0000 0x00 0x029f0000 0x00 0x4000>;
+		ti,ddr-freq0   = <0>;
+		ti,ddr-freq1   = <0>;
+		ti,ddr-freq2   = <0>;
+		ti,ddr-fhs-cnt = <0>;
+		clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
+		instance = <3>;
+		bootph-pre-ram;
+
+		ddr3: ddr@0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x72c>,
+			      <0x00 0x2000 0x00 0x4b0>,
+			      <0x00 0x4000 0x00 0x163c>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+			bootph-pre-ram;
+		};
+
+		ddr_pmu3: ddr-pmu@100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
 
 &scm_conf {
-- 
2.34.1

[RFC PATCH 13/22] arm64: dts: ti: k3-am62: Add DDR and controller node

[MANNURU VENKATESWARLU]

From: Santhosh Kumar K <s-k6@ti.com>

Add DDR Controller and LPDDR4 node for AM62x device. This defines the
memory controller with its register regions, interrupts, power domains
and clock requirements.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index c5ee263d34a62..d873928c1bdd9 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -1265,4 +1265,29 @@ elm0: ecc@25010000 {
 		clock-names = "fck";
 		status = "disabled";
 	};
+
+	memory-controller@f300000 {
+		compatible = "ti,am62-ddrss";
+		reg = <0x00 0x0f300000 0x00 0x200>;
+		reg-names = "ss_cfg";
+		ranges = <0x00 0x00 0x00 0x0f308000 0x00 0x55f8>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 170 0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ddr: ddr@0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x69c>,
+				<0x00 0x2000 0x00 0x564>,
+				<0x00 0x4000 0x00 0x15f8>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+		};
+
+		ddr_pmu0: ddr-pmu@100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
-- 
2.34.1

[RFC PATCH 14/22] arm64: dts: ti: k3-am62a: Add DDR and controller node

[MANNURU VENKATESWARLU]

From: Santhosh Kumar K <s-k6@ti.com>

Add DDR Controller and LPDDR4 node for AM62Ax device. This defines the
memory controller with its register regions, interrupts, power domains
and clock requirements.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 33 +++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
index 9e5b75a4e88e2..9629b790aa25a 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
@@ -1172,4 +1172,37 @@ e5010: jpeg-encoder@fd20000 {
 		power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 	};
+
+	memorycontroller: memory-controller@f300000 {
+		compatible = "ti,am62a-ddrss";
+		reg = <0x00 0x0f308000 0x00 0x4000>,
+		      <0x00 0x43014000 0x00 0x100>,
+		      <0x00 0x0f300000 0x00 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+		power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>,
+				<&k3_pds 55 TI_SCI_PD_SHARED>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x0000 0x00 0x0f308000 0x00 0x5e10>;
+		ti,ddr-freq1   = <0>;
+		ti,ddr-freq2   = <0>;
+		ti,ddr-fhs-cnt = <0>;
+		clocks = <&k3_clks 170 1>, <&k3_clks 16 4>;
+		bootph-pre-ram;
+
+		ddr: ddr@0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x6cc>,
+			      <0x00 0x2000 0x00 0x6a0>,
+			      <0x00 0x4000 0x00 0x1e10>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+			bootph-pre-ram;
+		};
+
+		ddr_pmu0: ddr-pmu@100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
-- 
2.34.1

[RFC PATCH 15/22] arm64: dts: ti: k3-am62p: Add DDR and controller node

[MANNURU VENKATESWARLU]

From: Santhosh Kumar K <s-k6@ti.com>

Add DDR Controller and LPDDR4 node for AM62Px device. This defines the
memory controller with its register reginos, interrupts, power domains
and clock requirements.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 .../dts/ti/k3-am62p-j722s-common-main.dtsi    | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index f130c7cb998d7..4e07ff4fa21ea 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -1135,4 +1135,29 @@ hsm: remoteproc@43c00000 {
 		/* reserved for early-stage bootloader */
 		status = "reserved";
 	};
+
+	memory-controller@f300000 {
+		compatible = "ti,am62p-ddrss", "ti,am62a-ddrss";
+		reg = <0x00 0x0f300000 0x00 0x200>;
+		reg-names = "ss_cfg";
+		ranges = <0x00 0x00 0x00 0x0f308000 0x00 0x5e10>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 170 0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ddr: ddr@0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x6cc>,
+				<0x00 0x2000 0x00 0x6a0>,
+				<0x00 0x4000 0x00 0x1e10>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+		};
+
+		ddr_pmu0: ddr-pmu@100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
-- 
2.34.1

[RFC PATCH 16/22] arm64: dts: ti: k3-am64: Add DDR and controller node

[MANNURU VENKATESWARLU]

From: Neha Malcom Francis <n-francis@ti.com>

Add DDR Controller and LPDDR4 node for AM64x device. This defines the
memory controller with its register regions, interrupts, power domains
and clock requirements.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 33 ++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 1b1d3970888b8..f7a331ed00e28 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1675,4 +1675,37 @@ main_vtm0: temperature-sensor@b00000 {
 		power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
 		#thermal-sensor-cells = <1>;
 	};
+
+	memorycontroller: memorycontroller@f300000 {
+		compatible = "ti,am64-ddrss";
+		reg = <0x00 0x0f308000 0x00 0x4000>,
+		      <0x00 0x43014000 0x00 0x100>,
+		      <0x00 0x0f300000 0x00 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+		power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
+				<&k3_pds 55 TI_SCI_PD_SHARED>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x0000 0x00 0x0f308000 0x00 0x55f8>;
+		ti,ddr-freq1   = <0>;
+		ti,ddr-freq2   = <0>;
+		ti,ddr-fhs-cnt = <0>;
+		clocks = <&k3_clks 138 0>, <&k3_clks 16 4>;
+		bootph-pre-ram;
+
+		ddr: ddr@0 {
+			compatible = "cdns,k3-ddr";
+			reg = <0x00 0x0000 0x00 0x69c>,
+			      <0x00 0x2000 0x00 0x564>,
+			      <0x00 0x4000 0x00 0x15f8>;
+			reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+			bootph-pre-ram;
+		};
+
+		ddr_pmu0: ddr-pmu@100 {
+			compatible = "ti,k3-ddr-pmu";
+			reg = <0x00 0x100 0x00 0x14>;
+		};
+	};
 };
-- 
2.34.1