Re: [PATCH 04/10] dt-bindings: pinctrl: add Ambarella CV75 pinctrl

[Rob Herring <robh@kernel.org>]

On Thu, Jul 30, 2026 at 06:43:24PM +0800, Long Zhao wrote:
> Add the CV75 pin controller binding and pinmux ID header.
> 
> Signed-off-by: Long Zhao <longzhao@ambarella.com>
> ---
>  .../pinctrl/ambarella,cv75-pinctrl.yaml       | 167 ++++++++++++++++++
>  .../dt-bindings/pinctrl/ambarella,pinctrl.h   |  11 ++
>  2 files changed, 178 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml
>  create mode 100644 include/dt-bindings/pinctrl/ambarella,pinctrl.h
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml
> new file mode 100644
> index 000000000000..8a331c642fad
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml
> @@ -0,0 +1,167 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/ambarella,cv75-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella CV75 Pin Controller
> +
> +maintainers:
> +  - Long Zhao <longzhao@ambarella.com>
> +
> +description:
> +  The Ambarella CV75 pin controller configures pin multiplexing, bias and
> +  drive strength for the main GPIO banks. Pin multiplexing entries encode
> +  the pin number and alternate function with the AMBA_PINMUX() macro from
> +  dt-bindings/pinctrl/ambarella,pinctrl.h.
> +
> +allOf:
> +  - $ref: pinctrl.yaml#
> +
> +properties:
> +  compatible:
> +    const: ambarella,cv75-pinctrl
> +
> +  reg:
> +    items:
> +      - description: GPIO bank 0 registers
> +      - description: GPIO bank 1 registers
> +      - description: GPIO bank 2 registers
> +      - description: IOMUX registers

I'm not really convinced this is 1 h/w block. Looks more like 4 to me.

> +
> +  reg-names:
> +    items:
> +      - const: gpio0
> +      - const: gpio1
> +      - const: gpio2
> +      - const: iomux
> +
> +  interrupts:
> +    items:
> +      - description: GPIO bank 0 interrupt
> +      - description: GPIO bank 1 interrupt
> +      - description: GPIO bank 2 interrupt

These go in the child nodes or your really should have 3 instances of 
your GPIO h/w.

> +
> +  ambarella,drive-strength-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: RCT syscon containing the drive-strength registers.
> +
> +  ambarella,pull-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: Secure scratchpad syscon containing the pull registers.
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 0
> +
> +patternProperties:
> +  "^gpio@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: false
> +
> +    properties:
> +      reg:
> +        maxItems: 1

If the child nodes stay, this should be the MMIO GPIO bank address, not 
a made up bank number.

> +
> +      gpio-controller: true
> +
> +      "#gpio-cells":
> +        const: 2
> +
> +      gpio-ranges:
> +        maxItems: 1
> +
> +      interrupt-controller: true
> +
> +      "#interrupt-cells":
> +        const: 2
> +
> +    required:
> +      - reg
> +      - gpio-controller
> +      - "#gpio-cells"
> +      - gpio-ranges
> +      - interrupt-controller
> +      - "#interrupt-cells"
> +
> +  "^[a-z0-9-]+-pins$":
> +    type: object
> +    allOf:
> +      - $ref: pinmux-node.yaml#
> +      - $ref: pincfg-node.yaml#
> +    additionalProperties: false
> +
> +    properties:
> +      function: true
> +
> +      pinmux:
> +        $ref: /schemas/types.yaml#/definitions/uint32-array
> +        minItems: 1
> +        maxItems: 96
> +
> +      bias-disable: true
> +      bias-pull-down: true
> +      bias-pull-up: true
> +
> +      drive-strength:
> +        enum: [3, 4, 5, 6, 7, 8, 9, 12]
> +
> +    required:
> +      - function
> +      - pinmux
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - ambarella,drive-strength-syscon
> +  - ambarella,pull-syscon
> +  - "#address-cells"
> +  - "#size-cells"
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/pinctrl/ambarella,pinctrl.h>
> +
> +    rct: rct {
> +    };
> +
> +    scratchpad: scratchpad {
> +    };
> +
> +    pinctrl: pinctrl@e4013000 {
> +        compatible = "ambarella,cv75-pinctrl";
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        reg = <0xe4013000 0x1000>, <0xe4014000 0x1000>,
> +              <0xe4015000 0x1000>, <0xe4010000 0x1000>;

The alignment and size of these blocks is what tells me these are 
separate blocks, not 1 block.

Rob