From: Krzysztof Kozlowski <krzk@kernel.org>
To: Long Zhao <longzhao@ambarella.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Linus Walleij <linusw@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org,
soc@lists.linux.dev
Subject: Re: [PATCH v2 04/10] dt-bindings: pinctrl: add Ambarella CV75 pinctrl
Date: Fri, 7 Aug 2026 08:06:50 +0200 [thread overview]
Message-ID: <20260807-slim-amusing-jaybird-0bd13a@quoll> (raw)
In-Reply-To: <20260806-longzhao-upstream-cv75-v2-v2-4-6b09707c5fe9@ambarella.com>
On Thu, Aug 06, 2026 at 05:34:12PM +0800, Long Zhao wrote:
> Add the CV75 pin controller binding.
>
> Signed-off-by: Long Zhao <longzhao@ambarella.com>
> ---
> .../bindings/pinctrl/ambarella,cv75-pinctrl.yaml | 175 +++++++++++++++++++++
> 1 file changed, 175 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml
> new file mode 100644
> index 000000000000..3fa30b275e51
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml
> @@ -0,0 +1,175 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/ambarella,cv75-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella CV75 Pin Controller
> +
> +maintainers:
> + - Long Zhao <longzhao@ambarella.com>
> +
> +description:
> + The Ambarella CV75 pin controller configures pin multiplexing, bias and
> + drive strength for the main GPIO banks. Pin groups and their mux settings
> + are defined by the pin controller driver and selected by function and group
> + names.
> +
> +allOf:
> + - $ref: pinctrl.yaml#
> +
> +properties:
> + compatible:
> + const: ambarella,cv75-pinctrl
> +
> + reg:
> + maxItems: 1
> + description: IOMUX registers
> +
> + ambarella,drive-strength-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: RCT syscon containing the drive-strength registers.
> +
> + ambarella,pull-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: Secure scratchpad syscon containing the pull registers.
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges: true
> +
> +patternProperties:
> + "^gpio@[0-9a-f]+$":
> + type: object
> + additionalProperties: false
> +
> + properties:
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + gpio-controller: true
> +
> + "#gpio-cells":
> + const: 2
> +
> + gpio-ranges:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 2
> +
> + required:
> + - reg
> + - interrupts
> + - gpio-controller
> + - "#gpio-cells"
> + - gpio-ranges
> + - interrupt-controller
> + - "#interrupt-cells"
> +
> + "^[a-z0-9-]+-pins$":
Mixing MMIO and non-MMIO nodes in a bus is discouraged. Sloppy code.
Why the pins aren't per gpio-controller?
> + type: object
> + allOf:
> + - $ref: pinmux-node.yaml#
> + - $ref: pincfg-node.yaml#
> + additionalProperties: false
> +
> + properties:
> + function:
> + const: uart0
If the function is fixed, then you do not need any of this.
You must post COMPLETE bindings, see writing bindings doc.
> +
> + groups:
> + $ref: /schemas/types.yaml#/definitions/string-array
> + items:
> + enum: [uart0tx, uart0rx]
Same here, pointless/redunadnt.
> + minItems: 2
> + maxItems: 2
> + uniqueItems: true
> +
> + bias-disable: true
> + bias-pull-down: true
> + bias-pull-up: true
> +
> + drive-strength:
> + enum: [3, 4, 5, 6, 7, 8, 9, 12]
> +
> + required:
> + - function
> + - groups
> +
> +required:
> + - compatible
> + - reg
> + - ambarella,drive-strength-syscon
> + - ambarella,pull-syscon
> + - "#address-cells"
> + - "#size-cells"
> + - ranges
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + rct: rct {
> + };
> +
> + scratchpad: scratchpad {
> + };
Drop above, irrelevant. Do you see any other bindings doing this?
> +
> + pinctrl: pinctrl@e4010000 {
> + compatible = "ambarella,cv75-pinctrl";
> + #address-cells = <1>;
> + #size-cells = <1>;
You need to follow DTS coding style.
> + reg = <0xe4010000 0x1000>;
> + ranges;
> + ambarella,drive-strength-syscon = <&rct>;
> + ambarella,pull-syscon = <&scratchpad>;
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-08-07 6:07 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-06 9:34 [PATCH v2 00/10] Ambarella CV75 SoC minimal bring-up Long Zhao via B4 Relay
2026-08-06 9:34 ` [PATCH v2 01/10] dt-bindings: arm: add Ambarella CV75 platforms Long Zhao via B4 Relay
2026-08-07 6:00 ` Krzysztof Kozlowski
2026-08-06 9:34 ` [PATCH v2 02/10] dt-bindings: soc: add Ambarella secure scratchpad Long Zhao via B4 Relay
2026-08-07 6:01 ` Krzysztof Kozlowski
2026-08-07 8:29 ` Long Zhao
2026-08-06 9:34 ` [PATCH v2 03/10] dt-bindings: clock: add Ambarella CV75 RCT clock controller Long Zhao via B4 Relay
2026-08-06 10:56 ` Rob Herring (Arm)
2026-08-07 6:02 ` Krzysztof Kozlowski
2026-08-06 9:34 ` [PATCH v2 04/10] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Long Zhao via B4 Relay
2026-08-07 6:06 ` Krzysztof Kozlowski [this message]
2026-08-06 9:34 ` [PATCH v2 05/10] dt-bindings: serial: add Ambarella UART Long Zhao via B4 Relay
2026-08-06 9:34 ` [PATCH v2 06/10] clk: ambarella: add CV75 CCU driver Long Zhao via B4 Relay
2026-08-06 9:34 ` [PATCH v2 07/10] pinctrl: ambarella: add Ambarella pin controller Long Zhao via B4 Relay
2026-08-07 17:45 ` Linus Walleij
2026-08-06 9:34 ` [PATCH v2 08/10] serial: ambarella: add Ambarella UART driver Long Zhao via B4 Relay
2026-08-07 6:18 ` Jiri Slaby
2026-08-07 18:37 ` Linus Walleij
2026-08-06 9:34 ` [PATCH v2 09/10] arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT Long Zhao via B4 Relay
2026-08-07 6:11 ` Krzysztof Kozlowski
2026-08-06 9:34 ` [PATCH v2 10/10] MAINTAINERS: add ARM/AMBARELLA SoC support Long Zhao via B4 Relay
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260807-slim-amusing-jaybird-0bd13a@quoll \
--to=krzk@kernel.org \
--cc=alexandre.belloni@bootlin.com \
--cc=arnd@arndb.de \
--cc=catalin.marinas@arm.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=jirislaby@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linusw@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-serial@vger.kernel.org \
--cc=longzhao@ambarella.com \
--cc=mturquette@baylibre.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=soc@lists.linux.dev \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox