[PATCH 16/25] clk: rockchip: Add SCLK_IN_SPI1 gate for RV1106

[Vladislav Leonov <vlad@zlab.su>]

Register the SCLK_IN_SPI1 clock gate (PERICLKGATE_CON3, bit 8),
mirroring the existing SCLK_IN_SPI0 gate. This clock is documented in
the RV1106 TRM but was missing in the Rockchip BSP kernel.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 drivers/clk/rockchip/clk-rv1106.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c
index 1e3a110192bb..236159157c7e 100644
--- a/drivers/clk/rockchip/clk-rv1106.c
+++ b/drivers/clk/rockchip/clk-rv1106.c
@@ -976,6 +976,8 @@ static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
 			RV1106_VEPUCLKGATE_CON(0), 14, GFLAGS),
 	GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0,
 			RV1106_VEPUCLKGATE_CON(1), 4, GFLAGS),
+	GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0,
+			RV1106_PERICLKGATE_CON(3), 8, GFLAGS),
 
 	GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
 			RV1106_PERICLKGATE_CON(4), 9, GFLAGS),
-- 
2.47.3