[PATCH] ARM: dts: vf500: describe the Cortex-A5 L1 caches

[PATCH] ARM: dts: vf500: describe the Cortex-A5 L1 caches

[Mehmet Fide]

From: Mehmet Fide <mehmet.fide@screeningeagle.com>

The cpu node carries no cache properties, so cacheinfo has nothing to
build the hierarchy from and gives up at boot:

  cacheinfo: Unable to detect cache hierarchy for CPU 0

The level and the type of the two L1 caches come from CLIDR and CCSIDR,
but the geometry does not, so /sys/devices/system/cpu/cpu0/cache is left
without a size, a line size or a set count.

Fill them in from the Vybrid reference manual (NXP VFXXXRM), table 2-4
"Platform modules": the A5 has a 2 way set associative 32 KB instruction
cache and a 4 way set associative 32 KB data cache, both with a 32 byte
line, so 512 and 256 sets.

Tested on a Colibri VF50. The warning is gone and sysfs now reports both
caches with the geometry above.

Signed-off-by: Mehmet Fide <mehmet.fide@screeningeagle.com>
---
 arch/arm/boot/dts/nxp/vf/vf500.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/vf/vf500.dtsi b/arch/arm/boot/dts/nxp/vf/vf500.dtsi
index 71ccdaa..a73e9a8 100644
--- a/arch/arm/boot/dts/nxp/vf/vf500.dtsi
+++ b/arch/arm/boot/dts/nxp/vf/vf500.dtsi
@@ -18,6 +18,12 @@
 		a5_cpu: cpu@0 {
 			compatible = "arm,cortex-a5";
 			device_type = "cpu";
+			d-cache-line-size = <32>;
+			d-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			i-cache-sets = <512>;
+			i-cache-size = <0x8000>;
 			reg = <0x0>;
 		};
 	};
-- 
2.54.0