From: phucduc.bui@gmail.com
To: Mark Brown <broonie@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
Cezary Rojewski <cezary.rojewski@intel.com>,
linux-sound@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
bui duc phuc <phucduc.bui@gmail.com>
Subject: [PATCH v3 2/8] ASoC: mediatek: mt8186: Fix clock handling in mux disable path
Date: Fri, 28 Aug 2026 16:15:26 +0700 [thread overview]
Message-ID: <20260828091532.600047-3-phucduc.bui@gmail.com> (raw)
In-Reply-To: <20260828091532.600047-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
In the disable path of the appl*_mux_setting() functions,
clk_disable_unprepare() is called after clk_set_parent().
If clk_set_parent() fails, clk_disable_unprepare() is skipped,
potentially leaving one of the clocks enabled.
Move the clk_disable_unprepare() calls before clk_set_parent()
so that the clocks are always disabled and unprepared in the
disable path.
Fixes: 55b423d5623c ("ASoC: mediatek: mt8186: support audio clock control in platform driver")
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/mediatek/mt8186/mt8186-afe-clk.c | 70 +++++++++++-----------
1 file changed, 36 insertions(+), 34 deletions(-)
diff --git a/sound/soc/mediatek/mt8186/mt8186-afe-clk.c b/sound/soc/mediatek/mt8186/mt8186-afe-clk.c
index aa8b2eaf7b95..a517aa67abf6 100644
--- a/sound/soc/mediatek/mt8186/mt8186-afe-clk.c
+++ b/sound/soc/mediatek/mt8186/mt8186-afe-clk.c
@@ -125,25 +125,26 @@ static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG1;
}
} else {
- ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
- afe_priv->clk[CLK_CLK26M]);
- if (ret) {
- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
- __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
- aud_clks[CLK_CLK26M], ret);
- goto EXIT;
- }
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
-
- ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
- afe_priv->clk[CLK_CLK26M]);
- if (ret) {
- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
- __func__, aud_clks[CLK_TOP_MUX_AUD_1],
- aud_clks[CLK_CLK26M], ret);
- goto EXIT;
- }
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
+
+ ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
+ afe_priv->clk[CLK_CLK26M]);
+ if (ret) {
+ dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
+ __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
+ aud_clks[CLK_CLK26M], ret);
+ goto EXIT;
+ }
+
+ ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
+ afe_priv->clk[CLK_CLK26M]);
+ if (ret) {
+ dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
+ __func__, aud_clks[CLK_TOP_MUX_AUD_1],
+ aud_clks[CLK_CLK26M], ret);
+ goto EXIT;
+ }
}
return 0;
@@ -199,25 +200,26 @@ static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG2;
}
} else {
- ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
- afe_priv->clk[CLK_CLK26M]);
- if (ret) {
- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
- __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
- aud_clks[CLK_CLK26M], ret);
- goto EXIT;
- }
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
-
- ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
- afe_priv->clk[CLK_CLK26M]);
- if (ret) {
- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
- __func__, aud_clks[CLK_TOP_MUX_AUD_2],
- aud_clks[CLK_CLK26M], ret);
- goto EXIT;
- }
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
+
+ ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
+ afe_priv->clk[CLK_CLK26M]);
+ if (ret) {
+ dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
+ __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
+ aud_clks[CLK_CLK26M], ret);
+ goto EXIT;
+ }
+
+ ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
+ afe_priv->clk[CLK_CLK26M]);
+ if (ret) {
+ dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
+ __func__, aud_clks[CLK_TOP_MUX_AUD_2],
+ aud_clks[CLK_CLK26M], ret);
+ goto EXIT;
+ }
}
return 0;
--
2.43.0
next prev parent reply other threads:[~2026-08-28 9:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 9:15 [PATCH v3 0/8] ASoC: mediatek: mt8186: Fix clock error handling phucduc.bui
2026-08-28 9:15 ` [PATCH v3 1/8] ASoC: mediatek: mt8186: Fix APLL mux setting " phucduc.bui
2026-08-28 9:15 ` phucduc.bui [this message]
2026-08-28 9:15 ` [PATCH v3 3/8] ASoC: mediatek: mt8186: Fix AFE clock " phucduc.bui
2026-08-28 9:15 ` [PATCH v3 4/8] ASoC: mediatek: mt8186: Fix APLL enable " phucduc.bui
2026-08-28 9:15 ` [PATCH v3 5/8] ASoC: mediatek: mt8186: Fix MCK " phucduc.bui
2026-08-28 9:15 ` [PATCH v3 6/8] ASoC: mediatek: mt8186: Fix gpio rollback on adda dl/ul partial failure phucduc.bui
2026-08-28 9:15 ` [PATCH v3 7/8] ASoC: mediatek: mt8186: Handle regcache sync failure phucduc.bui
2026-08-28 9:15 ` [PATCH v3 8/8] ASoC: mediatek: mt8186: Drop redundant probe error messages phucduc.bui
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