[PATCH v4 0/2] ARM: dts: aspeed: Add ASRock Rack B650D4U BMC

[PATCH v4 0/2] ARM: dts: aspeed: Add ASRock Rack B650D4U BMC

[Prasanth Kumar Padarthi]

Add device tree support for the ASRock Rack B650D4U BMC, which is
based on the ASPEED AST2600 SoC.

The series adds the board compatible and describes the BMC memory,
SPI NOR flash layout, UART console, and MAC0 connected to an
RTL8211F Ethernet PHY.

The MAC0 RGMII timing configuration was validated on B650D4U
hardware. With plain "rgmii", the PHY negotiated 1000baseT/Full but
received no valid packets and accumulated RX CRC errors. With
"rgmii-rxid", a 5000-packet test completed with 0% packet loss and
no RX CRC errors. "rgmii-id" was also tested successfully, but the
additional TX delay is not required, so "rgmii-rxid" is retained.

Changes in v4:
- Validate the MAC0 RGMII timing configuration on B650D4U hardware.
- Keep phy-mode = "rgmii-rxid" based on hardware A/B testing.
- Add the SPI NOR fixed partition layout validated on B650D4U
  hardware.
- Correct the BMC memory size to 512 MiB.
- Order peripheral nodes alphabetically by label.

Prasanth Kumar Padarthi (2):
  dt-bindings: arm: aspeed: Add ASRock Rack B650D4U
  ARM: dts: aspeed: Add ASRock Rack B650D4U BMC

 .../bindings/arm/aspeed/aspeed.yaml           |  1 +
 arch/arm/boot/dts/aspeed/Makefile             |  1 +
 .../dts/aspeed/aspeed-bmc-asrock-b650d4u.dts  | 95 +++++++++++++++++++
 3 files changed, 97 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts

-- 
2.47.3

[PATCH v4 1/2] dt-bindings: arm: aspeed: Add ASRock Rack B650D4U

[Prasanth Kumar Padarthi]

Add the compatible string for the ASRock Rack B650D4U BMC,
which is an AST2600-based server motherboard.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Prasanth Kumar Padarthi <prasanth.padarthi10@gmail.com>
---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index 9ba195b8f22d..4c9e96801c1a 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -81,6 +81,7 @@ properties:
               - ampere,mtmitchell-bmc
               - aspeed,ast2600-evb
               - aspeed,ast2600-evb-a1
+              - asrock,b650d4u-bmc
               - asus,ast2600-kommando-ipmi-card
               - asus,x4tf-bmc
               - facebook,anacapa-bmc
-- 
2.47.3

[PATCH v4 2/2] ARM: dts: aspeed: Add ASRock Rack B650D4U BMC

[Prasanth Kumar Padarthi]

Add the device tree for the ASRock Rack B650D4U BMC, which is
based on the ASPEED AST2600 SoC.

Describe the BMC memory, SPI NOR flash layout, UART console, and
MAC0 connected to an RTL8211F Ethernet PHY.

The MAC0 RGMII RX delay configuration was validated on hardware.
The RTL8211F requires its internal RX delay for reliable operation,
while an additional TX delay is not required.

Signed-off-by: Prasanth Kumar Padarthi <prasanth.padarthi10@gmail.com>
---
 arch/arm/boot/dts/aspeed/Makefile             |  1 +
 .../dts/aspeed/aspeed-bmc-asrock-b650d4u.dts  | 95 +++++++++++++++++++
 2 files changed, 96 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts

diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
index 6b68671f9379..b109491d5c8f 100644
--- a/arch/arm/boot/dts/aspeed/Makefile
+++ b/arch/arm/boot/dts/aspeed/Makefile
@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-ampere-mtmitchell.dtb \
 	aspeed-bmc-arm-stardragon4800-rep2.dtb \
 	aspeed-bmc-asrock-altrad8.dtb \
+	aspeed-bmc-asrock-b650d4u.dtb \
 	aspeed-bmc-asrock-e3c246d4i.dtb \
 	aspeed-bmc-asrock-e3c256d4i.dtb \
 	aspeed-bmc-asrock-paul-ipmi-card.dtb \
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts
new file mode 100644
index 000000000000..aa623f0ca36c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+
+/ {
+	model = "ASRock Rack B650D4U BMC";
+	compatible = "asrock,b650d4u-bmc", "aspeed,ast2600";
+
+	aliases {
+		serial0 = &uart5;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x20000000>;
+	};
+};
+
+&fmc {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		label = "bmc";
+		m25p,fast-read;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			u-boot@0 {
+				reg = <0x00000000 0x000e0000>;
+				label = "u-boot";
+				read-only;
+			};
+
+			u-boot-env@e0000 {
+				reg = <0x000e0000 0x00020000>;
+				label = "u-boot-env";
+			};
+
+			kernel@200000 {
+				reg = <0x00200000 0x00800000>;
+				label = "kernel";
+			};
+
+			rofs@a00000 {
+				reg = <0x00a00000 0x02000000>;
+				label = "rofs";
+				read-only;
+			};
+
+			rwfs@2a00000 {
+				reg = <0x02a00000 0x01600000>;
+				label = "rwfs";
+			};
+		};
+	};
+};
+
+&mac0 {
+	status = "okay";
+
+	/*
+	 * The RTL8211F provides the required RGMII RX delay. No additional
+	 * TX delay is required for this board.
+	 */
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&ethphy0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii1_default>;
+};
+
+&mdio0 {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&uart5 {
+	status = "okay";
+};
-- 
2.47.3

Re: [PATCH v4 2/2] ARM: dts: aspeed: Add ASRock Rack B650D4U BMC

[Tan Siewert]

Hi Prasanth,

On 8/30/26 8:20 PM, Prasanth Kumar Padarthi wrote:
> Add the device tree for the ASRock Rack B650D4U BMC, which is
> based on the ASPEED AST2600 SoC.
> 
> Describe the BMC memory, SPI NOR flash layout, UART console, and
> MAC0 connected to an RTL8211F Ethernet PHY.

Why no GPIOs? Why no I2C buses? You'd need at least i2c7 with an at24c128 to
populate the MAC address on MAC0.

> 
> The MAC0 RGMII RX delay configuration was validated on hardware.
> The RTL8211F requires its internal RX delay for reliable operation,
> while an additional TX delay is not required.

No, it does not. The traces have the same length and don't require special
delays. If you use u-boot/next, then it might be true because it still misses
the correct SoC-specific delays. This is, however, fixed in openbmc/u-boot.

I know that this is not optimal. I'm already working on getting this fixed in
upstream U-Boot too.

> 
> Signed-off-by: Prasanth Kumar Padarthi <prasanth.padarthi10@gmail.com>
>
> diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
> index 6b68671f9379..b109491d5c8f 100644
> --- a/arch/arm/boot/dts/aspeed/Makefile
> +++ b/arch/arm/boot/dts/aspeed/Makefile
> @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
>  	aspeed-bmc-ampere-mtmitchell.dtb \
>  	aspeed-bmc-arm-stardragon4800-rep2.dtb \
>  	aspeed-bmc-asrock-altrad8.dtb \
> +	aspeed-bmc-asrock-b650d4u.dtb \
>  	aspeed-bmc-asrock-e3c246d4i.dtb \
>  	aspeed-bmc-asrock-e3c256d4i.dtb \
>  	aspeed-bmc-asrock-paul-ipmi-card.dtb \
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts
> new file mode 100644
> index 000000000000..aa623f0ca36c
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +
> +#include "aspeed-g6.dtsi"
> +
> +/ {
> +	model = "ASRock Rack B650D4U BMC";
> +	compatible = "asrock,b650d4u-bmc", "aspeed,ast2600";
> +
> +	aliases {
> +		serial0 = &uart5;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x80000000 0x20000000>;
> +	};

Where's the reservation for video?

> +};
> +
> +&fmc {
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;

That's already defined in aspeed-g6.dtsi

> +		label = "bmc";
> +		m25p,fast-read;
> +		spi-max-frequency = <50000000>;
> +		spi-rx-bus-width = <4>;
> +		status = "okay";
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			u-boot@0 {
> +				reg = <0x00000000 0x000e0000>;
> +				label = "u-boot";
> +				read-only;
> +			};
> +
> +			u-boot-env@e0000 {
> +				reg = <0x000e0000 0x00020000>;
> +				label = "u-boot-env";
> +			};
> +
> +			kernel@200000 {
> +				reg = <0x00200000 0x00800000>;
> +				label = "kernel";
> +			};
> +
> +			rofs@a00000 {
> +				reg = <0x00a00000 0x02000000>;
> +				label = "rofs";
> +				read-only;
> +			};
> +
> +			rwfs@2a00000 {
> +				reg = <0x02a00000 0x01600000>;
> +				label = "rwfs";
> +			};

No. Include the partitions via `#include openbmc-flash-layout-64.dtsi`.

> +		};
> +	};
> +};
> +
> +&mac0 {
> +	status = "okay";
> +
> +	/*
> +	 * The RTL8211F provides the required RGMII RX delay. No additional
> +	 * TX delay is required for this board.
> +	 */

No? I do have this board myself with a custom BMC ROM and I can tell you that
you don't have to set delays other than the described SoC-specific delays, but
this is, as mentioned, already done in the BSP. (And no, I haven't upstreamed
my DTS yet bc I haven't had the time to do it.)

> +	phy-mode = "rgmii-rxid";

`rgmii-id`

> +	phy-handle = <&ethphy0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_rgmii1_default>;

No nvmem cell to set the MAC address? i2c7@57 offset 0x3f80? Please see the
other device-trees for ASRock Rack mainboards.

For me, it is a:

NACKed-by: Tan Siewert <tan.siewert@9elements.com>

Tan

-- 
Tan Siewert <tan.siewert@9elements.com>

Re: [PATCH v4 2/2] ARM: dts: aspeed: Add ASRock Rack B650D4U BMC

[Prasanth]

Hi Tan,

Thanks, this is very helpful, especially since you have tested the same board.

I will rework the next revision to use the existing ASRock Rack DTS
patterns, including the I2C7 EEPROM/NVMEM MAC address handling and the
standard 64 MiB OpenBMC flash layout. I will also investigate the
GPIOs and video memory reservation you mentioned.

For MAC0, I will change the PHY mode to rgmii-id and remove the claim
that the board requires RX-only PHY delay. I will also investigate the
ASPEED SoC-specific MAC delay configuration and the difference between
upstream U-Boot and openbmc/u-boot before sending the next revision.

Thanks,
Prasanth

On Mon, Aug 31, 2026 at 6:07 PM Tan Siewert <tan.siewert@9elements.com> wrote:
>
> Hi Prasanth,
>
> On 8/30/26 8:20 PM, Prasanth Kumar Padarthi wrote:
> > Add the device tree for the ASRock Rack B650D4U BMC, which is
> > based on the ASPEED AST2600 SoC.
> >
> > Describe the BMC memory, SPI NOR flash layout, UART console, and
> > MAC0 connected to an RTL8211F Ethernet PHY.
>
> Why no GPIOs? Why no I2C buses? You'd need at least i2c7 with an at24c128 to
> populate the MAC address on MAC0.
>
> >
> > The MAC0 RGMII RX delay configuration was validated on hardware.
> > The RTL8211F requires its internal RX delay for reliable operation,
> > while an additional TX delay is not required.
>
> No, it does not. The traces have the same length and don't require special
> delays. If you use u-boot/next, then it might be true because it still misses
> the correct SoC-specific delays. This is, however, fixed in openbmc/u-boot.
>
> I know that this is not optimal. I'm already working on getting this fixed in
> upstream U-Boot too.
>
> >
> > Signed-off-by: Prasanth Kumar Padarthi <prasanth.padarthi10@gmail.com>
> >
> > diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
> > index 6b68671f9379..b109491d5c8f 100644
> > --- a/arch/arm/boot/dts/aspeed/Makefile
> > +++ b/arch/arm/boot/dts/aspeed/Makefile
> > @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
> >       aspeed-bmc-ampere-mtmitchell.dtb \
> >       aspeed-bmc-arm-stardragon4800-rep2.dtb \
> >       aspeed-bmc-asrock-altrad8.dtb \
> > +     aspeed-bmc-asrock-b650d4u.dtb \
> >       aspeed-bmc-asrock-e3c246d4i.dtb \
> >       aspeed-bmc-asrock-e3c256d4i.dtb \
> >       aspeed-bmc-asrock-paul-ipmi-card.dtb \
> > diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts
> > new file mode 100644
> > index 000000000000..aa623f0ca36c
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts
> > @@ -0,0 +1,95 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/dts-v1/;
> > +
> > +#include "aspeed-g6.dtsi"
> > +
> > +/ {
> > +     model = "ASRock Rack B650D4U BMC";
> > +     compatible = "asrock,b650d4u-bmc", "aspeed,ast2600";
> > +
> > +     aliases {
> > +             serial0 = &uart5;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +     };
> > +
> > +     memory@80000000 {
> > +             device_type = "memory";
> > +             reg = <0x80000000 0x20000000>;
> > +     };
>
> Where's the reservation for video?
>
> > +};
> > +
> > +&fmc {
> > +     status = "okay";
> > +
> > +     flash@0 {
> > +             compatible = "jedec,spi-nor";
> > +             reg = <0>;
>
> That's already defined in aspeed-g6.dtsi
>
> > +             label = "bmc";
> > +             m25p,fast-read;
> > +             spi-max-frequency = <50000000>;
> > +             spi-rx-bus-width = <4>;
> > +             status = "okay";
> > +
> > +             partitions {
> > +                     compatible = "fixed-partitions";
> > +                     #address-cells = <1>;
> > +                     #size-cells = <1>;
> > +
> > +                     u-boot@0 {
> > +                             reg = <0x00000000 0x000e0000>;
> > +                             label = "u-boot";
> > +                             read-only;
> > +                     };
> > +
> > +                     u-boot-env@e0000 {
> > +                             reg = <0x000e0000 0x00020000>;
> > +                             label = "u-boot-env";
> > +                     };
> > +
> > +                     kernel@200000 {
> > +                             reg = <0x00200000 0x00800000>;
> > +                             label = "kernel";
> > +                     };
> > +
> > +                     rofs@a00000 {
> > +                             reg = <0x00a00000 0x02000000>;
> > +                             label = "rofs";
> > +                             read-only;
> > +                     };
> > +
> > +                     rwfs@2a00000 {
> > +                             reg = <0x02a00000 0x01600000>;
> > +                             label = "rwfs";
> > +                     };
>
> No. Include the partitions via `#include openbmc-flash-layout-64.dtsi`.
>
> > +             };
> > +     };
> > +};
> > +
> > +&mac0 {
> > +     status = "okay";
> > +
> > +     /*
> > +      * The RTL8211F provides the required RGMII RX delay. No additional
> > +      * TX delay is required for this board.
> > +      */
>
> No? I do have this board myself with a custom BMC ROM and I can tell you that
> you don't have to set delays other than the described SoC-specific delays, but
> this is, as mentioned, already done in the BSP. (And no, I haven't upstreamed
> my DTS yet bc I haven't had the time to do it.)
>
> > +     phy-mode = "rgmii-rxid";
>
> `rgmii-id`
>
> > +     phy-handle = <&ethphy0>;
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pinctrl_rgmii1_default>;
>
> No nvmem cell to set the MAC address? i2c7@57 offset 0x3f80? Please see the
> other device-trees for ASRock Rack mainboards.
>
> For me, it is a:
>
> NACKed-by: Tan Siewert <tan.siewert@9elements.com>
>
> Tan
>
> --
> Tan Siewert <tan.siewert@9elements.com>

Re: [PATCH v4 0/2] ARM: dts: aspeed: Add ASRock Rack B650D4U BMC

[Andrew Lunn]

On Sun, Aug 30, 2026 at 11:50:34PM +0530, Prasanth Kumar Padarthi wrote:
> Add device tree support for the ASRock Rack B650D4U BMC, which is
> based on the ASPEED AST2600 SoC.
> 
> The series adds the board compatible and describes the BMC memory,
> SPI NOR flash layout, UART console, and MAC0 connected to an
> RTL8211F Ethernet PHY.
> 
> The MAC0 RGMII timing configuration was validated on B650D4U
> hardware. With plain "rgmii", the PHY negotiated 1000baseT/Full but
> received no valid packets and accumulated RX CRC errors. With
> "rgmii-rxid", a 5000-packet test completed with 0% packet loss and
> no RX CRC errors. "rgmii-id" was also tested successfully, but the
> additional TX delay is not required, so "rgmii-rxid" is retained.

Please take a read of:

https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/net/ethernet-controller.yaml#L287

Does the PCB have 2ns of delay for TX, but notR RX?

     Andrew

Re: [PATCH v4 0/2] ARM: dts: aspeed: Add ASRock Rack B650D4U BMC

[Prasanth]

Hi Andrew,

I do not currently have the PCB layout or RGMII trace-length information,
so I cannot confirm that the PCB provides approximately 2 ns of TX delay
but no RX delay.

My hardware results are:

rgmii negotiates 1000baseT/Full, but RX traffic fails with CRC errors.
rgmii-rxid passes a 5000-packet test with no loss or RX CRC errors.
rgmii-id also passes the same test.

These results indicate that an RX delay is required, but they do not
establish whether the TX delay is provided by the PCB, MAC, or PHY. I
therefore agree that the traffic test alone is insufficient to justify
rgmii-rxid.

I have contacted ASRock Rack requesting confirmation of the RGMII timing
and PCB trace-delay configuration. I will wait for that information
before selecting the phy-mode for the next revision or making a claim
about where the TX delay is implemented.

Thanks,
Prasanth

On Mon, Aug 31, 2026 at 1:53 AM Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Sun, Aug 30, 2026 at 11:50:34PM +0530, Prasanth Kumar Padarthi wrote:
> > Add device tree support for the ASRock Rack B650D4U BMC, which is
> > based on the ASPEED AST2600 SoC.
> >
> > The series adds the board compatible and describes the BMC memory,
> > SPI NOR flash layout, UART console, and MAC0 connected to an
> > RTL8211F Ethernet PHY.
> >
> > The MAC0 RGMII timing configuration was validated on B650D4U
> > hardware. With plain "rgmii", the PHY negotiated 1000baseT/Full but
> > received no valid packets and accumulated RX CRC errors. With
> > "rgmii-rxid", a 5000-packet test completed with 0% packet loss and
> > no RX CRC errors. "rgmii-id" was also tested successfully, but the
> > additional TX delay is not required, so "rgmii-rxid" is retained.
>
> Please take a read of:
>
> https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/net/ethernet-controller.yaml#L287
>
> Does the PCB have 2ns of delay for TX, but notR RX?
>
>      Andrew

Re: [PATCH v4 0/2] ARM: dts: aspeed: Add ASRock Rack B650D4U BMC

[Andrew Lunn]

On Mon, Aug 31, 2026 at 06:43:46AM +0530, Prasanth wrote:
> Hi Andrew,
> 
> I do not currently have the PCB layout or trace-length information, so I cannot
> prove that the board provides the TX delay externally.
> 
> What I have validated on hardware is:
> 
> rgmii: fails, with RX CRC errors and no valid RX traffic
> rgmii-rxid: passes, 5000/5000 packets, 0% loss, no RX CRC errors
> rgmii-id: also passes with the same traffic test
> 
> This shows that the RTL8211F RX internal delay is required, but it does not
> establish where the TX delay is provided.
> 
> Given that I cannot provide PCB-level evidence for the TX delay, would you
> prefer that I use rgmii-id for the next revision?

There has been a number of threads about the Aspeed SoC. It typically
has delays enabled in its MAC, by the bootloader. The Linux MAC driver
does not disable this, nor does it mask the value passed to the
PHY. So you see many Aspeed .dts files incorrectly using 'rgmii'. Over
the last couple of years i have been pointing out this problem, but
nobody has stepped up to fix the issue. Most DT developers just leave
the Ethernet node out, in order to get something merged.

You case is interesting, because you are not suggesting 'rgmii'. So it
could be there is more going on.

If you look in the email archives you should find the information
about where to configure the delay in the hardware. You might want to
read it out to understand how the bootloader has configured the
hardware.

    Andrew

Re: [PATCH v4 0/2] ARM: dts: aspeed: Add ASRock Rack B650D4U BMC

[Prasanth]

Hi Andrew,

Thanks. As I mentioned earlier, I had already found that the AST2600
has MAC-side RGMII delay configuration.

I will now check the actual delay register values on this board after
U-Boot has initialized the MAC, and compare them with the
corresponding U-Boot configuration. That should help determine how
much of the observed behavior is coming from the MAC-side delays left
configured by the bootloader.

Tan Siewert has also confirmed that the RGMII traces on the B650D4U do
not provide the delay, and pointed out the difference between the
SoC-specific delay handling in upstream U-Boot and openbmc/u-boot.

I will investigate that before preparing the next revision and will
remove the RX-only delay claim from the current patch.

Thanks,
Prasanth

On Mon, Aug 31, 2026 at 5:42 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Mon, Aug 31, 2026 at 06:43:46AM +0530, Prasanth wrote:
> > Hi Andrew,
> >
> > I do not currently have the PCB layout or trace-length information, so I cannot
> > prove that the board provides the TX delay externally.
> >
> > What I have validated on hardware is:
> >
> > rgmii: fails, with RX CRC errors and no valid RX traffic
> > rgmii-rxid: passes, 5000/5000 packets, 0% loss, no RX CRC errors
> > rgmii-id: also passes with the same traffic test
> >
> > This shows that the RTL8211F RX internal delay is required, but it does not
> > establish where the TX delay is provided.
> >
> > Given that I cannot provide PCB-level evidence for the TX delay, would you
> > prefer that I use rgmii-id for the next revision?
>
> There has been a number of threads about the Aspeed SoC. It typically
> has delays enabled in its MAC, by the bootloader. The Linux MAC driver
> does not disable this, nor does it mask the value passed to the
> PHY. So you see many Aspeed .dts files incorrectly using 'rgmii'. Over
> the last couple of years i have been pointing out this problem, but
> nobody has stepped up to fix the issue. Most DT developers just leave
> the Ethernet node out, in order to get something merged.
>
> You case is interesting, because you are not suggesting 'rgmii'. So it
> could be there is more going on.
>
> If you look in the email archives you should find the information
> about where to configure the delay in the hardware. You might want to
> read it out to understand how the bootloader has configured the
> hardware.
>
>     Andrew