[PATCH net-next 0/3] net: phy: motorcomm: Enable analog frontend DAC on yt8531S

[PATCH net-next 0/3] net: phy: motorcomm: Enable analog frontend DAC on yt8531S

[Maxime Chevallier]

In the process of getting more stmmac boards to run tests on, I've
acquired a nice and inexpensive YT6801 PCIe card, that can do
10/100/1000BaseT. It uses stmmac's PCI variant dwmac-motorcomm, as well
as an integrated Motorcomm PHY (the YT8531S).

However while testing the card, I had link-up maybe once every 10
reboots, and no traffic whatsoever. Comparing with the out-of-tree
driver provided by Motorcomm, it was found that some Analog Frontend DAC
needs a clock to be enabled, and indeed it fixed the issue.

As I don't know much about this device, this series implements the DAC
CLK configuration in the YT8531S driver only for the integrated version,
that uses the GMII interface.

I split that into 3 commits, the first 2 are splitting-out the YT8521
and YT8531S config_init(). The third commit adds the DAC configuration.

This was tested on YT6801, which now reliably reports link up.

Maxime Chevallier (3):
  net: phy: motorcomm: Split yt8521_config_init() page management
  net: phy: motorcomm: Add a dedicated .config_init for YT8531S
  net: phy: motorcomm: Enable analog frontend on YT8531S

 drivers/net/phy/motorcomm.c | 76 ++++++++++++++++++++++++++-----------
 1 file changed, 54 insertions(+), 22 deletions(-)

-- 
2.55.0

[PATCH net-next 1/3] net: phy: motorcomm: Split yt8521_config_init() page management

[Maxime Chevallier]

In preparation for separate .config_init() implementations for YT8521
and YT8531S, let's split the yt8521_config_init() into a high-level
helper that deals with page handling, and another one that implements
the logic. This will ease splitting the YT8531S-specific logic out.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
---
 drivers/net/phy/motorcomm.c | 38 ++++++++++++++++++++++---------------
 1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index c5a2cda8d31b..58e4d67b945f 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c
@@ -1680,27 +1680,16 @@ static int yt8521_resume(struct phy_device *phydev)
 	return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0);
 }
 
-/**
- * yt8521_config_init() - called to initialize the PHY
- * @phydev: a pointer to a &struct phy_device
- *
- * returns 0 or negative errno code
- */
-static int yt8521_config_init(struct phy_device *phydev)
+static int __yt8521_config_init(struct phy_device *phydev)
 {
 	struct device *dev = &phydev->mdio.dev;
-	int old_page;
 	int ret = 0;
 
-	old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
-	if (old_page < 0)
-		goto err_restore_page;
-
 	/* set rgmii delay mode */
 	if (phydev->interface != PHY_INTERFACE_MODE_SGMII) {
 		ret = ytphy_rgmii_clk_delay_config(phydev);
 		if (ret < 0)
-			goto err_restore_page;
+			return ret;
 	}
 
 	if (device_property_read_bool(dev, "motorcomm,auto-sleep-disabled")) {
@@ -1708,7 +1697,7 @@ static int yt8521_config_init(struct phy_device *phydev)
 		ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG,
 				       YT8521_ESC1R_SLEEP_SW, 0);
 		if (ret < 0)
-			goto err_restore_page;
+			return ret;
 	}
 
 	if (device_property_read_bool(dev, "motorcomm,keep-pll-enabled")) {
@@ -1716,13 +1705,32 @@ static int yt8521_config_init(struct phy_device *phydev)
 		ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
 				       YT8521_CGR_RX_CLK_EN, 0);
 		if (ret < 0)
-			goto err_restore_page;
+			return ret;
 	}
 
 	if (phy_interface_is_rgmii(phydev) &&
 	    phydev_id_compare(phydev, PHY_ID_YT8531S))
 		ret = yt8531_set_ds(phydev);
 
+	return ret;
+}
+
+/**
+ * yt8521_config_init() - called to initialize the PHY
+ * @phydev: a pointer to a &struct phy_device
+ *
+ * returns 0 or negative errno code
+ */
+static int yt8521_config_init(struct phy_device *phydev)
+{
+	int old_page, ret = 0;
+
+	old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
+	if (old_page < 0)
+		goto err_restore_page;
+
+	ret = __yt8521_config_init(phydev);
+
 err_restore_page:
 	return phy_restore_page(phydev, old_page, ret);
 }
-- 
2.55.0

[PATCH net-next 2/3] net: phy: motorcomm: Add a dedicated .config_init for YT8531S

[Maxime Chevallier]

The YT8531S PHY configuration logic is similar to the YT8521, but with
some extra steps for the RGMII configuration. In preparation for
improvements in the YT8531S configuration for the version found
integrated with the YT6801 PCIe NIC, let's split the logic out by
extending the YT8521 configuration sequence.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
---
 drivers/net/phy/motorcomm.c | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index 58e4d67b945f..36c229460a77 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c
@@ -1700,19 +1700,12 @@ static int __yt8521_config_init(struct phy_device *phydev)
 			return ret;
 	}
 
-	if (device_property_read_bool(dev, "motorcomm,keep-pll-enabled")) {
+	if (device_property_read_bool(dev, "motorcomm,keep-pll-enabled"))
 		/* enable RXC clock when no wire plug */
-		ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
-				       YT8521_CGR_RX_CLK_EN, 0);
-		if (ret < 0)
-			return ret;
-	}
+		return ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG,
+					YT8521_CGR_RX_CLK_EN, 0);
 
-	if (phy_interface_is_rgmii(phydev) &&
-	    phydev_id_compare(phydev, PHY_ID_YT8531S))
-		ret = yt8531_set_ds(phydev);
-
-	return ret;
+	return 0;
 }
 
 /**
@@ -1735,6 +1728,25 @@ static int yt8521_config_init(struct phy_device *phydev)
 	return phy_restore_page(phydev, old_page, ret);
 }
 
+static int yt8531s_config_init(struct phy_device *phydev)
+{
+	int old_page, ret = 0;
+
+	old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE);
+	if (old_page < 0)
+		goto err_restore_page;
+
+	ret = __yt8521_config_init(phydev);
+	if (ret)
+		goto err_restore_page;
+
+	if (phy_interface_is_rgmii(phydev))
+		ret = yt8531_set_ds(phydev);
+
+err_restore_page:
+	return phy_restore_page(phydev, old_page, ret);
+}
+
 static const unsigned long supported_trgs = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
 					     BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
 					     BIT(TRIGGER_NETDEV_LINK)        |
@@ -3143,7 +3155,7 @@ static struct phy_driver motorcomm_phy_drvs[] = {
 		.set_wol	= ytphy_set_wol,
 		.config_aneg	= yt8521_config_aneg,
 		.aneg_done	= yt8521_aneg_done,
-		.config_init	= yt8521_config_init,
+		.config_init	= yt8531s_config_init,
 		.read_status	= yt8521_read_status,
 		.soft_reset	= yt8521_soft_reset,
 		.suspend	= yt8521_suspend,
-- 
2.55.0

[PATCH net-next 3/3] net: phy: motorcomm: Enable analog frontend on YT8531S

[Maxime Chevallier]

The YT6801 PCIe NIC includes the dwmac-motorcomm IP for the MAC part, as
well as a YT8531S PHY, configured in GMII mode.

It seems this PHY requires the Analog Front-end (AFE) DAC clock to be
enabled for link to reliably establish, otherwise the link just doesn't
come up.

Let's enable it at config_init().

This logic has been extracted from the vendor driver provided by
Motorcomm.

It's really unclear if this is specific to the integrated version of
that PHY, and how this potentially interacts with the fiber mode this
PHY supports, so this configuration is only enabled when the interface
is GMII, i.e. the PHY is integrated.

With this, the PHY reliably establishes link and the YT6801 PCIe card
becomes fully functional.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
---
 drivers/net/phy/motorcomm.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index 36c229460a77..90a4f86f2758 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c
@@ -144,6 +144,11 @@
 #define YT8521_CLOCK_GATING_REG			0xC
 #define YT8521_CGR_RX_CLK_EN			BIT(12)
 
+/* Analog front-end control register 3 */
+#define YT8531S_EXT_AFE_CTRL3			0x12
+/* Analog front-end DAC clock enable */
+#define YT8531S_AFE_CTRL3_CLKDAC_AON		BIT(13)
+
 #define YT8521_EXTREG_SLEEP_CONTROL1_REG	0x27
 #define YT8521_ESC1R_SLEEP_SW			BIT(15)
 #define YT8521_ESC1R_PLLON_SLP			BIT(14)
@@ -1740,8 +1745,15 @@ static int yt8531s_config_init(struct phy_device *phydev)
 	if (ret)
 		goto err_restore_page;
 
-	if (phy_interface_is_rgmii(phydev))
+	if (phy_interface_is_rgmii(phydev)) {
 		ret = yt8531_set_ds(phydev);
+		if (ret)
+			goto err_restore_page;
+	}
+
+	if (phydev->interface == PHY_INTERFACE_MODE_GMII)
+		ret = ytphy_modify_ext(phydev, YT8531S_EXT_AFE_CTRL3,
+				       0, YT8531S_AFE_CTRL3_CLKDAC_AON);
 
 err_restore_page:
 	return phy_restore_page(phydev, old_page, ret);
-- 
2.55.0

Re: [PATCH net-next 3/3] net: phy: motorcomm: Enable analog frontend on YT8531S

[Paolo Abeni]

On 8/31/26 9:37 AM, Maxime Chevallier wrote:
> The YT6801 PCIe NIC includes the dwmac-motorcomm IP for the MAC part, as
> well as a YT8531S PHY, configured in GMII mode.
> 
> It seems this PHY requires the Analog Front-end (AFE) DAC clock to be
> enabled for link to reliably establish, otherwise the link just doesn't
> come up.
> 
> Let's enable it at config_init().
> 
> This logic has been extracted from the vendor driver provided by
> Motorcomm.
> 
> It's really unclear if this is specific to the integrated version of
> that PHY, and how this potentially interacts with the fiber mode this
> PHY supports, so this configuration is only enabled when the interface
> is GMII, i.e. the PHY is integrated.
> 
> With this, the PHY reliably establishes link and the YT6801 PCIe card
> becomes fully functional.
> 
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> ---
>  drivers/net/phy/motorcomm.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
> index 36c229460a77..90a4f86f2758 100644
> --- a/drivers/net/phy/motorcomm.c
> +++ b/drivers/net/phy/motorcomm.c
> @@ -144,6 +144,11 @@
>  #define YT8521_CLOCK_GATING_REG			0xC
>  #define YT8521_CGR_RX_CLK_EN			BIT(12)
>  
> +/* Analog front-end control register 3 */
> +#define YT8531S_EXT_AFE_CTRL3			0x12
> +/* Analog front-end DAC clock enable */
> +#define YT8531S_AFE_CTRL3_CLKDAC_AON		BIT(13)
> +
>  #define YT8521_EXTREG_SLEEP_CONTROL1_REG	0x27
>  #define YT8521_ESC1R_SLEEP_SW			BIT(15)
>  #define YT8521_ESC1R_PLLON_SLP			BIT(14)
> @@ -1740,8 +1745,15 @@ static int yt8531s_config_init(struct phy_device *phydev)
>  	if (ret)
>  		goto err_restore_page;
>  
> -	if (phy_interface_is_rgmii(phydev))
> +	if (phy_interface_is_rgmii(phydev)) {
>  		ret = yt8531_set_ds(phydev);
> +		if (ret)
> +			goto err_restore_page;
> +	}
> +
> +	if (phydev->interface == PHY_INTERFACE_MODE_GMII)
> +		ret = ytphy_modify_ext(phydev, YT8531S_EXT_AFE_CTRL3,
> +				       0, YT8531S_AFE_CTRL3_CLKDAC_AON);

Sashiko suspects this will not survive a suspend/resume:

https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260831073747.361482-1-maxime.chevallier%40bootlin.com

/P

Re: [PATCH net-next 3/3] net: phy: motorcomm: Enable analog frontend on YT8531S

[Maxime Chevallier]

On 9/1/26 15:59, Paolo Abeni wrote:
> On 8/31/26 9:37 AM, Maxime Chevallier wrote:
>> The YT6801 PCIe NIC includes the dwmac-motorcomm IP for the MAC part, as
>> well as a YT8531S PHY, configured in GMII mode.
>>
>> It seems this PHY requires the Analog Front-end (AFE) DAC clock to be
>> enabled for link to reliably establish, otherwise the link just doesn't
>> come up.
>>
>> Let's enable it at config_init().
>>
>> This logic has been extracted from the vendor driver provided by
>> Motorcomm.
>>
>> It's really unclear if this is specific to the integrated version of
>> that PHY, and how this potentially interacts with the fiber mode this
>> PHY supports, so this configuration is only enabled when the interface
>> is GMII, i.e. the PHY is integrated.
>>
>> With this, the PHY reliably establishes link and the YT6801 PCIe card
>> becomes fully functional.
>>
>> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
>> ---
>>  drivers/net/phy/motorcomm.c | 14 +++++++++++++-
>>  1 file changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
>> index 36c229460a77..90a4f86f2758 100644
>> --- a/drivers/net/phy/motorcomm.c
>> +++ b/drivers/net/phy/motorcomm.c
>> @@ -144,6 +144,11 @@
>>  #define YT8521_CLOCK_GATING_REG			0xC
>>  #define YT8521_CGR_RX_CLK_EN			BIT(12)
>>  
>> +/* Analog front-end control register 3 */
>> +#define YT8531S_EXT_AFE_CTRL3			0x12
>> +/* Analog front-end DAC clock enable */
>> +#define YT8531S_AFE_CTRL3_CLKDAC_AON		BIT(13)
>> +
>>  #define YT8521_EXTREG_SLEEP_CONTROL1_REG	0x27
>>  #define YT8521_ESC1R_SLEEP_SW			BIT(15)
>>  #define YT8521_ESC1R_PLLON_SLP			BIT(14)
>> @@ -1740,8 +1745,15 @@ static int yt8531s_config_init(struct phy_device *phydev)
>>  	if (ret)
>>  		goto err_restore_page;
>>  
>> -	if (phy_interface_is_rgmii(phydev))
>> +	if (phy_interface_is_rgmii(phydev)) {
>>  		ret = yt8531_set_ds(phydev);
>> +		if (ret)
>> +			goto err_restore_page;
>> +	}
>> +
>> +	if (phydev->interface == PHY_INTERFACE_MODE_GMII)
>> +		ret = ytphy_modify_ext(phydev, YT8531S_EXT_AFE_CTRL3,
>> +				       0, YT8531S_AFE_CTRL3_CLKDAC_AON);
> 
> Sashiko suspects this will not survive a suspend/resume:
> 
> https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260831073747.361482-1-maxime.chevallier%40bootlin.com

hmm sashiko may be right, worth adding right now as it seems there are
some discussions already on motorcomm suspend/resume issues, let me spin
a V2

Thanks !

Maxime

Re: [PATCH net-next 0/3] net: phy: motorcomm: Enable analog frontend DAC on yt8531S

[Yao Zi]

On Mon, Aug 31, 2026 at 09:37:42AM +0200, Maxime Chevallier wrote:
> In the process of getting more stmmac boards to run tests on, I've
> acquired a nice and inexpensive YT6801 PCIe card, that can do
> 10/100/1000BaseT. It uses stmmac's PCI variant dwmac-motorcomm, as well
> as an integrated Motorcomm PHY (the YT8531S).
> 
> However while testing the card, I had link-up maybe once every 10
> reboots, and no traffic whatsoever. Comparing with the out-of-tree
> driver provided by Motorcomm, it was found that some Analog Frontend DAC
> needs a clock to be enabled, and indeed it fixed the issue.

As a side note, this operation was added between v1.0.30 and v1.031 of
the vendor driver, and we haven't observed similar issues with the
current YT8531S driver, so maybe this is a silicon issue only present in
later revisions of the chip.

If interested, you could find v1.028, v1.029, and v1.031 of the YT6801
driver here[1]. And REG_MII_EXT_AFE_CONTROL_CLKDAC_AON_POS was
introduced in this commit[2].

> As I don't know much about this device, this series implements the DAC
> CLK configuration in the YT8531S driver only for the integrated version,
> that uses the GMII interface.
> 
> I split that into 3 commits, the first 2 are splitting-out the YT8521
> and YT8531S config_init(). The third commit adds the DAC configuration.
> 
> This was tested on YT6801, which now reliably reports link up.
> 
> Maxime Chevallier (3):
>   net: phy: motorcomm: Split yt8521_config_init() page management
>   net: phy: motorcomm: Add a dedicated .config_init for YT8531S
>   net: phy: motorcomm: Enable analog frontend on YT8531S
> 
>  drivers/net/phy/motorcomm.c | 76 ++++++++++++++++++++++++++-----------
>  1 file changed, 54 insertions(+), 22 deletions(-)
> 
> -- 
> 2.55.0
> 

Regards,
Yao Zi

[1]: https://github.com/deepin-community/kernel/blob/linux-6.6.y/drivers/net/ethernet/motorcomm/yt6801/
[2]: https://github.com/deepin-community/kernel/commit/721c505713d104fe48a817e703936dfe583b8ae4

Re: [PATCH net-next 3/3] net: phy: motorcomm: Enable analog frontend on YT8531S

[Yao Zi]

On Tue, Sep 01, 2026 at 04:21:36PM +0200, Maxime Chevallier wrote:
> 
> 
> On 9/1/26 15:59, Paolo Abeni wrote:
> > On 8/31/26 9:37 AM, Maxime Chevallier wrote:
> >> The YT6801 PCIe NIC includes the dwmac-motorcomm IP for the MAC part, as
> >> well as a YT8531S PHY, configured in GMII mode.
> >>
> >> It seems this PHY requires the Analog Front-end (AFE) DAC clock to be
> >> enabled for link to reliably establish, otherwise the link just doesn't
> >> come up.
> >>
> >> Let's enable it at config_init().
> >>
> >> This logic has been extracted from the vendor driver provided by
> >> Motorcomm.
> >>
> >> It's really unclear if this is specific to the integrated version of
> >> that PHY, and how this potentially interacts with the fiber mode this
> >> PHY supports, so this configuration is only enabled when the interface
> >> is GMII, i.e. the PHY is integrated.
> >>
> >> With this, the PHY reliably establishes link and the YT6801 PCIe card
> >> becomes fully functional.
> >>
> >> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> >> ---
> >>  drivers/net/phy/motorcomm.c | 14 +++++++++++++-
> >>  1 file changed, 13 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
> >> index 36c229460a77..90a4f86f2758 100644
> >> --- a/drivers/net/phy/motorcomm.c
> >> +++ b/drivers/net/phy/motorcomm.c
> >> @@ -144,6 +144,11 @@
> >>  #define YT8521_CLOCK_GATING_REG			0xC
> >>  #define YT8521_CGR_RX_CLK_EN			BIT(12)
> >>  
> >> +/* Analog front-end control register 3 */
> >> +#define YT8531S_EXT_AFE_CTRL3			0x12
> >> +/* Analog front-end DAC clock enable */
> >> +#define YT8531S_AFE_CTRL3_CLKDAC_AON		BIT(13)
> >> +
> >>  #define YT8521_EXTREG_SLEEP_CONTROL1_REG	0x27
> >>  #define YT8521_ESC1R_SLEEP_SW			BIT(15)
> >>  #define YT8521_ESC1R_PLLON_SLP			BIT(14)
> >> @@ -1740,8 +1745,15 @@ static int yt8531s_config_init(struct phy_device *phydev)
> >>  	if (ret)
> >>  		goto err_restore_page;
> >>  
> >> -	if (phy_interface_is_rgmii(phydev))
> >> +	if (phy_interface_is_rgmii(phydev)) {
> >>  		ret = yt8531_set_ds(phydev);
> >> +		if (ret)
> >> +			goto err_restore_page;
> >> +	}
> >> +
> >> +	if (phydev->interface == PHY_INTERFACE_MODE_GMII)
> >> +		ret = ytphy_modify_ext(phydev, YT8531S_EXT_AFE_CTRL3,
> >> +				       0, YT8531S_AFE_CTRL3_CLKDAC_AON);
> > 
> > Sashiko suspects this will not survive a suspend/resume:
> > 
> > https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260831073747.361482-1-maxime.chevallier%40bootlin.com
> 
> hmm sashiko may be right, worth adding right now as it seems there are
> some discussions already on motorcomm suspend/resume issues, let me spin
> a V2
> 
> Thanks !

Yes, suspend/resume already works for some time on devices unaffected
by the issue under discussion. It looks good to me apart from this.
I'll call some guys to test for regressions on devices proven to work
before.

> Maxime
> 

Best regards,
Yao Zi