* [PATCH V4 4/4] arm64: dts: freescale: Add chargebyte Charge Control Y
2026-09-03 8:04 [PATCH V4 0/4] arm64: dts: freescale: Add chargebyte Charge Control Y Stefan Wahren
` (2 preceding siblings ...)
2026-09-03 8:04 ` [PATCH V4 3/4] dt-bindings: phy: ti,tcan104x-can: Document Microchip MCP2542 Stefan Wahren
@ 2026-09-03 8:04 ` Stefan Wahren
3 siblings, 0 replies; 5+ messages in thread
From: Stefan Wahren @ 2026-09-03 8:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Marc Kleine-Budde,
Vincent Mailhol, Vinod Koul, Neil Armstrong, Frank Li,
Pengutronix Kernel Team, Fabio Estevam, Aswath Govindraju
Cc: Christoph Stoidner, linux-kernel, devicetree, linux-can,
linux-phy, imx, linux-arm-kernel, Stefan Wahren, Martin Lukas,
Michael Heimpold
This adds the support for chargebyte Charge Control Y, which is
an Electrical Vehicle Supply Equipment (EVSE) for MCS (Megawatt
Charging System) charging stations (according to IEC 61851-23-1).
chargebyte Charge Control Y uses phyCORE-i.MX 93 ARM
- NXP i.MX93 1.7 GHz
- 1 GB DDR4 RAM
- up to 8 GB eMMC
- 2x 100 MBit/s Ethernet interfaces
- 10BASE-T1S Ethernet for MCS communication
- CAN interface
- separate safety chip
- TPM chip
- power buffered RTC
Co-developed-by: Martin Lukas <martin.lukas@chargebyte.com>
Signed-off-by: Martin Lukas <martin.lukas@chargebyte.com>
Co-developed-by: Michael Heimpold <michael.heimpold@chargebyte.com>
Signed-off-by: Michael Heimpold <michael.heimpold@chargebyte.com>
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx93-charge-control-y.dts | 439 ++++++++++++++++++
.../boot/dts/freescale/imx93-phycore-som.dtsi | 2 +-
3 files changed, 441 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-charge-control-y.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 95ae85ab4adf..8817992218a5 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -652,6 +652,7 @@ imx93-11x11-frdm-pixpaper-dtbs += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm-pixpaper.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx93-charge-control-y.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx93-charge-control-y.dts b/arch/arm64/boot/dts/freescale/imx93-charge-control-y.dts
new file mode 100644
index 000000000000..ba240f528f9b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-charge-control-y.dts
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2025-2026 chargebyte GmbH
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx93-phycore-som.dtsi"
+
+/ {
+ model = "chargebyte Charge Control Y";
+ compatible = "chargebyte,imx93-charge-control-y", "phytec,imx93-phycore-som", "fsl,imx93";
+
+ aliases {
+ ethernet0 = &fec;
+ ethernet1 = &lan8651;
+ ethernet2 = &eqos;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ rtc0 = &rv3028;
+ rtc1 = &bbnsm_rtc;
+ serial0 = &lpuart1;
+ serial1 = &lpuart2;
+ serial2 = &lpuart3;
+ serial3 = &lpuart4;
+ serial4 = &lpuart5;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ // Heartbeat LED of phyCore is not populated
+ /delete-node/ leds;
+
+ flexcan1_tc: can-phy0 {
+ compatible = "microchip,mcp2542", "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <1000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "VCC_SD";
+ };
+
+ user_leds: user-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_user_leds>;
+
+ led_user_green: led-user-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_BOOT;
+ gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "timer";
+ };
+
+ led_user_red: led-user-red {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_SD;
+ gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ };
+ };
+};
+
+&eeprom0 {
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Wired ethernet interface */
+ eth1_mac_address: base-mac-address@100 {
+ compatible = "mac-base";
+ reg = <0x100 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ /* MCS ethernet interface */
+ eth2_mac_address: base-mac-address@108 {
+ compatible = "mac-base";
+ reg = <0x108 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+};
+
+/* Ethernet 2 */
+&eqos {
+ phy-mode = "rmii";
+ phy-handle = <ðphy2>;
+ assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
+ <&clk IMX93_CLK_ENET>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <100000000>, <50000000>;
+
+ nvmem-cells = <ð1_mac_address 0>;
+ nvmem-cell-names = "mac-address";
+
+ status = "okay";
+};
+
+/* Ethernet 1 */
+&fec {
+ /* Since MDIO bus is handled by FEC, all PHY strap pins and
+ * reference clock must be initialized at the same time.
+ */
+ pinctrl-0 = <&pinctrl_fec &pinctrl_eqos &pinctrl_eqos_strap>;
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ phys = <&flexcan1_tc>;
+ status = "okay";
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_lan8651_rst>;
+ gpio-line-names = "", "", "", "X_nRST_LAN", "",
+ "", "LPUART2_RX", "LPUART2_TX", "CAN1_TX", "CAN1_RX",
+ "", "SPI_TPM_nCS0", "", "", "",
+ "";
+};
+
+&gpio2 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "X_LAN_nIRQ", "X_LAN_nCS", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "GREEN_LED",
+ "RED_LED", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names = "SD2_nCD", "", "", "", "",
+ "", "", "SD2_nRESET", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "SOM_EMMC_nRESET", "", "", "", "",
+ "", "", "", "", "",
+ "", "";
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio4>;
+ gpio-line-names = "", "", "X_RTC_nINT", "", "",
+ "", "", "", "", "",
+ "", "", "SAFETY_BOOTMODE_SET", "ENET1_RST", "",
+ "", "", "", "", "",
+ "", "SOM_EEPROM_WP", "", "SOM_PHY_RESET", "",
+ "", "", "PMIC_IRQ_B", "nSAFETY_RESET_INT", "SPI_TPM_nINT0";
+};
+
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
+ scl-gpios = <&gpio1 00 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 01 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ rv3028: rtc@52 {
+ compatible = "microcrystal,rv3028";
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio4>;
+ wakeup-source;
+ trickle-resistor-ohms = <3000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ reg = <0x52>;
+ };
+};
+
+&lpspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi1>;
+ num-cs = <1>;
+ cs-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+/* MCS Ethernet SPI */
+&lpspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi3>;
+ num-cs = <1>;
+ cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ lan8651: ethernet@0 {
+ compatible = "microchip,lan8651", "microchip,lan8650";
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <25000000>;
+
+ nvmem-cells = <ð2_mac_address 0>;
+ nvmem-cell-names = "mac-address";
+
+ /*
+ * Since GPIO reset management for the LAN8651 has not yet been
+ * implemented, X_nRST_LAN should be retained as a GPIO in
+ * userspace for the rare case that a reset via SPI does not work.
+ */
+ };
+};
+
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&lpuart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+/* Ethernet 2 PHY */
+&mdio {
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ compatible = "ethernet-phy-id2000.a140";
+ clocks = <&clk IMX93_CLK_ENET_REF_PHY>;
+ reset-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ reset-assert-us = <30>;
+ reset-deassert-us = <50000>;
+ };
+};
+
+/* SD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ disable-wp;
+ no-sdio;
+ no-mmc;
+ status = "okay";
+};
+
+&iomuxc {
+
+ // Heartbeat LED of phyCore is not populated
+ /delete-node/ pinctrl_leds;
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000057e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x50e
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e
+ >;
+ };
+
+ pinctrl_eqos_strap: eqosstrapgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x17e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x17e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x17e
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x17e
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
+ MX93_PAD_PDM_CLK__CAN1_TX 0x1382
+ >;
+ };
+
+ pinctrl_gpio1: gpio1grp {
+ fsl,pins = <
+ MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x382
+ >;
+ };
+
+ pinctrl_gpio4: gpio4grp {
+ fsl,pins = <
+ MX93_PAD_ENET1_TXC__GPIO4_IO07 0x382
+ MX93_PAD_ENET1_RD2__GPIO4_IO12 0x39e
+ MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x39e
+ MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
+ >;
+ };
+
+ /* X_nRST_LAN is wired to a pull resistor, so it's not floating */
+ pinctrl_lan8651_rst: lan8651rstgrp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b86
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b86
+ >;
+ };
+
+ pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__GPIO1_IO00 0x40000b9e
+ MX93_PAD_I2C1_SDA__GPIO1_IO01 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpspi1: lpspi1grp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x186
+ MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x186
+ MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x186
+ MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x186
+ MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x186
+ >;
+ };
+
+ /* PinCtrl MCS LAN SPI */
+ pinctrl_lpspi3: lpspi3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO07__GPIO2_IO07 0x186
+ MX93_PAD_GPIO_IO08__GPIO2_IO08 0x186
+ MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x186
+ MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x186
+ MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x186
+ >;
+ };
+
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e
+ MX93_PAD_GPIO_IO14__LPUART3_TX 0x30e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_cd: usdhc2cdgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_default: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x118e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_user_leds: userledgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO24__GPIO2_IO24 0x31e
+ MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index 325e465d0056..489ed3f7fb61 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
@@ -201,7 +201,7 @@ ldo5: LDO5 {
};
/* EEPROM */
- eeprom@50 {
+ eeprom0: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
--
2.43.0
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