* [PATCH] arm64: dts: renesas: r8a779g0: Add MSI cells to GICv3 ITS
@ 2026-09-08 16:22 Marek Vasut
2026-09-09 15:33 ` Geert Uytterhoeven
0 siblings, 1 reply; 2+ messages in thread
From: Marek Vasut @ 2026-09-08 16:22 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Rob Herring, devicetree, linux-kernel,
linux-renesas-soc
Fill in missing #msi-cells = <1> into the GIC ITS node, update
its-parent phandles and fill in 1:1 msi-map .
Fixes: 7fe73a3a3f2c ("arm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodes")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index ea6495261c2bb..ca17bfbf83fdf 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -809,7 +809,8 @@ pciec0: pcie@e65d0000 {
resets = <&cpg 624>;
reset-names = "pwr";
max-link-speed = <4>;
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
+ msi-map = <0x0 &its 0x0 0x10000>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
@@ -857,7 +858,8 @@ pciec1: pcie@e65d8000 {
resets = <&cpg 625>;
reset-names = "pwr";
max-link-speed = <4>;
- msi-parent = <&its>;
+ msi-parent = <&its 0>;
+ msi-map = <0x0 &its 0x0 0x10000>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
@@ -2165,6 +2167,7 @@ its: msi-controller@40000 {
reg = <0x0 0x40000 0x0 0x20000>;
dma-noncoherent;
msi-controller;
+ #msi-cells = <1>;
};
};
--
2.53.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a779g0: Add MSI cells to GICv3 ITS
2026-09-08 16:22 [PATCH] arm64: dts: renesas: r8a779g0: Add MSI cells to GICv3 ITS Marek Vasut
@ 2026-09-09 15:33 ` Geert Uytterhoeven
0 siblings, 0 replies; 2+ messages in thread
From: Geert Uytterhoeven @ 2026-09-09 15:33 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Rob Herring, devicetree, linux-kernel,
linux-renesas-soc
On Tue, 8 Sept 2026 at 18:23, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> Fill in missing #msi-cells = <1> into the GIC ITS node, update
> its-parent phandles and fill in 1:1 msi-map .
>
> Fixes: 7fe73a3a3f2c ("arm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodes")
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
As the original commit is not yet in soc, I will fold this fix into
the original while applying.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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