* [PATCH v8 1/2] PCI: Configure Root Port MPS during host probing
2026-09-11 13:21 [PATCH v8 0/2] PCI: Configure Root Port MPS during host probing Hans Zhang
@ 2026-09-11 13:21 ` Hans Zhang
2026-09-11 13:21 ` [PATCH v8 2/2] PCI: dwc: Remove redundant MPS configuration Hans Zhang
1 sibling, 0 replies; 3+ messages in thread
From: Hans Zhang @ 2026-09-11 13:21 UTC (permalink / raw)
To: lpieralisi, kwilczynski, bhelgaas, helgaas, heiko, mani, yue.wang
Cc: pali, neil.armstrong, robh, jingoohan1, khilman, jbrunet,
martin.blumenstingl, cassel, linux-pci, linux-kernel,
linux-arm-kernel, linux-amlogic, linux-rockchip, Hans Zhang,
Mahesh Vaidya, Ricardo Pardini, Shawn Lin
Current PCIe initialization logic may leave Root Ports operating with
non-optimal Maximum Payload Size (MPS) settings. The existing code in
pci_configure_mps() returns early for devices without an upstream bridge
which includes Root Ports, so their MPS values remain at firmware
defaults. This fails to utilize the controller's full capabilities,
leading to suboptimal data transfer efficiency across the PCIe hierarchy.
With this patch, during the host controller probing phase:
- When PCIe bus tuning is enabled (not PCIE_BUS_TUNE_OFF) and not
PCIE_BUS_PEER2PEER (which requires the default 128 bytes for optimal
peer-to-peer operation), and
- The device is a Root Port, the Root Port's MPS is set to its maximum
supported value.
Note that this initial maximum MPS setting may be reduced later, during
downstream device enumeration, if any downstream device does not support
the Root Port's maximum MPS.
This change ensures Root Ports are initialized to their maximum MPS before
downstream devices negotiate MPS, while maintaining backward compatibility
via the PCIE_BUS_TUNE_OFF check and not interfering with the
PCIE_BUS_PEER2PEER strategy.
Suggested-by: Niklas Cassel <cassel@kernel.org>
Suggested-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Hans Zhang <18255117159@163.com>
Tested-by: Mahesh Vaidya <mahesh.vaidya@altera.com>
Tested-by: Ricardo Pardini <ricardo@pardini.net> # on Odroid-HC4
Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/pci/probe.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 27008e2ea5af..dc4747858918 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2229,6 +2229,18 @@ static void pci_configure_mps(struct pci_dev *dev)
return;
}
+ /*
+ * Unless MPS strategy is PCIE_BUS_TUNE_OFF (don't touch MPS at all) or
+ * PCIE_BUS_PEER2PEER (use minimum MPS for peer-to-peer), set Root Ports'
+ * MPS to their maximum supported value. Depending on the MPS strategy
+ * and MPSS of downstream devices, a Root Port's MPS may be reduced
+ * later during device enumeration.
+ */
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT &&
+ pcie_bus_config != PCIE_BUS_TUNE_OFF &&
+ pcie_bus_config != PCIE_BUS_PEER2PEER)
+ pcie_set_mps(dev, 128 << dev->pcie_mpss);
+
if (!bridge || !pci_is_pcie(bridge))
return;
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v8 2/2] PCI: dwc: Remove redundant MPS configuration
2026-09-11 13:21 [PATCH v8 0/2] PCI: Configure Root Port MPS during host probing Hans Zhang
2026-09-11 13:21 ` [PATCH v8 1/2] " Hans Zhang
@ 2026-09-11 13:21 ` Hans Zhang
1 sibling, 0 replies; 3+ messages in thread
From: Hans Zhang @ 2026-09-11 13:21 UTC (permalink / raw)
To: lpieralisi, kwilczynski, bhelgaas, helgaas, heiko, mani, yue.wang
Cc: pali, neil.armstrong, robh, jingoohan1, khilman, jbrunet,
martin.blumenstingl, cassel, linux-pci, linux-kernel,
linux-arm-kernel, linux-amlogic, linux-rockchip, Hans Zhang
The Meson PCIe controller driver manually configures maximum payload
size (MPS) through meson_set_max_payload, duplicating functionality now
centralized in the PCI core. Deprecating redundant code simplifies the
driver and aligns it with the consolidated MPS management strategy,
improving long-term maintainability.
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/controller/dwc/pci-meson.c | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
index 8559d132dcde..8c176f78953e 100644
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -273,22 +273,6 @@ static int meson_size_to_payload(struct meson_pcie *mp, int size)
return fls(size) - 8;
}
-static void meson_set_max_payload(struct meson_pcie *mp, int size)
-{
- struct dw_pcie *pci = &mp->pci;
- u32 val;
- u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
- int max_payload_size = meson_size_to_payload(mp, size);
-
- val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
- val &= ~PCI_EXP_DEVCTL_PAYLOAD;
- dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
-
- val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
- val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
- dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
-}
-
static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
{
struct dw_pcie *pci = &mp->pci;
@@ -363,7 +347,6 @@ static int meson_pcie_host_init(struct dw_pcie_rp *pp)
pp->bridge->ops = &meson_pci_ops;
- meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread