[PATCH v3 0/4] Add SRAM Nodes for VPU

[PATCH v3 0/4] Add SRAM Nodes for VPU

[Brandon Brnich]

Hello All,

This series is responsible for adding the SRAM nodes for the Wave5 VPU to
use. First patch is responsible for carving out the SRAM pool from
main_navss that the VPU on J721s2 will then reference.

The last 2 patches use the existing oc_sram pool already found in the
relevant device trees.


Changes since v2:

  - Removed j784s4 since there are two vpu instances, need to find
    another SRAM pool so both can get full benefit of B/W savings

Changes since v1:

  - properly updates the nodename in the first two patches to pass
    dtbs_check. 

Best,
Brandon

Brandon Brnich (4):
  arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss
  arm64: dts: ti: k3-j721s2-main: Assign SRAM to VPU node
  arm64: dts: ti: k3-am62a-main: Assign SRAM to VPU node
  arm64: dts: ti: k3-am62p-j722s-common-main: Assign SRAM to VPU node

 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi              | 1 +
 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 1 +
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi             | 9 +++++++++
 3 files changed, 11 insertions(+)

-- 
2.43.0

[PATCH v3 1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss

[Brandon Brnich]

The NavigatorSS (NAVSS) address space contains a 64 KiB on-chip SRAM
region at its base address. Add an mmio-sram node to expose this region
to consumers via the generic SRAM allocator API.

Signed-off-by: Brandon Brnich <b-brnich@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 1228ac5711bf0..1fd173a68c0b2 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -784,6 +784,14 @@ main_navss: bus@30000000 {
 		dma-coherent;
 		dma-ranges;
 
+		main_navss_sram: sram@30000000 {
+			compatible = "mmio-sram";
+			reg = <0x00 0x30000000 0x00 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x30000000 0x10000>;
+		};
+
 		main_navss_intr: interrupt-controller@310e0000 {
 			compatible = "ti,sci-intr";
 			reg = <0x00 0x310e0000 0x00 0x4000>;
-- 
2.43.0

[PATCH v3 2/4] arm64: dts: ti: k3-j721s2-main: Assign SRAM to VPU node

[Brandon Brnich]

The Wave5 VPU supports connecting to on-chip SRAM through its secondary
AXI interface. This allows temporal buffers to be stored on a per-stream
basis, reducing DDR memory traffic.

Signed-off-by: Brandon Brnich <b-brnich@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 1fd173a68c0b2..233aedcbf2ec3 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -716,6 +716,7 @@ vpu: video-codec@4210000 {
 		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&k3_clks 179 2>;
 		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+		sram = <&main_navss_sram>;
 	};
 
 	main_sdhci0: mmc@4f80000 {
-- 
2.43.0

[PATCH v3 3/4] arm64: dts: ti: k3-am62a-main: Assign SRAM to VPU node

[Brandon Brnich]

The Wave5 VPU supports connecting to on-chip SRAM through its secondary
AXI interface. This allows temporal buffers to be stored on a per-stream
basis, reducing DDR memory traffic.

Signed-off-by: Brandon Brnich <b-brnich@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
index 9e5b75a4e88e2..92dd1b96cef4d 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
@@ -1149,6 +1149,7 @@ vpu: video-codec@30210000 {
 		reg = <0x00 0x30210000 0x00 0x10000>;
 		clocks = <&k3_clks 204 2>;
 		power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
+		sram = <&oc_sram>;
 	};
 
 	c7x_0: dsp@7e000000 {
-- 
2.43.0

[PATCH v3 4/4] arm64: dts: ti: k3-am62p-j722s-common-main: Assign SRAM to VPU node

[Brandon Brnich]

The Wave5 VPU supports connecting to on-chip SRAM through its secondary
AXI interface. This allows temporal buffers to be stored on a per-stream
basis, reducing DDR memory traffic.

Signed-off-by: Brandon Brnich <b-brnich@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index f130c7cb998d7..61e3588bbfdc5 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -1117,6 +1117,7 @@ vpu: video-codec@30210000 {
 		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&k3_clks 204 2>;
 		power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
+		sram = <&oc_sram>;
 	};
 
 	hsm: remoteproc@43c00000 {
-- 
2.43.0

Re: [PATCH v3 0/4] Add SRAM Nodes for VPU

[Nishanth Menon]

Hi Brandon Brnich,

On Mon, 21 Sep 2026 13:48:46 -0500, Brandon Brnich wrote:
> This series is responsible for adding the SRAM nodes for the Wave5 VPU to
> use. First patch is responsible for carving out the SRAM pool from
> main_navss that the VPU on J721s2 will then reference.
> 
> The last 2 patches use the existing oc_sram pool already found in the
> relevant device trees.
> 
> [...]

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/4] arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss
      commit: b4824bac766e1696a31c54c14541b65e33eb683f
[2/4] arm64: dts: ti: k3-j721s2-main: Assign SRAM to VPU node
      commit: 86ab93a198114653faf0fef11a88d4a240f5adf4
[3/4] arm64: dts: ti: k3-am62a-main: Assign SRAM to VPU node
      commit: 0bd8ecba297bd50fe5b154a96f6eaf0233b28dd3
[4/4] arm64: dts: ti: k3-am62p-j722s-common-main: Assign SRAM to VPU node
      commit: 330236fda4fd7a63e3bf9d9ce1b7ce227ddb8f1c

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
-- 
Regards,
Nishanth Menon
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