[PATCH v2] ARM: errata: document Cortex-A9 from r2 as affected by erratum 754322

[PATCH v2] ARM: errata: document Cortex-A9 from r2 as affected by erratum 754322

[Qingfang Deng]

The Cortex-A9 r4 Software Developers Errata Notice (ARM UAN 0009D),
section 2.3.3, lists erratum 754322 as open (unresolved) and affecting
all r2, r3 and r4 revisions. The Kconfig help text currently mentions
only r2 and r3.

Update the help text to include all revisions from r2p0 so that users
configuring Cortex-A9 r4 systems know that the workaround also applies
to them.

Link: https://documentation-service.arm.com/static/608118675e70d934bc69f143
Signed-off-by: Qingfang Deng <qingfang.deng@linux.dev>
---
v2:
 Drop fixes tag, and mention that it affects all revisions from r2.

v1: https://lore.kernel.org/linux-arm-kernel/20260920032926.452884-1-qingfang.deng@linux.dev/
---
 arch/arm/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0cc289a7184a..ec0c6191161f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -707,8 +707,8 @@ config ARM_ERRATA_754322
 	bool "ARM errata: possible faulty MMU translations following an ASID switch"
 	depends on CPU_V7
 	help
-	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
-	  r3p*) erratum. A speculative memory access may cause a page table walk
+	  This option enables the workaround for the 754322 Cortex-A9 (r2p* and
+	  later) erratum. A speculative memory access may cause a page table walk
 	  which starts prior to an ASID switch but completes afterwards. This
 	  can populate the micro-TLB with a stale entry which may be hit with
 	  the new ASID. This workaround places two dsb instructions in the mm
-- 
2.43.0