* [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support
@ 2026-09-28 19:44 Christian Marangi
2026-09-28 19:45 ` [PATCH net-next v24 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Christian Marangi
` (8 more replies)
0 siblings, 9 replies; 17+ messages in thread
From: Christian Marangi @ 2026-09-28 19:44 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
This series add the initial support for the Airoha AN8855 Switch.
It's a 5 port Gigabit Switch with SGMII/HSGMII upstream port.
This is starting to get in the wild and there are already some router
having this switch chip.
MT7530 is generalized with reg fields to a shared library to
reduce code duplication and reuse all the logic for AN8855.
There is this special thing where PHY needs to be calibrated with values
from the switch efuse. (the thing have a whole cpu timer and MCU)
Given the double usage of PHY and Switch accessor, a special handling
is used with registering a mdio-regmap bus for each internal PHY.
From v8 Driver is now evaluated with Kernel selftest scripts for DSA:
Additional info about the test bridge_vlan_aware.sh.
It was discovered that the Airoha Switch (and probably the Mediatek one
that produce the same test results) hardcode checking for 802.1ad when
the port is configured in VLAN-Aware mode (aka Security mode).
In such mode, both 802.1q and 802.1ad TPID are checked, hence the
bridge_vlan_aware.sh test fails as packets with 802.1ad TPID are rejected
(in the case where a wrong VLAN ID is forwarded)
This was confirmed by Airoha and multiple try were done to try to
workaround this problem. No solution were found to this as ACL mechanism
can't work on receiving packets and the Switch doesn't support turning off
this.
The current driver is in use from 4 month on OpenWrt with all kind of
scenario confirming working in VLAN bridge. By tweaking the
bridge_vlan_aware.sh test with setting the TPID to 0x9100, the test
correctly pass as packets gets classified as untagged and the default PVID
applied. It's also confirmed that switch correctly parse the 802.1ad tag
and make the packet pass only when allowed by VLAN table rules.
Output local_termination.sh
TEST: lan2: Unicast IPv4 to primary MAC address [ OK ]
TEST: lan2: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: lan2: Unicast IPv4 to unknown MAC address [ OK ]
TEST: lan2: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: lan2: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: lan2: Multicast IPv4 to joined group [ OK ]
TEST: lan2: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: lan2: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: lan2: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: lan2: Multicast IPv6 to joined group [ OK ]
TEST: lan2: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: lan2: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: lan2: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: lan2: 1588v2 over L2 transport, Sync [ OK ]
TEST: lan2: 1588v2 over L2 transport, Follow-Up [ OK ]
TEST: lan2: 1588v2 over L2 transport, Peer Delay Request [ OK ]
TEST: lan2: 1588v2 over IPv4, Sync [FAIL]
reception failed
TEST: lan2: 1588v2 over IPv4, Follow-Up [FAIL]
reception failed
TEST: lan2: 1588v2 over IPv4, Peer Delay Request [FAIL]
reception failed
TEST: lan2: 1588v2 over IPv6, Sync [FAIL]
reception failed
TEST: lan2: 1588v2 over IPv6, Follow-Up [FAIL]
reception failed
TEST: lan2: 1588v2 over IPv6, Peer Delay Request [FAIL]
reception failed
TEST: vlan_filtering=0 bridge: Unicast IPv4 to primary MAC address [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv4 to joined group [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: vlan_filtering=0 bridge: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv6 to joined group [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: vlan_filtering=0 bridge: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to primary MAC address [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv4 to joined group [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: vlan_filtering=1 bridge: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv6 to joined group [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: vlan_filtering=1 bridge: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: VLAN upper: Unicast IPv4 to primary MAC address [ OK ]
TEST: VLAN upper: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: VLAN upper: Unicast IPv4 to unknown MAC address [ OK ]
TEST: VLAN upper: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: VLAN upper: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: VLAN upper: Multicast IPv4 to joined group [ OK ]
TEST: VLAN upper: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN upper: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: VLAN upper: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: VLAN upper: Multicast IPv6 to joined group [ OK ]
TEST: VLAN upper: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN upper: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: VLAN upper: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: VLAN upper: 1588v2 over L2 transport, Sync [ OK ]
TEST: VLAN upper: 1588v2 over L2 transport, Follow-Up [FAIL]
reception failed
TEST: VLAN upper: 1588v2 over L2 transport, Peer Delay Request [ OK ]
TEST: VLAN upper: 1588v2 over IPv4, Sync [FAIL]
reception failed
;TEST: VLAN upper: 1588v2 over IPv4, Follow-Up [FAIL]
reception failed
TEST: VLAN upper: 1588v2 over IPv4, Peer Delay Request [FAIL]
reception failed
TEST: VLAN upper: 1588v2 over IPv6, Sync [FAIL]
reception failed
TEST: VLAN upper: 1588v2 over IPv6, Follow-Up [FAIL]
reception failed
TEST: VLAN upper: 1588v2 over IPv6, Peer Delay Request [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to primary MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to unknown MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to joined group [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to joined group [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over L2 transport, Sync [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over L2 transport, Follow-Up [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over L2 transport, Peer Delay Request [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv4, Sync [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv4, Follow-Up [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv4, Peer Delay Request [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv6, Sync [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv6, Follow-Up [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv6, Peer Delay Request [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to primary MAC address [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to joined group [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to joined group [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over L2 transport, Sync [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over L2 transport, Follow-Up [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over L2 transport, Peer Delay Request [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv4, Sync [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv4, Follow-Up [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv4, Peer Delay Request [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv6, Sync [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv6, Follow-Up [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv6, Peer Delay Request [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to primary MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to joined group [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to joined group [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to primary MAC address [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to joined group [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to joined group [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to unknown group, allmulti [ OK ]
Output bridge_vlan_unaware.sh
TEST: ping [ OK ]
TEST: ping6 [ OK ]
TEST: FDB learning [ OK ]
TEST: Unknown unicast flood [ OK ]
TEST: Unregistered multicast flood [ OK ]
Output bridge_vlan_aware.sh
TEST: ping [ OK ]
TEST: ping6 [ OK ]
TEST: FDB learning [ OK ]
TEST: Unknown unicast flood [ OK ]
TEST: Unregistered multicast flood [ OK ]
INFO: Add and delete a VLAN on bridge port lan2
TEST: ping [ OK ]
TEST: ping6 [ OK ]
TEST: Externally learned FDB entry - ageing & roaming [ OK ]
TEST: FDB entry in PVID for VLAN-tagged with other TPID [FAIL]
FDB entry was not learned when it should
TEST: Reception of VLAN with other TPID as untagged [FAIL]
Packet was not forwarded when it should
TEST: Reception of VLAN with other TPID as untagged (no PVID) [FAIL]
Packet was forwarded when should not
Changes v24:
- Add review tag by Andrew
- Fix missing multicast from generalize patch
- Add patch to move mediatek drivers to dedicated driver
- Zero out saved timer on LPI disable
- Correctl check regfiled on FDB read
- Fix MFD leaked of node
Changes v23:
- Add review by tag for DT patch
- Fix MFD fwnode handle release
- Better handle LPI handling for AN8855
- Add additional kconfig for AN8855
- Use shorter name for virtual phy bus
Changes v22:
- Improve MFD lock handling for phy bus
- Prevent devm crash on removal for MFD driver
- Address VAWD bug reported by bot
- Fix wrong msb for MIB for AN8855 driver
- Better handle kconfig dependency
- Read tx_lpi under lock
Changes v21:
- Rebase on top of net-next
- Drop megred patch from Daniel
- Address suggestion reported by bot for MFD driver
- Drop reset for MFD driver
- Reset FDB and VLAN data on writing
- Fix not correct PCR matrix in port enable
- Add ID_EN7528 fields
- Fix MAC address learning SA_DIS
- Fix MAC address FDB read swapped
- Fix mib reset logic
- Fix AN8855 missing regfiled
- Fix AN8855 ethtool stats access
- Improve tx lpi timer for AN8855
- Improve MFD Documentation patch
Changes v20:
- Address all the typo pointed out by bot
- Make documentation schema more consistent
- Address some concern for the mfd driver from bot
- Fix some conversion problem for the generalization patch
Changes v19:
- Rebase on top of net-next
- Rework with shared function from mt7530 driver
- Add dependency for mt7530 lock
- Fix some define typo for AN8855
Changes v18:
- Fix configurting typo
- Init ret in MFD driver
Changes v17:
- Drop nvmem patch (subset merged and present in linux-next)
- Fix wrong Documentation patch for MFD
- Address reviews for MFD driver
- Rework MTK tag to slipt for Airoha name
Changes v16:
- Rebase on top of net-next
- Drop PBUS implementation (Airoha said that it's not OK to use it)
- Convert to simple mdio-regmap and split regmap
- Fix typo for some define (AND8855 -> AN8855)
Changes v15:
- Rebase on top of net-next
- Drop regmap MDIO patch (in favor of PBUS)
- Implement MDIO PBUS and rework MDIO driver/MFD
- Reimplement EEE support
- Add some check for regmap from MFD
- Move to single regmap and add comments with all findings
Changes v14:
- Move MAITAINERS entry to dedicated commit (make it easier for cross
subsystem merge)
- Pack variables in trap function
- Add additional patch for reported difference from MTK tag
Changes v13:
- Reimplement tx_lpi OPs
- Rework mdio-regmap to internally encode/decode address
- Fix error in Documentation
- Drop ext-surge property (assume calibration with declared nvmem cell)
- Fix comments from Lee on MFD driver
- Improve print error and drop extra space in DSA driver
Changes v12:
- Update on top of net-next
- Add additional info on conver-letter about slefttests and HW limitation
- Introduce mdio-regmap generalization for multiple address
- Drop dev flags and define PHY calibration in PHY node directly
Changes v11:
- Address reviews from Christophe (spell mistake + dev_err_probe)
- Fix kconfig dependency for MFD driver (depends on MDIO_DEVICE instead of MDIO)
(indirectly fix link error for mdio APIs)
- Fix copy-paste error for MFD driver of_table
- Fix compilation error for PHY (move NVMEM to .config)
- Drop unneeded NVMEM node from MDIO example schema (from Andrew)
- Adapt MFD example schema to MDIO reg property restrictions
Changes v10:
- Entire rework to MFD + split to MDIO, EFUSE, SWITCH separate drivers
- Drop EEE OPs (while Russell finish RFC for EEE changes)
- Use new pcs_inpand OPs
- Drop AN restart function and move to pcs_config
- Enable assisted_learning and disable CPU learn (preparation for fdb_isolation)
- Move EFUSE read in Internal PHY driver to .config to handle EPROBE_DEFER
(needed now that NVMEM driver is register externally instead of internally to switch
node)
Changes v9:
- Error out on using 5G speed as currently not supported
- Add missing MAC_2500FD in phylink mac_capabilities
- Add comment and improve if condition for an8855_phylink_mac_config
Changes v8:
- Add port Fast Age support
- Add support for Port Isolation
- Use correct register for Learning Disable
- Add support for Ageing Time OP
- Set default PVID to 0 by default
- Add mdb OPs
- Add port change MTU
- Fix support for Upper VLAN
Changes v7:
- Fix devm_dsa_register_switch wrong export symbol
Changes v6:
- Drop standard MIB and handle with ethtool OPs (as requested by Jakub)
- Cosmetic: use bool instead of 0 or 1
Changes v5:
- Add devm_dsa_register_switch() patch
- Add Reviewed-by tag for DT patch
Changes v4:
- Set regmap readable_table static (mute compilation warning)
- Add support for port_bridge flags (LEARNING, FLOOD)
- Reset fdb struct in fdb_dump
- Drop support_asym_pause in port_enable
- Add define for get_phy_flags
- Fix bug for port not inititially part of a bridge
(in an8855_setup the port matrix was always cleared but
the CPU port was never initially added)
- Disable learning and flood for user port by default
- Set CPU port to flood and learning by default
- Correctly AND force duplex and flow control in an8855_phylink_mac_link_up
- Drop RGMII from pcs_config
- Check ret in "Disable AN if not in autoneg"
- Use devm_mutex_init
- Fix typo for AN8855_PORT_CHECK_MODE
- Better define AN8855_STP_LISTENING = AN8855_STP_BLOCKING
- Fix typo in AN8855_PHY_EN_DOWN_SHIFT
- Use paged helper for PHY
- Skip calibration in config_init if priv not defined
Changes v3:
- Out of RFC
- Switch PHY code to select_page API
- Better describe masks and bits in PHY driver for ADC register
- Drop raw values and use define for mii read/write
- Switch to absolute PHY address
- Replace raw values with mask and bits for pcs_config
- Fix typo for ext-surge property name
- Drop support for relocating Switch base PHY address on the bus
Changes v2:
- Drop mutex guard patch
- Drop guard usage in DSA driver
- Use __mdiobus_write/read
- Check return condition and return errors for mii read/write
- Fix wrong logic for EEE
- Fix link_down (don't force link down with autoneg)
- Fix forcing speed on sgmii autoneg
- Better document link speed for sgmii reg
- Use standard define for sgmii reg
- Imlement nvmem support to expose switch EFUSE
- Rework PHY calibration with the use of NVMEM producer/consumer
- Update DT with new NVMEM property
- Move aneg validation for 2500-basex in pcs_config
- Move r50Ohm table and function to PHY driver
Christian Marangi (10):
dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch
dt-bindings: net: Document support for AN8855 Switch Internal PHY
dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC
mfd: an8855: Add support for Airoha AN8855 Switch
net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
net: dsa: tag_mtk: add Airoha variant usage of this TAG
MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch
net: dsa: move mediatek DSA driver in dedicated directory
net: dsa: mt7530: generalize and move common function to lib module
net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver
.../bindings/mfd/airoha,an8855.yaml | 176 ++
.../bindings/net/airoha,an8855-phy.yaml | 83 +
.../net/dsa/airoha,an8855-switch.yaml | 86 +
MAINTAINERS | 22 +-
drivers/mfd/Kconfig | 14 +
drivers/mfd/Makefile | 1 +
drivers/mfd/airoha-an8855.c | 579 ++++++
drivers/net/dsa/Kconfig | 45 +-
drivers/net/dsa/Makefile | 5 +-
drivers/net/dsa/mediatek/Kconfig | 59 +
drivers/net/dsa/mediatek/Makefile | 7 +
drivers/net/dsa/mediatek/an8855.c | 1741 +++++++++++++++++
drivers/net/dsa/mediatek/an8855.h | 755 +++++++
drivers/net/dsa/mediatek/mt7530-lib.c | 1156 +++++++++++
drivers/net/dsa/mediatek/mt7530-lib.h | 413 ++++
drivers/net/dsa/{ => mediatek}/mt7530-mdio.c | 4 +
drivers/net/dsa/{ => mediatek}/mt7530-mmio.c | 4 +
drivers/net/dsa/{ => mediatek}/mt7530.c | 1366 +++----------
drivers/net/dsa/{ => mediatek}/mt7530.h | 256 +--
drivers/net/dsa/{ => mediatek}/mt7628.c | 0
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_an8855.c | 275 +++
include/net/dsa.h | 2 +
net/dsa/Kconfig | 11 +
net/dsa/Makefile | 2 +-
net/dsa/tag_mtk.c | 36 +-
27 files changed, 5808 insertions(+), 1297 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
create mode 100644 drivers/mfd/airoha-an8855.c
create mode 100644 drivers/net/dsa/mediatek/Kconfig
create mode 100644 drivers/net/dsa/mediatek/Makefile
create mode 100644 drivers/net/dsa/mediatek/an8855.c
create mode 100644 drivers/net/dsa/mediatek/an8855.h
create mode 100644 drivers/net/dsa/mediatek/mt7530-lib.c
create mode 100644 drivers/net/dsa/mediatek/mt7530-lib.h
rename drivers/net/dsa/{ => mediatek}/mt7530-mdio.c (99%)
rename drivers/net/dsa/{ => mediatek}/mt7530-mmio.c (97%)
rename drivers/net/dsa/{ => mediatek}/mt7530.c (63%)
rename drivers/net/dsa/{ => mediatek}/mt7530.h (81%)
rename drivers/net/dsa/{ => mediatek}/mt7628.c (100%)
create mode 100644 drivers/net/phy/air_an8855.c
--
2.55.0
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH net-next v24 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch
2026-09-28 19:44 [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
@ 2026-09-28 19:45 ` Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY Christian Marangi
` (7 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Christian Marangi @ 2026-09-28 19:45 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Document support for Airoha AN8855 5-port Gigabit Switch.
It does expose the 5 Internal PHYs on the MDIO bus and each port
can access the Switch register space by configuring the PHY page.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../net/dsa/airoha,an8855-switch.yaml | 86 +++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
new file mode 100644
index 000000000000..5ad9b9e13983
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Gigabit Switch
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+ Airoha AN8855 is a 5-port Gigabit Switch.
+
+ It does expose the 5 Internal PHYs on the MDIO bus and each port
+ can access the Switch register space by configuring the PHY page.
+
+$ref: dsa.yaml#/$defs/ethernet-ports
+
+properties:
+ compatible:
+ const: airoha,an8855-switch
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ ethernet-switch {
+ compatible = "airoha,an8855-switch";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy1>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy2>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy3>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy4>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy5>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
--
2.55.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH net-next v24 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY
2026-09-28 19:44 [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
2026-09-28 19:45 ` [PATCH net-next v24 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Christian Marangi
@ 2026-09-28 19:45 ` Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi
` (6 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Christian Marangi @ 2026-09-28 19:45 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Document support for AN8855 Switch Internal PHY.
Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal
PHYs on the MDIO bus.
Each PHY might need to be calibrated to correctly work with the
use of the eFUSE provided by the Switch SoC. This can be enabled by
defining in the PHY node the NVMEM cell properties.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/net/airoha,an8855-phy.yaml | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
diff --git a/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
new file mode 100644
index 000000000000..d2f86116badf
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,an8855-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Switch Internal PHY
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+ Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal
+ PHYs on the MDIO bus.
+
+ Each PHY might need to be calibrated to correctly work with the
+ use of the eFUSE provided by the Switch SoC.
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ethernet-phy-idc0ff.0410
+ required:
+ - compatible
+
+properties:
+ reg:
+ maxItems: 1
+
+ nvmem-cells:
+ items:
+ - description: phandle to SoC eFUSE tx_a
+ - description: phandle to SoC eFUSE tx_b
+ - description: phandle to SoC eFUSE tx_c
+ - description: phandle to SoC eFUSE tx_d
+
+ nvmem-cell-names:
+ items:
+ - const: tx_a
+ - const: tx_b
+ - const: tx_c
+ - const: tx_d
+
+required:
+ - compatible
+ - reg
+
+dependentRequired:
+ nvmem-cells: [ nvmem-cell-names ]
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@1 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c45";
+
+ reg = <1>;
+ };
+
+ ethernet-phy@2 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c45";
+
+ reg = <2>;
+
+ nvmem-cells = <&shift_sel_port0_tx_a>,
+ <&shift_sel_port0_tx_b>,
+ <&shift_sel_port0_tx_c>,
+ <&shift_sel_port0_tx_d>;
+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+ };
+ };
--
2.55.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH net-next v24 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC
2026-09-28 19:44 [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
2026-09-28 19:45 ` [PATCH net-next v24 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Christian Marangi
2026-09-28 19:45 ` [PATCH net-next v24 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY Christian Marangi
@ 2026-09-28 19:45 ` Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 04/10] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi
` (5 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Christian Marangi @ 2026-09-28 19:45 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Document support for Airoha AN8855 Switch SoC. This SoC expose various
peripherals like an Ethernet Switch, a NVMEM provider and Ethernet PHYs.
It does also support i2c and timers but those are not currently
supported/used.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/mfd/airoha,an8855.yaml | 176 ++++++++++++++++++
1 file changed, 176 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
diff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
new file mode 100644
index 000000000000..48127e956c96
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/airoha,an8855.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Switch SoC
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+ Airoha AN8855 Switch is a SoC that expose various peripherals like an
+ Ethernet Switch, a NVMEM provider and Ethernet PHYs.
+
+ It does also support i2c and timers but those are not currently
+ supported/used.
+
+properties:
+ compatible:
+ const: airoha,an8855
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ efuse:
+ type: object
+ $ref: /schemas/nvmem/airoha,an8855-efuse.yaml
+ description: EFUSE exposed by the Airoha AN8855 SoC
+
+ ethernet-switch:
+ type: object
+ $ref: /schemas/net/dsa/airoha,an8855-switch.yaml
+ description: Switch exposed by the Airoha AN8855 SoC
+
+ mdio:
+ type: object
+ $ref: /schemas/net/mdio.yaml#
+ description: MDIO exposed by the Airoha AN8855 SoC
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - mdio
+ - ethernet-switch
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ soc@1 {
+ compatible = "airoha,an8855";
+ reg = <1>;
+
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ efuse {
+ compatible = "airoha,an8855-efuse";
+
+ #nvmem-cell-cells = <0>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
+ reg = <0xc 0x4>;
+ };
+
+ shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
+ reg = <0x10 0x4>;
+ };
+
+ shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
+ reg = <0x14 0x4>;
+ };
+
+ shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
+ reg = <0x18 0x4>;
+ };
+
+ shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
+ reg = <0x1c 0x4>;
+ };
+
+ shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
+ reg = <0x20 0x4>;
+ };
+
+ shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
+ reg = <0x24 0x4>;
+ };
+
+ shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
+ reg = <0x28 0x4>;
+ };
+ };
+ };
+
+ ethernet-switch {
+ compatible = "airoha,an8855-switch";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy1>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy2>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+
+ nvmem-cells = <&shift_sel_port0_tx_a>,
+ <&shift_sel_port0_tx_b>,
+ <&shift_sel_port0_tx_c>,
+ <&shift_sel_port0_tx_d>;
+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+ };
+
+ internal_phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+
+ nvmem-cells = <&shift_sel_port1_tx_a>,
+ <&shift_sel_port1_tx_b>,
+ <&shift_sel_port1_tx_c>,
+ <&shift_sel_port1_tx_d>;
+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+ };
+ };
+ };
+ };
--
2.55.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH net-next v24 04/10] mfd: an8855: Add support for Airoha AN8855 Switch
2026-09-28 19:44 [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (2 preceding siblings ...)
2026-09-28 19:45 ` [PATCH net-next v24 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi
@ 2026-09-28 19:45 ` Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Christian Marangi
` (4 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Christian Marangi @ 2026-09-28 19:45 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Add support for Airoha AN8855 Switch that provide support for a DSA
switch and a NVMEM provider.
Also make use of the mdio-regmap driver and register a regmap for each
internal PHY of the switch.
This is needed to handle the double usage of the PHYs as both PHY and
Switch accessor.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/mfd/Kconfig | 14 +
drivers/mfd/Makefile | 1 +
drivers/mfd/airoha-an8855.c | 579 ++++++++++++++++++++++++++++++++++++
3 files changed, 594 insertions(+)
create mode 100644 drivers/mfd/airoha-an8855.c
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index e4fd4572472f..afbdcec0fce8 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR
using regmap_mmio accesses for ARM32 parts and SMC calls to
EL3 for ARM64 parts.
+config MFD_AIROHA_AN8855
+ tristate "Airoha AN8855 Switch Core"
+ select MFD_CORE
+ select REGMAP
+ select PHYLIB
+ select MDIO_REGMAP
+ depends on NETDEVICES && OF
+ help
+ Support for the Airoha AN8855 Switch Core. This is an SoC
+ that provides various peripherals, to count, i2c, an Ethrnet
+ Switch, a CPU timer, GPIO, eFUSE.
+
+ Currently it provides a DSA switch and a NVMEM provider.
+
config MFD_ACT8945A
tristate "Active-semi ACT8945A"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 72d3944b0ad8..484127dba2ad 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o
obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o
obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
obj-$(CONFIG_MFD_88PM886_PMIC) += 88pm886.o
+obj-$(CONFIG_MFD_AIROHA_AN8855) += airoha-an8855.o
obj-$(CONFIG_MFD_ACT8945A) += act8945a.o
obj-$(CONFIG_MFD_SM501) += sm501.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o
diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c
new file mode 100644
index 000000000000..cd5791ef436d
--- /dev/null
+++ b/drivers/mfd/airoha-an8855.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Core driver for Airoha AN8855 Switch
+ *
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/fwnode_mdio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mfd/core.h>
+#include <linux/mdio.h>
+#include <linux/mdio/mdio-regmap.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
+
+/* Register for HW trap status */
+#define AN8855_HWTRAP 0x1000009c
+
+/*
+ * Register of the Switch ID
+ * (called Project ID in Documentation)
+ */
+#define AN8855_CREV 0x10005000
+#define AN8855_ID 0x8855 /* Switch ID */
+
+/* Register for GPHY Power Down
+ * Used to Toggle the Gigabit PHY power and enable them.
+ */
+#define AN8855_RG_GPHY_AFE_PWD 0x1028c840
+
+/* MII Registers */
+#define AN8855_PHY_SELECT_PAGE 0x1f
+#define AN8855_PHY_PAGE GENMASK(2, 0)
+#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
+#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
+#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4)
+
+/* MII Registers Page 4 */
+#define AN8855_PBUS_MODE 0x10
+#define AN8855_PBUS_MODE_ADDR_FIXED 0x0
+#define AN8855_PBUS_MODE_ADDR_INCR BIT(15)
+#define AN8855_PBUS_WR_ADDR_HIGH 0x11
+#define AN8855_PBUS_WR_ADDR_LOW 0x12
+#define AN8855_PBUS_WR_DATA_HIGH 0x13
+#define AN8855_PBUS_WR_DATA_LOW 0x14
+#define AN8855_PBUS_RD_ADDR_HIGH 0x15
+#define AN8855_PBUS_RD_ADDR_LOW 0x16
+#define AN8855_PBUS_RD_DATA_HIGH 0x17
+#define AN8855_PBUS_RD_DATA_LOW 0x18
+
+#define AN8855_MAX_PHY_PORT 5
+
+struct an8855_core_priv {
+ struct mii_bus *bus;
+ struct mii_bus *phy_bus;
+ unsigned int switch_addr;
+ u16 current_page;
+};
+
+struct an8855_phy_priv {
+ u8 addr;
+ struct an8855_core_priv *core;
+};
+
+struct an8855_phy_bus {
+ struct mii_bus *bus;
+ struct fwnode_handle *node;
+ u8 addr;
+};
+
+static const struct mfd_cell an8855_cells[] = {
+ MFD_CELL_OF("an8855-efuse", NULL, NULL, 0, 0,
+ "airoha,an8855-efuse"),
+ MFD_CELL_OF("an8855-switch", NULL, NULL, 0, 0,
+ "airoha,an8855-switch"),
+};
+
+static int an8855_mii_set_page(struct an8855_core_priv *priv, u8 addr,
+ u8 page) __must_hold(&priv->bus->mdio_lock)
+{
+ struct mii_bus *bus = priv->bus;
+ int ret;
+
+ ret = __mdiobus_write(bus, addr, AN8855_PHY_SELECT_PAGE, page);
+ if (ret) {
+ dev_err_ratelimited(&bus->dev, "failed to set mii page\n");
+ return ret;
+ }
+
+ /* Cache current page if next MII read/write is for Switch page */
+ priv->current_page = page;
+ return 0;
+}
+
+static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg,
+ u32 *val) __must_hold(&bus->mdio_lock)
+{
+ int lo, hi, ret;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
+ AN8855_PBUS_MODE_ADDR_FIXED);
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH,
+ upper_16_bits(reg));
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW,
+ lower_16_bits(reg));
+ if (ret)
+ goto err;
+
+ hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH);
+ if (hi < 0) {
+ ret = hi;
+ goto err;
+ }
+
+ lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW);
+ if (lo < 0) {
+ ret = lo;
+ goto err;
+ }
+
+ *val = ((u32)hi << 16) | lo;
+
+ return 0;
+err:
+ dev_err_ratelimited(&bus->dev, "failed to read register\n");
+ return ret;
+}
+
+/*
+ * Protect concurrent access to phy page if switch address also
+ * expose a PHY.
+ */
+static void an8855_regmap_lock(struct an8855_core_priv *priv)
+{
+ if (priv->phy_bus)
+ mutex_lock(&priv->phy_bus->mdio_lock);
+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+}
+
+static void an8855_regmap_unlock(struct an8855_core_priv *priv)
+{
+ mutex_unlock(&priv->bus->mdio_lock);
+ if (priv->phy_bus)
+ mutex_unlock(&priv->phy_bus->mdio_lock);
+}
+
+static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+ struct an8855_core_priv *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ int ret;
+
+ an8855_regmap_lock(priv);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret < 0)
+ goto exit;
+
+ ret = an8855_mii_read32(bus, addr, reg, val);
+
+exit:
+ an8855_regmap_unlock(priv);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg,
+ u32 val) __must_hold(&bus->mdio_lock)
+{
+ int ret;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
+ AN8855_PBUS_MODE_ADDR_FIXED);
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH,
+ upper_16_bits(reg));
+ if (ret)
+ goto err;
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW,
+ lower_16_bits(reg));
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH,
+ upper_16_bits(val));
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW,
+ lower_16_bits(val));
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ dev_err_ratelimited(&bus->dev,
+ "failed to write an8855 register\n");
+ return ret;
+}
+
+static int an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val)
+{
+ struct an8855_core_priv *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ int ret;
+
+ an8855_regmap_lock(priv);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret)
+ goto exit;
+
+ ret = an8855_mii_write32(bus, addr, reg, val);
+
+exit:
+ an8855_regmap_unlock(priv);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask,
+ uint32_t write_val)
+{
+ struct an8855_core_priv *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ u32 val;
+ int ret;
+
+ an8855_regmap_lock(priv);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret)
+ goto exit;
+
+ ret = an8855_mii_read32(bus, addr, reg, &val);
+ if (ret < 0)
+ goto exit;
+
+ val &= ~mask;
+ val |= write_val & mask;
+ ret = an8855_mii_write32(bus, addr, reg, val);
+
+exit:
+ an8855_regmap_unlock(priv);
+
+ return ret < 0 ? ret : 0;
+}
+
+static const struct regmap_range an8855_readable_ranges[] = {
+ regmap_reg_range(0x10000000, 0x10000fff), /* SCU */
+ regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */
+ regmap_reg_range(0x10002000, 0x10002fff), /* MCU */
+ regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */
+ regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */
+ regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */
+ regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */
+ regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */
+ regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */
+ regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */
+ regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */
+ regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */
+ regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */
+ regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */
+ regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */
+ regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */
+ regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */
+ regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */
+ regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */
+ regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */
+ regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */
+ regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */
+ regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */
+ regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */
+ regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */
+ regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */
+ regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */
+};
+
+static const struct regmap_access_table an8855_readable_table = {
+ .yes_ranges = an8855_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges),
+};
+
+static const struct regmap_config an8855_regmap_config = {
+ .name = "switch",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0xbfffffff,
+ .reg_read = an8855_regmap_read,
+ .reg_write = an8855_regmap_write,
+ .reg_update_bits = an8855_regmap_update_bits,
+ .disable_locking = true,
+ .rd_table = &an8855_readable_table,
+};
+
+static int an8855_regmap_phy_reset_page(struct an8855_core_priv *priv,
+ int phy) __must_hold(&priv->bus->mdio_lock)
+{
+ /* Check PHY page only for addr shared with switch */
+ if (phy != priv->switch_addr)
+ return 0;
+
+ /* Don't restore page if it's not set to Switch page */
+ if (priv->current_page != AN8855_PHY_PAGE_EXTENDED_4)
+ return 0;
+
+ /*
+ * Restore page to 0, PHY might change page right after but that
+ * will be ignored as it won't be a switch page.
+ */
+ return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);
+}
+
+static int an8855_regmap_phy_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+ struct an8855_phy_priv *priv = ctx;
+ struct an8855_core_priv *core_priv;
+ u32 addr = priv->addr;
+ struct mii_bus *bus;
+ int ret;
+
+ core_priv = priv->core;
+ bus = core_priv->bus;
+
+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_regmap_phy_reset_page(core_priv, addr);
+ if (ret)
+ goto exit;
+
+ ret = __mdiobus_read(bus, addr, reg);
+ if (ret >= 0)
+ *val = ret;
+
+exit:
+ mutex_unlock(&bus->mdio_lock);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_regmap_phy_write(void *ctx, uint32_t reg, uint32_t val)
+{
+ struct an8855_phy_priv *priv = ctx;
+ struct an8855_core_priv *core_priv;
+ u32 addr = priv->addr;
+ struct mii_bus *bus;
+ int ret;
+
+ core_priv = priv->core;
+ bus = core_priv->bus;
+
+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_regmap_phy_reset_page(core_priv, addr);
+ if (ret)
+ goto exit;
+
+ ret = __mdiobus_write(bus, addr, reg, val);
+
+exit:
+ mutex_unlock(&bus->mdio_lock);
+
+ return ret;
+}
+
+static const struct regmap_config an8855_phy_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 16,
+ .reg_read = an8855_regmap_phy_read,
+ .reg_write = an8855_regmap_phy_write,
+ .disable_locking = true,
+ .max_register = 0x1f,
+};
+
+static int an8855_read_switch_id(struct device *dev, struct regmap *regmap)
+{
+ u32 id;
+ int ret;
+
+ ret = regmap_read(regmap, AN8855_CREV, &id);
+ if (ret)
+ return ret;
+
+ if (id != AN8855_ID) {
+ dev_err(dev, "Detected Switch ID %x but %x was expected\n",
+ id, AN8855_ID);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int an8855_phy_bus_register(struct device *dev, struct an8855_core_priv *priv,
+ struct device_node *phy_np,
+ struct an8855_phy_bus *phy_bus_info)
+{
+ struct mdio_regmap_config mrc = { };
+ struct an8855_phy_priv *phy_priv;
+ struct regmap *regmap;
+ u32 addr, phy_offset;
+ struct mii_bus *bus;
+ int ret;
+
+ ret = of_property_read_u32(phy_np, "reg", &addr);
+ if (ret)
+ return ret;
+
+ phy_offset = addr - priv->switch_addr;
+ if (phy_offset >= AN8855_MAX_PHY_PORT)
+ return -EINVAL;
+
+ phy_priv = devm_kzalloc(dev, sizeof(*phy_priv), GFP_KERNEL);
+ if (!phy_priv)
+ return -ENOMEM;
+
+ phy_priv->addr = addr;
+ phy_priv->core = priv;
+
+ regmap = devm_regmap_init(dev, NULL, phy_priv, &an8855_phy_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap),
+ "phy%d regmap initialization failed\n",
+ addr);
+
+ mrc.regmap = regmap;
+ mrc.parent = dev;
+ mrc.valid_addr = addr;
+ snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-phy%u", dev_name(dev), addr);
+
+ bus = devm_mdio_regmap_register(dev, &mrc);
+ if (IS_ERR(bus))
+ return PTR_ERR(bus);
+
+ if (addr == priv->switch_addr)
+ priv->phy_bus = bus;
+
+ phy_bus_info->bus = bus;
+ phy_bus_info->addr = addr;
+ phy_bus_info->node = fwnode_handle_get(of_fwnode_handle(phy_np));
+
+ return 0;
+}
+
+static int an8855_mdio_register(struct device *dev, struct an8855_core_priv *priv,
+ struct an8855_phy_bus *phy_bus_infos)
+{
+ struct device_node *mdio_np;
+ int ret = 0;
+ int i = 0;
+
+ mdio_np = of_get_child_by_name(dev->of_node, "mdio");
+ if (!mdio_np)
+ return -ENODEV;
+
+ for_each_available_child_of_node_scoped(mdio_np, phy_np) {
+ if (i >= AN8855_MAX_PHY_PORT) {
+ ret = -EINVAL;
+ goto exit;
+ }
+
+ ret = an8855_phy_bus_register(dev, priv, phy_np,
+ &phy_bus_infos[i]);
+ if (ret)
+ goto exit;
+
+ i++;
+ }
+
+exit:
+ of_node_put(mdio_np);
+ if (ret) {
+ while (i--)
+ fwnode_handle_put(phy_bus_infos[i].node);
+
+ return ret;
+ }
+
+ return i;
+}
+
+static int an8855_core_probe(struct mdio_device *mdiodev)
+{
+ struct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] = { };
+ struct device *dev = &mdiodev->dev;
+ struct an8855_core_priv *priv;
+ struct regmap *regmap;
+ int num_phys;
+ int i, ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->bus = mdiodev->bus;
+ priv->switch_addr = mdiodev->addr;
+ /* No DMA for mdiobus, mute warning for DMA mask not set */
+ dev->dma_mask = &dev->coherent_dma_mask;
+
+ /* Register virtual MDIO for each PHY */
+ num_phys = an8855_mdio_register(dev, priv, phy_bus_infos);
+ if (num_phys < 0)
+ return num_phys;
+
+ regmap = devm_regmap_init(dev, NULL, priv, &an8855_regmap_config);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ dev_err_probe(dev, ret, "regmap initialization failed\n");
+ goto err_put_fwnodes;
+ }
+
+ /* Reset PHY page for switch address */
+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_mii_set_page(priv, priv->switch_addr,
+ AN8855_PHY_PAGE_STANDARD);
+ mutex_unlock(&priv->bus->mdio_lock);
+ if (ret)
+ goto err_put_fwnodes;
+
+ ret = an8855_read_switch_id(dev, regmap);
+ if (ret)
+ goto err_put_fwnodes;
+
+ /* Release global PHY power down */
+ ret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0);
+ if (ret)
+ goto err_put_fwnodes;
+
+ /* Register PHYs */
+ for (i = 0; i < num_phys; i++) {
+ ret = fwnode_mdiobus_register_phy(phy_bus_infos[i].bus,
+ phy_bus_infos[i].node,
+ phy_bus_infos[i].addr);
+ fwnode_handle_put(phy_bus_infos[i].node);
+ phy_bus_infos[i].node = NULL;
+
+ if (ret)
+ goto err_put_fwnodes;
+ }
+
+ return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells,
+ ARRAY_SIZE(an8855_cells), NULL, 0,
+ NULL);
+
+err_put_fwnodes:
+ for (i = 0; i < num_phys; i++)
+ if (phy_bus_infos[i].node)
+ fwnode_handle_put(phy_bus_infos[i].node);
+
+ return ret;
+}
+
+static const struct of_device_id an8855_core_of_match[] = {
+ { .compatible = "airoha,an8855" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_core_of_match);
+
+static struct mdio_driver an8855_core_driver = {
+ .probe = an8855_core_probe,
+ .mdiodrv.driver = {
+ .name = "an8855",
+ .of_match_table = an8855_core_of_match,
+ },
+};
+mdio_module_driver(an8855_core_driver);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for Airoha AN8855");
+MODULE_LICENSE("GPL");
--
2.55.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH net-next v24 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
2026-09-28 19:44 [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (3 preceding siblings ...)
2026-09-28 19:45 ` [PATCH net-next v24 04/10] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi
@ 2026-09-28 19:45 ` Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG Christian Marangi
` (3 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Christian Marangi @ 2026-09-28 19:45 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Cc: Andrew Lunn
Add support for Airoha AN8855 Internal Switch Gigabit PHY.
This is a simple PHY driver to configure and calibrate the PHY for the
AN8855 Switch with the use of NVMEM cells.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_an8855.c | 275 +++++++++++++++++++++++++++++++++++
3 files changed, 282 insertions(+)
create mode 100644 drivers/net/phy/air_an8855.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d3835597e379..eca2ce135c86 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -96,6 +96,12 @@ config AIR_AN8801_PHY
help
Currently supports the Airoha AN8801R PHY.
+config AIR_AN8855_PHY
+ tristate "Airoha AN8855 Internal Gigabit PHY"
+ depends on NVMEM || !NVMEM
+ help
+ Currently supports the internal Airoha AN8855 Switch PHY.
+
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
select AIR_NET_PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 579066a638f0..d5c633db0742 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
obj-$(CONFIG_ADIN1140_PHY) += adin1140-phy.o
obj-$(CONFIG_AIR_AN8801_PHY) += air_an8801.o
+obj-$(CONFIG_AIR_AN8855_PHY) += air_an8855.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
diff --git a/drivers/net/phy/air_an8855.c b/drivers/net/phy/air_an8855.c
new file mode 100644
index 000000000000..bc22256fd5f9
--- /dev/null
+++ b/drivers/net/phy/air_an8855.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+
+#define AN8855_PHY_SELECT_PAGE 0x1f
+#define AN8855_PHY_PAGE GENMASK(2, 0)
+#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
+#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
+
+/* MII Registers Page 1 */
+#define AN8855_PHY_EXT_REG_14 0x14
+#define AN8855_PHY_EN_DOWN_SHIFT BIT(4)
+
+/* R50 Calibration regs in MDIO_MMD_VEND1 */
+#define AN8855_PHY_R50OHM_RSEL_TX_AB 0x174
+#define AN8855_PHY_R50OHM_RSEL_TX_A_EN BIT(15)
+#define AN8855_PHY_R50OHM_RSEL_TX_A GENMASK(14, 8)
+#define AN8855_PHY_R50OHM_RSEL_TX_B_EN BIT(7)
+#define AN8855_PHY_R50OHM_RSEL_TX_B GENMASK(6, 0)
+#define AN8855_PHY_R50OHM_RSEL_TX_CD 0x175
+#define AN8855_PHY_R50OHM_RSEL_TX_C_EN BIT(15)
+#define AN8855_PHY_R50OHM_RSEL_TX_C GENMASK(14, 8)
+#define AN8855_PHY_R50OHM_RSEL_TX_D_EN BIT(7)
+#define AN8855_PHY_R50OHM_RSEL_TX_D GENMASK(6, 0)
+
+#define AN8855_SWITCH_EFUSE_R50O GENMASK(30, 24)
+
+/* PHY TX PAIR DELAY SELECT Register */
+#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE 0x013
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE GENMASK(14, 12)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_B_GBE GENMASK(10, 8)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE GENMASK(6, 4)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_D_GBE GENMASK(2, 0)
+/* PHY ADC Register */
+#define AN8855_PHY_RXADC_CTRL 0x0d8
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_A BIT(12)
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_B BIT(8)
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_C BIT(4)
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_D BIT(0)
+#define AN8855_PHY_RXADC_REV_0 0x0d9
+#define AN8855_PHY_RG_AD_RESERVE0_A GENMASK(15, 8)
+#define AN8855_PHY_RG_AD_RESERVE0_B GENMASK(7, 0)
+#define AN8855_PHY_RXADC_REV_1 0x0da
+#define AN8855_PHY_RG_AD_RESERVE0_C GENMASK(15, 8)
+#define AN8855_PHY_RG_AD_RESERVE0_D GENMASK(7, 0)
+
+#define AN8855_PHY_ID 0xc0ff0410
+
+struct air_an8855_priv {
+ bool needs_calibration;
+ u8 calibration_data[4];
+};
+
+static const u8 dsa_r50ohm_table[] = {
+ 127, 127, 127, 127, 127, 127, 127, 127, 127, 127,
+ 127, 127, 127, 127, 127, 127, 127, 126, 122, 117,
+ 112, 109, 104, 101, 97, 94, 90, 88, 84, 80,
+ 78, 74, 72, 68, 66, 64, 61, 58, 56, 53,
+ 51, 48, 47, 44, 42, 40, 38, 36, 34, 32,
+ 31, 28, 27, 24, 24, 22, 20, 18, 16, 16,
+ 14, 12, 11, 9
+};
+
+static int an8855_get_r50ohm_val(struct device *dev, const char *calib_name,
+ u8 *dest)
+{
+ u32 shift_sel, val;
+ int ret;
+ int i;
+
+ ret = nvmem_cell_read_u32(dev, calib_name, &val);
+ if (ret)
+ return ret;
+
+ shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val);
+ for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++)
+ if (dsa_r50ohm_table[i] == shift_sel)
+ break;
+
+ if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table))
+ *dest = dsa_r50ohm_table[25];
+ else
+ *dest = dsa_r50ohm_table[i - 8];
+
+ return 0;
+}
+
+static int an8855_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct air_an8855_priv *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->needs_calibration = of_property_present(dev->of_node,
+ "nvmem-cells");
+
+ if (priv->needs_calibration) {
+ int ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_a", &priv->calibration_data[0]);
+ if (ret)
+ return ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_b", &priv->calibration_data[1]);
+ if (ret)
+ return ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_c", &priv->calibration_data[2]);
+ if (ret)
+ return ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_d", &priv->calibration_data[3]);
+ if (ret)
+ return ret;
+ }
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static int an8855_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val;
+
+ val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);
+ if (val < 0)
+ return val;
+
+ *data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :
+ DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;
+
+ return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1,
+ AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT,
+ ds);
+}
+
+static int an8855_config_init(struct phy_device *phydev)
+{
+ struct air_an8855_priv *priv = phydev->priv;
+ int ret;
+
+ /* Enable HW auto downshift */
+ ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
+ if (ret)
+ return ret;
+
+ if (priv->needs_calibration) {
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX_AB,
+ AN8855_PHY_R50OHM_RSEL_TX_A_EN | AN8855_PHY_R50OHM_RSEL_TX_A |
+ AN8855_PHY_R50OHM_RSEL_TX_B_EN | AN8855_PHY_R50OHM_RSEL_TX_B,
+ AN8855_PHY_R50OHM_RSEL_TX_A_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A,
+ priv->calibration_data[0]) |
+ AN8855_PHY_R50OHM_RSEL_TX_B_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B,
+ priv->calibration_data[1]));
+ if (ret)
+ return ret;
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX_CD,
+ AN8855_PHY_R50OHM_RSEL_TX_C_EN | AN8855_PHY_R50OHM_RSEL_TX_C |
+ AN8855_PHY_R50OHM_RSEL_TX_D_EN | AN8855_PHY_R50OHM_RSEL_TX_D,
+ AN8855_PHY_R50OHM_RSEL_TX_C_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C,
+ priv->calibration_data[2]) |
+ AN8855_PHY_R50OHM_RSEL_TX_D_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D,
+ priv->calibration_data[3]));
+ if (ret)
+ return ret;
+ }
+
+ /* Apply values to reduce signal noise */
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE,
+ AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE |
+ AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE,
+ FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE, 0x4) |
+ FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE, 0x4));
+ if (ret)
+ return ret;
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL,
+ AN8855_PHY_RG_AD_SAMPLE_PHSEL_A |
+ AN8855_PHY_RG_AD_SAMPLE_PHSEL_C);
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0,
+ FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1));
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1,
+ FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int an8855_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return an8855_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int an8855_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return an8855_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int an8855_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, AN8855_PHY_SELECT_PAGE);
+}
+
+static int an8855_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page);
+}
+
+static struct phy_driver an8855_driver[] = {
+{
+ PHY_ID_MATCH_EXACT(AN8855_PHY_ID),
+ .name = "Airoha AN8855 internal PHY",
+ /* PHY_GBIT_FEATURES */
+ .flags = PHY_IS_INTERNAL,
+ .probe = an8855_probe,
+ .config_init = an8855_config_init,
+ .soft_reset = genphy_soft_reset,
+ .get_tunable = an8855_get_tunable,
+ .set_tunable = an8855_set_tunable,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ .read_page = an8855_read_page,
+ .write_page = an8855_write_page,
+}, };
+
+module_phy_driver(an8855_driver);
+
+static struct mdio_device_id __maybe_unused an8855_tbl[] = {
+ { PHY_ID_MATCH_EXACT(AN8855_PHY_ID) },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, an8855_tbl);
+
+MODULE_DESCRIPTION("Airoha AN8855 PHY driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
--
2.55.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH net-next v24 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG
2026-09-28 19:44 [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (4 preceding siblings ...)
2026-09-28 19:45 ` [PATCH net-next v24 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Christian Marangi
@ 2026-09-28 19:45 ` Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 07/10] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch Christian Marangi
` (2 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Christian Marangi @ 2026-09-28 19:45 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Cc: Andrew Lunn
Add variant of the MTK TAG for Airoha Switch and comments about difference
between Airoha AN8855 and Mediatek tag bitmap.
Airoha AN8855 doesn't support controlling SA learning and Leaky VLAN
from tag. Although these bits are not used (and even not defined for
Leaky VLAN), it's worth to add comments for these difference to prevent
any kind of regression in the future if ever these bits will be used.
Rework the makefile, config and tag driver to better report to
external tool (like libpcap) the usage of this variant with a dedicated
"Airoha" name.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
include/net/dsa.h | 2 ++
net/dsa/Kconfig | 11 +++++++++++
net/dsa/Makefile | 2 +-
net/dsa/tag_mtk.c | 36 +++++++++++++++++++++++++++++++++---
4 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 5d12191b6f6f..9824c63ad50b 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -62,6 +62,7 @@ struct tc_action;
#define DSA_TAG_PROTO_KSZ8463_VALUE 34
#define DSA_TAG_PROTO_MT7628_VALUE 35
#define DSA_TAG_PROTO_KS8995_VALUE 36
+#define DSA_TAG_PROTO_AIROHA_VALUE 37
enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
@@ -76,6 +77,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_KSZ9893 = DSA_TAG_PROTO_KSZ9893_VALUE,
DSA_TAG_PROTO_LAN9303 = DSA_TAG_PROTO_LAN9303_VALUE,
DSA_TAG_PROTO_MTK = DSA_TAG_PROTO_MTK_VALUE,
+ DSA_TAG_PROTO_AIROHA = DSA_TAG_PROTO_AIROHA_VALUE,
DSA_TAG_PROTO_QCA = DSA_TAG_PROTO_QCA_VALUE,
DSA_TAG_PROTO_TRAILER = DSA_TAG_PROTO_TRAILER_VALUE,
DSA_TAG_PROTO_8021Q = DSA_TAG_PROTO_8021Q_VALUE,
diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
index 4f44bf3ede23..28a249f04a43 100644
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -24,6 +24,13 @@ config NET_DSA_TAG_NONE
Say Y or M if you want to enable support for switches which don't tag
frames over the CPU port.
+config NET_DSA_TAG_AIROHA
+ tristate "Tag driver for Airoha switches"
+ select NET_DSA_TAG_MTK_COMMON
+ help
+ Say Y or M if you want to enable support for tagging frames for
+ Airoha switches.
+
config NET_DSA_TAG_AR9331
tristate "Tag driver for Atheros AR9331 SoC with built-in switch"
help
@@ -104,8 +111,12 @@ config NET_DSA_TAG_MT7628
Say Y or M if you want to enable support for tagging frames for the
switch embedded in the MT7628 SoC.
+config NET_DSA_TAG_MTK_COMMON
+ tristate
+
config NET_DSA_TAG_MTK
tristate "Tag driver for Mediatek switches"
+ select NET_DSA_TAG_MTK_COMMON
help
Say Y or M if you want to enable support for tagging frames for
Mediatek switches.
diff --git a/net/dsa/Makefile b/net/dsa/Makefile
index 1f9cc30e9988..7ccaa528a989 100644
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_NET_DSA_TAG_KS8995) += tag_ks8995.o
obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o
obj-$(CONFIG_NET_DSA_TAG_MT7628) += tag_mt7628.o
-obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
+obj-$(CONFIG_NET_DSA_TAG_MTK_COMMON) += tag_mtk.o
obj-$(CONFIG_NET_DSA_TAG_MXL_862XX) += tag_mxl862xx.o
obj-$(CONFIG_NET_DSA_TAG_MXL_GSW1XX) += tag_mxl-gsw1xx.o
obj-$(CONFIG_NET_DSA_TAG_NETC) += tag_netc.o
diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
index c7dc7731675e..f8087d768da6 100644
--- a/net/dsa/tag_mtk.c
+++ b/net/dsa/tag_mtk.c
@@ -11,6 +11,7 @@
#include "tag.h"
#define MTK_NAME "mtk"
+#define AIROHA_NAME "airoha"
#define MTK_HDR_LEN 4
#define MTK_HDR_XMIT_UNTAGGED 0
@@ -18,6 +19,9 @@
#define MTK_HDR_XMIT_TAGGED_TPID_88A8 2
#define MTK_HDR_RECV_SOURCE_PORT_MASK GENMASK(2, 0)
#define MTK_HDR_XMIT_DP_BIT_MASK GENMASK(5, 0)
+/* AN8855 doesn't support SA_DIS and Leaky VLAN
+ * control in tag as these bits doesn't exist.
+ */
#define MTK_HDR_XMIT_SA_DIS BIT(6)
static struct sk_buff *mtk_tag_xmit(struct sk_buff *skb,
@@ -99,6 +103,7 @@ static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, struct net_device *dev)
return skb;
}
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)
static const struct dsa_device_ops mtk_netdev_ops = {
.name = MTK_NAME,
.proto = DSA_TAG_PROTO_MTK,
@@ -107,8 +112,33 @@ static const struct dsa_device_ops mtk_netdev_ops = {
.needed_headroom = MTK_HDR_LEN,
};
-MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
-MODULE_LICENSE("GPL");
+DSA_TAG_DRIVER(mtk_netdev_ops);
MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);
+#endif
-module_dsa_tag_driver(mtk_netdev_ops);
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
+static const struct dsa_device_ops airoha_netdev_ops = {
+ .name = AIROHA_NAME,
+ .proto = DSA_TAG_PROTO_AIROHA,
+ .xmit = mtk_tag_xmit,
+ .rcv = mtk_tag_rcv,
+ .needed_headroom = MTK_HDR_LEN,
+};
+
+DSA_TAG_DRIVER(airoha_netdev_ops);
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_AIROHA, AIROHA_NAME);
+#endif
+
+static struct dsa_tag_driver *dsa_tag_driver_array[] = {
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)
+ &DSA_TAG_DRIVER_NAME(mtk_netdev_ops),
+#endif
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
+ &DSA_TAG_DRIVER_NAME(airoha_netdev_ops),
+#endif
+};
+
+module_dsa_tag_drivers(dsa_tag_driver_array);
+
+MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
+MODULE_LICENSE("GPL");
--
2.55.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH net-next v24 07/10] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch
2026-09-28 19:44 [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (5 preceding siblings ...)
2026-09-28 19:45 ` [PATCH net-next v24 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG Christian Marangi
@ 2026-09-28 19:45 ` Christian Marangi
2026-09-28 19:45 ` [PATCH net-next v24 08/10] net: dsa: move mediatek DSA driver in dedicated directory Christian Marangi
2026-09-28 19:45 ` [PATCH net-next v24 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Christian Marangi
8 siblings, 0 replies; 17+ messages in thread
From: Christian Marangi @ 2026-09-28 19:45 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Cc: Andrew Lunn
Add myself as maintainer for AN8855 DSA driver and all the related
subdriver (mfd, mdio, phy, nvmem)
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
MAINTAINERS | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6de1ff058db6..59e6385b2c50 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -759,6 +759,22 @@ S: Maintained
F: Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
F: drivers/net/ethernet/airoha/
+AIROHA AN8855 DSA DRIVER
+M: Christian Marangi <ansuelsmth@gmail.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
+F: Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
+F: Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
+F: Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml
+F: drivers/mfd/airoha-an8855.c
+F: drivers/net/dsa/mediatek/an8855.c
+F: drivers/net/dsa/mediatek/an8855.h
+F: drivers/net/phy/air_an8855.c
+F: drivers/nvmem/an8855-efuse.c
+
AIROHA PCIE PHY DRIVER
M: Lorenzo Bianconi <lorenzo@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
--
2.55.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH net-next v24 08/10] net: dsa: move mediatek DSA driver in dedicated directory
2026-09-28 19:44 [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (6 preceding siblings ...)
2026-09-28 19:45 ` [PATCH net-next v24 07/10] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch Christian Marangi
@ 2026-09-28 19:45 ` Christian Marangi
2026-09-28 19:45 ` [PATCH net-next v24 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Christian Marangi
8 siblings, 0 replies; 17+ messages in thread
From: Christian Marangi @ 2026-09-28 19:45 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
To tidy things up and better organize DSA drivers, move the Mediatek
related driver to the dedicated Vendor directory.
MAINTAINERS file is updated accordingly to reference the new location.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
MAINTAINERS | 6 +--
drivers/net/dsa/Kconfig | 45 +-------------------
drivers/net/dsa/Makefile | 5 +--
drivers/net/dsa/mediatek/Kconfig | 45 ++++++++++++++++++++
drivers/net/dsa/mediatek/Makefile | 5 +++
drivers/net/dsa/{ => mediatek}/mt7530-mdio.c | 0
drivers/net/dsa/{ => mediatek}/mt7530-mmio.c | 0
drivers/net/dsa/{ => mediatek}/mt7530.c | 0
drivers/net/dsa/{ => mediatek}/mt7530.h | 0
drivers/net/dsa/{ => mediatek}/mt7628.c | 0
10 files changed, 55 insertions(+), 51 deletions(-)
create mode 100644 drivers/net/dsa/mediatek/Kconfig
create mode 100644 drivers/net/dsa/mediatek/Makefile
rename drivers/net/dsa/{ => mediatek}/mt7530-mdio.c (100%)
rename drivers/net/dsa/{ => mediatek}/mt7530-mmio.c (100%)
rename drivers/net/dsa/{ => mediatek}/mt7530.c (100%)
rename drivers/net/dsa/{ => mediatek}/mt7530.h (100%)
rename drivers/net/dsa/{ => mediatek}/mt7628.c (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 59e6385b2c50..ff8c5dda07b5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16839,9 +16839,9 @@ M: Chester A. Unal <chester.a.unal@arinc9.com>
M: Daniel Golle <daniel@makrotopia.org>
L: netdev@vger.kernel.org
S: Maintained
-F: drivers/net/dsa/mt7530-mdio.c
-F: drivers/net/dsa/mt7530-mmio.c
-F: drivers/net/dsa/mt7530.*
+F: drivers/net/dsa/mediatek/mt7530-mdio.c
+F: drivers/net/dsa/mediatek/mt7530-mmio.c
+F: drivers/net/dsa/mediatek/mt7530.*
F: net/dsa/tag_mtk.c
MEDIATEK T7XX 5G WWAN MODEM DRIVER
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index fe8cd5338fda..ffc26eb3e899 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -28,50 +28,7 @@ source "drivers/net/dsa/hirschmann/Kconfig"
source "drivers/net/dsa/lantiq/Kconfig"
-config NET_DSA_MT7530
- tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
- select NET_DSA_TAG_MTK
- select REGMAP_IRQ
- imply NET_DSA_MT7530_MDIO
- imply NET_DSA_MT7530_MMIO
- help
- This enables support for the MediaTek MT7530 and MT7531 Ethernet
- switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
- MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
- supported as well.
-
-config NET_DSA_MT7530_MDIO
- tristate "MediaTek MT7530 MDIO interface driver"
- depends on NET_DSA_MT7530
- select MEDIATEK_GE_PHY
- select PCS_MTK_LYNXI
- help
- This enables support for the MediaTek MT7530 and MT7531 switch
- chips which are connected via MDIO, as well as multi-chip
- module MT7530 which can be found in the MT7621AT, MT7621DAT,
- MT7621ST and MT7623AI SoCs.
-
-config NET_DSA_MT7530_MMIO
- tristate "MediaTek MT7530 MMIO interface driver"
- depends on NET_DSA_MT7530
- depends on HAS_IOMEM
- imply MEDIATEK_GE_SOC_PHY
- help
- This enables support for the built-in Ethernet switch found
- in the MediaTek MT7988 SoC.
- The switch is a similar design as MT7531, but the switch registers
- are directly mapped into the SoCs register space rather than being
- accessible via MDIO.
-
-config NET_DSA_MT7628
- tristate "MediaTek MT7628 Embedded Ethernet switch support"
- depends on HAS_IOMEM && (SOC_MT7620 || COMPILE_TEST)
- select NET_DSA_TAG_MT7628
- select MEDIATEK_FE_SOC_PHY
- select REGMAP_MMIO
- help
- This enables support for the built-in Ethernet switch found
- in the MT7628 SoC.
+source "drivers/net/dsa/mediatek/Kconfig"
config NET_DSA_MV88E6060
tristate "Marvell 88E6060 ethernet switch chip support"
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index 7e637d56b35c..ee4784a9839b 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -2,10 +2,6 @@
obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm-sf2.o
bcm-sf2-objs := bcm_sf2.o bcm_sf2_cfp.o
obj-$(CONFIG_NET_DSA_LOOP) += dsa_loop.o
-obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
-obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
-obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
-obj-$(CONFIG_NET_DSA_MT7628) += mt7628.o
obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o
obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
@@ -17,6 +13,7 @@ obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_SPI) += vitesse-vsc73xx-spi.o
obj-y += b53/
obj-y += hirschmann/
obj-y += lantiq/
+obj-y += mediatek/
obj-y += microchip/
obj-y += motorcomm/
obj-y += mv88e6xxx/
diff --git a/drivers/net/dsa/mediatek/Kconfig b/drivers/net/dsa/mediatek/Kconfig
new file mode 100644
index 000000000000..ef62481662fd
--- /dev/null
+++ b/drivers/net/dsa/mediatek/Kconfig
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config NET_DSA_MT7530
+ tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
+ select NET_DSA_TAG_MTK
+ select REGMAP_IRQ
+ imply NET_DSA_MT7530_MDIO
+ imply NET_DSA_MT7530_MMIO
+ help
+ This enables support for the MediaTek MT7530 and MT7531 Ethernet
+ switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
+ MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
+ supported as well.
+
+config NET_DSA_MT7530_MDIO
+ tristate "MediaTek MT7530 MDIO interface driver"
+ depends on NET_DSA_MT7530
+ select MEDIATEK_GE_PHY
+ select PCS_MTK_LYNXI
+ help
+ This enables support for the MediaTek MT7530 and MT7531 switch
+ chips which are connected via MDIO, as well as multi-chip
+ module MT7530 which can be found in the MT7621AT, MT7621DAT,
+ MT7621ST and MT7623AI SoCs.
+
+config NET_DSA_MT7530_MMIO
+ tristate "MediaTek MT7530 MMIO interface driver"
+ depends on NET_DSA_MT7530
+ depends on HAS_IOMEM
+ imply MEDIATEK_GE_SOC_PHY
+ help
+ This enables support for the built-in Ethernet switch found
+ in the MediaTek MT7988 SoC.
+ The switch is a similar design as MT7531, but the switch registers
+ are directly mapped into the SoCs register space rather than being
+ accessible via MDIO.
+
+config NET_DSA_MT7628
+ tristate "MediaTek MT7628 Embedded Ethernet switch support"
+ depends on HAS_IOMEM && (SOC_MT7620 || COMPILE_TEST)
+ select NET_DSA_TAG_MT7628
+ select MEDIATEK_FE_SOC_PHY
+ select REGMAP_MMIO
+ help
+ This enables support for the built-in Ethernet switch found
+ in the MT7628 SoC.
diff --git a/drivers/net/dsa/mediatek/Makefile b/drivers/net/dsa/mediatek/Makefile
new file mode 100644
index 000000000000..0ed6e11f292e
--- /dev/null
+++ b/drivers/net/dsa/mediatek/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
+obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
+obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
+obj-$(CONFIG_NET_DSA_MT7628) += mt7628.o
diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mediatek/mt7530-mdio.c
similarity index 100%
rename from drivers/net/dsa/mt7530-mdio.c
rename to drivers/net/dsa/mediatek/mt7530-mdio.c
diff --git a/drivers/net/dsa/mt7530-mmio.c b/drivers/net/dsa/mediatek/mt7530-mmio.c
similarity index 100%
rename from drivers/net/dsa/mt7530-mmio.c
rename to drivers/net/dsa/mediatek/mt7530-mmio.c
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mediatek/mt7530.c
similarity index 100%
rename from drivers/net/dsa/mt7530.c
rename to drivers/net/dsa/mediatek/mt7530.c
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mediatek/mt7530.h
similarity index 100%
rename from drivers/net/dsa/mt7530.h
rename to drivers/net/dsa/mediatek/mt7530.h
diff --git a/drivers/net/dsa/mt7628.c b/drivers/net/dsa/mediatek/mt7628.c
similarity index 100%
rename from drivers/net/dsa/mt7628.c
rename to drivers/net/dsa/mediatek/mt7628.c
--
2.55.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH net-next v24 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver
2026-09-28 19:44 [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (7 preceding siblings ...)
2026-09-28 19:45 ` [PATCH net-next v24 08/10] net: dsa: move mediatek DSA driver in dedicated directory Christian Marangi
@ 2026-09-28 19:45 ` Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
8 siblings, 1 reply; 17+ messages in thread
From: Christian Marangi @ 2026-09-28 19:45 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Cc: Andrew Lunn
Add Airoha AN8855 5-Port Gigabit DSA switch. Switch can support
10M, 100M, 1Gb, 2.5G and 5G Ethernet Speed but 5G is currently error out
as it's not currently supported as requires additional configuration for
the PCS.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/dsa/mediatek/Kconfig | 10 +
drivers/net/dsa/mediatek/Makefile | 1 +
drivers/net/dsa/mediatek/an8855.c | 1741 +++++++++++++++++++++++++
drivers/net/dsa/mediatek/an8855.h | 755 +++++++++++
drivers/net/dsa/mediatek/mt7530-lib.c | 68 +-
drivers/net/dsa/mediatek/mt7530-lib.h | 22 +
6 files changed, 2577 insertions(+), 20 deletions(-)
create mode 100644 drivers/net/dsa/mediatek/an8855.c
create mode 100644 drivers/net/dsa/mediatek/an8855.h
diff --git a/drivers/net/dsa/mediatek/Kconfig b/drivers/net/dsa/mediatek/Kconfig
index 7b48300dca0c..2799e78a8651 100644
--- a/drivers/net/dsa/mediatek/Kconfig
+++ b/drivers/net/dsa/mediatek/Kconfig
@@ -1,4 +1,14 @@
# SPDX-License-Identifier: GPL-2.0-only
+config NET_DSA_AN8855
+ tristate "Airoha AN8855 Ethernet switch support"
+ depends on MFD_AIROHA_AN8855 || COMPILE_TEST
+ depends on NET_DSA
+ select NET_DSA_MT7530_LIB
+ select NET_DSA_TAG_AIROHA
+ help
+ This enables support for the Ethernet switch inside the
+ Airoha AN8855 chip.
+
config NET_DSA_MT7530_LIB
tristate
diff --git a/drivers/net/dsa/mediatek/Makefile b/drivers/net/dsa/mediatek/Makefile
index b2c0693dbb58..60e5f5cd0901 100644
--- a/drivers/net/dsa/mediatek/Makefile
+++ b/drivers/net/dsa/mediatek/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_NET_DSA_AN8855) += an8855.o
obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
obj-$(CONFIG_NET_DSA_MT7530_LIB) += mt7530-lib.o
obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
diff --git a/drivers/net/dsa/mediatek/an8855.c b/drivers/net/dsa/mediatek/an8855.c
new file mode 100644
index 000000000000..b4b02b7cb6eb
--- /dev/null
+++ b/drivers/net/dsa/mediatek/an8855.c
@@ -0,0 +1,1741 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Airoha AN8855 DSA Switch driver
+ * Copyright (C) 2023 Min Yao <min.yao@airoha.com>
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <linux/bitfield.h>
+#include <linux/ethtool.h>
+#include <linux/etherdevice.h>
+#include <linux/if_bridge.h>
+#include <linux/iopoll.h>
+#include <linux/netdevice.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <net/dsa.h>
+
+#include "an8855.h"
+#include "mt7530-lib.h"
+
+static const struct mt7530_reg_field an8855_fields[] = {
+ { MT7530_BC_FFP, REG_FIELD(AN8855_BCF, 0, 7) },
+ { MT7530_UNM_FFP, REG_FIELD(AN8855_UNMF, 0, 7) },
+ { MT7530_UNU_FFP, REG_FIELD(AN8855_UNUF, 0, 7) },
+
+ { MT7530_CCR_MIB_ENABLE, REG_FIELD(AN8855_MIB_CCR, 31, 31) },
+ { MT7530_CCR_RX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 7, 7) },
+ { MT7530_CCR_RX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 6, 6) },
+ { MT7530_CCR_TX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 5, 5) },
+ { MT7530_CCR_TX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 4, 4) },
+
+ { MT7530_BPDU_EG_TAG, REG_FIELD(AN8855_BPC, 9, 11) },
+ { MT7530_BPDU_PORT_FW, REG_FIELD(AN8855_BPC, 0, 2) },
+ { MT7530_PAE_BPDU_FR, REG_FIELD(AN8855_PAC, 28, 28) },
+ { MT7530_PAE_EG_TAG, REG_FIELD(AN8855_PAC, 25, 27) },
+ { MT7530_PAE_PORT_FW, REG_FIELD(AN8855_PAC, 16, 18) },
+ { MT7530_R01_BPDU_FR, REG_FIELD(AN8855_RGAC1, 12, 12) },
+ { MT7530_R01_EG_TAG, REG_FIELD(AN8855_RGAC1, 9, 11) },
+ { MT7530_R01_PORT_FW, REG_FIELD(AN8855_RGAC1, 0, 2) },
+ { MT7530_R02_BPDU_FR, REG_FIELD(AN8855_RGAC1, 28, 28) },
+ { MT7530_R02_EG_TAG, REG_FIELD(AN8855_RGAC1, 25, 27) },
+ { MT7530_R02_PORT_FW, REG_FIELD(AN8855_RGAC1, 16, 18) },
+ { MT7530_R03_BPDU_FR, REG_FIELD(AN8855_RGAC2, 12, 12) },
+ { MT7530_R03_EG_TAG, REG_FIELD(AN8855_RGAC2, 9, 11) },
+ { MT7530_R03_PORT_FW, REG_FIELD(AN8855_RGAC2, 0, 2) },
+ { MT7530_R0E_BPDU_FR, REG_FIELD(AN8855_RGAC2, 28, 28) },
+ { MT7530_R0E_EG_TAG, REG_FIELD(AN8855_RGAC2, 25, 27) },
+ { MT7530_R0E_PORT_FW, REG_FIELD(AN8855_RGAC2, 16, 18) },
+
+ { MT7530_VAWD_IVL_MAC, REG_FIELD(AN8855_VAWD0, 5, 5) },
+ { MT7530_VAWD_EG_CON, REG_FIELD(AN8855_VAWD0, 11, 11) },
+ { MT7530_VAWD_VTAG_EN, REG_FIELD(AN8855_VAWD0, 10, 10) },
+ { MT7530_VAWD_PORT_MEM, REG_FIELD(AN8855_VAWD0, 26, 31) },
+ { MT7530_VAWD_FID, REG_FIELD(AN8855_VAWD0, 1, 4) },
+ { MT7530_VAWD_VLAN_VALID, REG_FIELD(AN8855_VAWD0, 0, 0) },
+ { __MT7530_VAWD1, REG_FIELD(AN8855_VAWD0, 0, 31) },
+
+ { MT7530_VAWD_ETAG, REG_FIELD(AN8855_VAWD0, 12, 23) },
+ { __MT7530_VAWD2, REG_FIELD(AN8855_VAWD1, 0, 31) },
+
+ { MT7530_VTCR_BUSY, REG_FIELD(AN8855_VTCR, 31, 31) },
+ { MT7530_VTCR_FUNC, REG_FIELD(AN8855_VTCR, 12, 15) },
+ { MT7530_VTCR_VID, REG_FIELD(AN8855_VTCR, 0, 11) },
+
+ { MT7530_ATWD_CVID, REG_FIELD(AN8855_ATWD, 16, 27), },
+ { MT7530_ATWD_IVL, REG_FIELD(AN8855_ATWD, 15, 15), },
+ { MT7530_ATWD_FID, REG_FIELD(AN8855_ATWD, 28, 31), },
+ { MT7530_ATWD_AGE_TIMER, REG_FIELD(AN8855_ATA2, 0, 8), },
+ { MT7530_ATWD_PORT_MAP, REG_FIELD(AN8855_ATWD2, 0, 7), },
+ { AN8855_ATWD_TYPE, REG_FIELD(AN8855_ATA2, 9, 9), },
+ { AN8855_ATWD_VLD, REG_FIELD(AN8855_ATWD, 0, 0), },
+ { MT7530_ATWD_MAC_BYTE_5, REG_FIELD(AN8855_ATA2, 16, 23), },
+ { MT7530_ATWD_MAC_BYTE_4, REG_FIELD(AN8855_ATA2, 24, 31), },
+ { MT7530_ATWD_MAC_BYTE_3, REG_FIELD(AN8855_ATA1, 0, 7), },
+ { MT7530_ATWD_MAC_BYTE_2, REG_FIELD(AN8855_ATA1, 8, 15), },
+ { MT7530_ATWD_MAC_BYTE_1, REG_FIELD(AN8855_ATA1, 16, 23), },
+ { MT7530_ATWD_MAC_BYTE_0, REG_FIELD(AN8855_ATA1, 24, 31), },
+
+ { __MT7530_ATWD1, REG_FIELD(AN8855_ATWD, 0, 31), },
+ { __MT7530_ATWD2, REG_FIELD(AN8855_ATWD2, 0, 31), },
+ { __MT7530_ATWD3, REG_FIELD(AN8855_ATA1, 0, 31), },
+ { __MT7530_ATWD4, REG_FIELD(AN8855_ATA2, 0, 31), },
+
+ { MT7530_ATRD_CVID, REG_FIELD(AN8855_ATRD0, 10, 21), },
+ { MT7530_ATRD_AGE_TIMER, REG_FIELD(AN8855_ATRD1, 3, 11), },
+ { MT7530_ATRD_PORT_MAP, REG_FIELD(AN8855_ATRD3, 0, 7), },
+ { AN8855_ATRD_ARP, REG_FIELD(AN8855_ATRD0, 1, 2), },
+ { MT7530_ATRD_MAC_BYTE_5, REG_FIELD(AN8855_ATRD1, 16, 23), },
+ { MT7530_ATRD_MAC_BYTE_4, REG_FIELD(AN8855_ATRD1, 24, 31), },
+ { MT7530_ATRD_MAC_BYTE_3, REG_FIELD(AN8855_ATRD2, 0, 7), },
+ { MT7530_ATRD_MAC_BYTE_2, REG_FIELD(AN8855_ATRD2, 8, 15), },
+ { MT7530_ATRD_MAC_BYTE_1, REG_FIELD(AN8855_ATRD2, 16, 23), },
+ { MT7530_ATRD_MAC_BYTE_0, REG_FIELD(AN8855_ATRD2, 24, 31), },
+
+ { MT7530_ATC_BUSY, REG_FIELD(AN8855_ATC, 31, 31), },
+ { MT7530_ATC_MAT, REG_FIELD(AN8855_ATC, 7, 11), },
+ { MT7530_ATC_CMD, REG_FIELD(AN8855_ATC, 0, 2), },
+ { __MT7530_ATC, REG_FIELD(AN8855_ATC, 0, 31), },
+
+ { MT7530_MIRROR_EN, REG_FIELD(AN8855_MIR, 7, 7) },
+ { MT7530_MIRROR_PORT, REG_FIELD(AN8855_MIR, 0, 4) },
+
+ { MT7530_SSP_FID_PST, REG_FIELD_ID(AN8855_SSP, 0, 15, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PCR_PORT_TX_MIR, REG_FIELD_ID(AN8855_PCR, 20, 20, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PCR_PORT_RX_MIR, REG_FIELD_ID(AN8855_PCR, 16, 16, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PCR_PORT_VLAN, REG_FIELD_ID(AN8855_PCR, 0, 1, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PCR_MATRIX, REG_FIELD_ID(AN8855_PORTMATRIX, 0, 5, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PSC_SA_DIS, REG_FIELD_ID(AN8855_PSC, 4, 4, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PVC_EG_TAG, REG_FIELD_ID(AN8855_PVC, 8, 10, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PVC_VLAN_ATTR, REG_FIELD_ID(AN8855_PVC, 6, 7, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PVC_ACC_FRM, REG_FIELD_ID(AN8855_PVC, 0, 1, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PPBV1_G0_PORT_VID, REG_FIELD_ID(AN8855_PPBV1, 0, 11, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_PVID_G0_PORT_VID, REG_FIELD_ID(AN8855_PVID, 0, 11, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_GMACCR_MAX_RX_JUMBO, REG_FIELD(AN8855_GMACCR, 4, 7) },
+ { MT7530_GMACCR_MAX_RX_PKT_LEN, REG_FIELD(AN8855_GMACCR, 0, 1) },
+
+ { MT7530_MIB_TX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_TX_CRC_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_UNICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_BROADCAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_SINGLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_SINGLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_MULTIPLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTIPLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_DEFERRED, REG_FIELD_ID(AN8855_PORT_MIB_TX_DEFERRED, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_LATE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_LATE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_EXCESSIVE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_TX_PAUSE, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_64, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_OVERSIZE_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_OVERSIZE_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_FILTERING, REG_FIELD_ID(AN8855_PORT_MIB_RX_FILTERING, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_MULTICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_BROADCAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_ALIGN_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_ALIGN_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_CRC_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_UNDER_SIZE_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNDER_SIZE_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_FRAG_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_FRAG_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_OVER_SZ_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_OVER_SZ_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_JABBER_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_JABBER_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_RX_PAUSE, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_64, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_CTRL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_CTRL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_INGRESS_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_INGRESS_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_ARL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_ARL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_FLOW_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_FLOW_CONTROL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_WRED_DROP, REG_FIELD_ID(AN8855_PORT_MIB_WRED_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_MIRROR_DROP, REG_FIELD_ID(AN8855_PORT_MIB_MIRROR_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_PORT_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_PORT_CONTROL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+};
+
+static const struct mt7530_mib_desc an8855_mib[] = {
+ MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),
+ MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"),
+ MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"),
+ MIB_DESC(AN8855_MIB_TX_OVERSIZE_DROP, -1, "TxOversizeDrop"),
+ MIB_DESC(AN8855_MIB_TX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, "TxBadPktBytes"),
+ MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"),
+ MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"),
+ MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"),
+ MIB_DESC(MT7530_MIB_RX_CTRL_DROP, -1, "RxCtrlDrop"),
+ MIB_DESC(MT7530_MIB_RX_INGRESS_DROP, -1, "RxIngressDrop"),
+ MIB_DESC(MT7530_MIB_RX_ARL_DROP, -1, "RxArlDrop"),
+ MIB_DESC(AN8855_MIB_FLOW_CONTROL_DROP, -1, "FlowControlDrop"),
+ MIB_DESC(AN8855_MIB_WRED_DROP, -1, "WredDrop"),
+ MIB_DESC(AN8855_MIB_MIRROR_DROP, -1, "MirrorDrop"),
+ MIB_DESC(AN8855_MIB_RX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, "RxBadPktBytes"),
+ MIB_DESC(AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, -1, "RxsFlowSamplingPktDrop"),
+ MIB_DESC(AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, -1, "RxsFlowTotalPktDrop"),
+ MIB_DESC(AN8855_MIB_PORT_CONTROL_DROP, -1, "PortControlDrop"),
+};
+
+static void
+an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
+{
+ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct an8855_priv *priv = ds->priv;
+ bool learning = false;
+ int ret;
+
+ mt7530_lib_stp_state_set(&priv->lib_priv, port, state);
+
+ switch (state) {
+ case BR_STATE_LEARNING:
+ case BR_STATE_FORWARDING:
+ learning = dp->learning;
+ fallthrough;
+ default:
+ break;
+ }
+
+ ret = regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS,
+ learning ? 0 : AN8855_SA_DIS);
+ if (ret)
+ dev_err(priv->ds->dev, "failed to update learn reg: %d\n", ret);
+}
+
+static void an8855_port_fast_age(struct dsa_switch *ds, int port)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* Set to clean Dynamic entry */
+ ret = regmap_write(priv->regmap, AN8855_ATA2, AN8855_ATA2_TYPE);
+ if (ret) {
+ dev_err(priv->ds->dev, "failed to update ATA2 reg: %d\n", ret);
+ goto exit;
+ }
+
+ /* Set Port */
+ ret = regmap_write(priv->regmap, AN8855_ATWD2,
+ FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
+ if (ret) {
+ dev_err(priv->ds->dev, "failed to update ATWD2 reg: %d\n", ret);
+ goto exit;
+ }
+
+ /* Flush Dynamic entry at port */
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+ AN8855_FDB_MAT_MAC_TYPE_PORT, NULL);
+ if (ret)
+ dev_err(priv->ds->dev, "failed to send FDB cmd: %d\n", ret);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
+ BR_BCAST_FLOOD | BR_ISOLATED))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int an8855_port_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_bridge_flags(&priv->lib_priv, port, flags,
+ extack);
+}
+
+static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
+{
+ struct an8855_priv *priv = ds->priv;
+ u32 age_count, age_unit, val;
+
+ /* Convert msec in AN8855_L2_AGING_MS_CONSTANT counter */
+ val = msecs / AN8855_L2_AGING_MS_CONSTANT;
+
+ /* Derive the count unit */
+ age_unit = DIV_ROUND_UP(val, FIELD_MAX(AN8855_AGE_CNT) + 1) - 1;
+ if (age_unit > FIELD_MAX(AN8855_AGE_UNIT))
+ age_unit = FIELD_MAX(AN8855_AGE_UNIT);
+
+ /* Get the count in unit, age_unit is always incremented by 1 internally */
+ age_count = DIV_ROUND_UP(val, age_unit + 1) - 1;
+
+ return regmap_update_bits(priv->regmap, AN8855_AAC,
+ AN8855_AGE_CNT | AN8855_AGE_UNIT,
+ FIELD_PREP(AN8855_AGE_CNT, age_count) |
+ FIELD_PREP(AN8855_AGE_UNIT, age_unit));
+}
+
+static int an8855_port_bridge_join(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge,
+ bool *tx_fwd_offload,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_bridge_join(&priv->lib_priv, port, bridge,
+ tx_fwd_offload, extack);
+}
+
+static void an8855_port_bridge_leave(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_bridge_leave(&priv->lib_priv, port, bridge);
+}
+
+static int an8855_port_fdb_add(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_fdb_add(&priv->lib_priv, port, addr, vid, db);
+}
+
+static int an8855_port_fdb_del(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_fdb_del(&priv->lib_priv, port, addr, vid, db);
+}
+
+static int an8855_port_fdb_dump(struct dsa_switch *ds, int port,
+ dsa_fdb_dump_cb_t *cb, void *data)
+{
+ struct an8855_priv *priv = ds->priv;
+ int banks, count = 0;
+ u32 rsp;
+ int ret;
+ int i;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* Load search port */
+ ret = regmap_write(priv->regmap, AN8855_ATWD2,
+ FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
+ if (ret)
+ goto exit;
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START,
+ AN8855_FDB_MAT_MAC_PORT, &rsp);
+ if (ret < 0)
+ goto exit;
+
+ do {
+ /* From response get the number of banks to read, exit if 0 */
+ banks = FIELD_GET(AN8855_ATC_HIT, rsp);
+ if (!banks)
+ break;
+
+ /* Each banks have 4 entry */
+ for (i = 0; i < 4; i++) {
+ struct mt7530_fdb _fdb = { };
+
+ count++;
+
+ /* Check if bank is present */
+ if (!(banks & BIT(i)))
+ continue;
+
+ /* Select bank entry index */
+ ret = regmap_write(priv->regmap, AN8855_ATRDS,
+ FIELD_PREP(AN8855_ATRD_SEL, i));
+ if (ret)
+ break;
+ /* wait 1ms for the bank entry to be filled */
+ usleep_range(1000, 1500);
+ mt7530_lib_fdb_read(&priv->lib_priv, &_fdb);
+
+ ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, data);
+ if (ret < 0)
+ break;
+ }
+
+ /* Stop if reached max FDB number */
+ if (ret < 0 || count >= AN8855_NUM_FDB_RECORDS)
+ break;
+
+ /* Read next bank */
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_NEXT,
+ AN8855_FDB_MAT_MAC_PORT, &rsp);
+ if (ret < 0)
+ break;
+ } while (true);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+ return ret;
+}
+
+static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port,
+ bool vlan_filtering,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_vlan_filtering(&priv->lib_priv, port,
+ vlan_filtering,
+ extack);
+}
+
+static int an8855_port_vlan_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_vlan_add(&priv->lib_priv, port, vlan, extack);
+}
+
+static int an8855_port_vlan_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_vlan_del(&priv->lib_priv, port, vlan);
+}
+
+static int an8855_port_mdb_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_mdb_add(&priv->lib_priv, port, mdb, db);
+}
+
+static int an8855_port_mdb_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_mdb_del(&priv->lib_priv, port, mdb, db);
+}
+
+static int an8855_port_change_mtu(struct dsa_switch *ds, int port,
+ int new_mtu)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_change_mtu(&priv->lib_priv, port, new_mtu);
+}
+
+static int an8855_port_max_mtu(struct dsa_switch *ds, int port)
+{
+ return AN8855_MAX_MTU;
+}
+
+static void an8855_get_strings(struct dsa_switch *ds, int port,
+ u32 stringset, uint8_t *data)
+{
+ int i;
+
+ if (stringset != ETH_SS_STATS)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(an8855_mib); i++)
+ ethtool_puts(&data, an8855_mib[i].name);
+}
+
+static void an8855_get_ethtool_stats(struct dsa_switch *ds, int port,
+ uint64_t *data)
+{
+ struct an8855_priv *priv = ds->priv;
+ const struct mt7530_mib_desc *mib;
+ struct mt7530_lib_priv *lib_priv;
+ int i;
+
+ lib_priv = &priv->lib_priv;
+ for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) {
+ struct regmap_field *high = NULL;
+
+ mib = &an8855_mib[i];
+ if (mib->field_high != -1)
+ high = lib_priv->fields[mib->field_high];
+
+ mt7530_lib_read_port_stats(lib_priv->fields[mib->field_low],
+ high, port, data + i);
+ }
+}
+
+static int an8855_get_sset_count(struct dsa_switch *ds, int port,
+ int sset)
+{
+ if (sset != ETH_SS_STATS)
+ return -EOPNOTSUPP;
+
+ return ARRAY_SIZE(an8855_mib);
+}
+
+static void an8855_get_eth_mac_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_mac_stats *mac_stats)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_get_eth_mac_stats(&priv->lib_priv, port, mac_stats);
+}
+
+static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = {
+ { 0, 64 },
+ { 65, 127 },
+ { 128, 255 },
+ { 256, 511 },
+ { 512, 1023 },
+ { 1024, 1518 },
+ { 1519, AN8855_MAX_MTU },
+ {}
+};
+
+static const struct mt7530_rmon_hist an8855_rmon_hist_info = {
+ .ranges_fields = (unsigned int []){
+ MT7530_MIB_RX_PKT_SZ_64,
+ MT7530_MIB_RX_PKT_SZ_65_TO_127,
+ MT7530_MIB_RX_PKT_SZ_128_TO_255,
+ MT7530_MIB_RX_PKT_SZ_256_TO_511,
+ MT7530_MIB_RX_PKT_SZ_512_TO_1023,
+ AN8855_MIB_RX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_RX_PKT_SZ_1519_TO_MAX,
+ },
+ .ranges_tx_fields = (unsigned int []){
+ MT7530_MIB_TX_PKT_SZ_64,
+ MT7530_MIB_TX_PKT_SZ_65_TO_127,
+ MT7530_MIB_TX_PKT_SZ_128_TO_255,
+ MT7530_MIB_TX_PKT_SZ_256_TO_511,
+ MT7530_MIB_TX_PKT_SZ_512_TO_1023,
+ AN8855_MIB_TX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_TX_PKT_SZ_1519_TO_MAX,
+ },
+ .ranges = an8855_rmon_ranges,
+ .num_ranges = ARRAY_SIZE(an8855_rmon_ranges) - 1,
+};
+
+static void an8855_get_rmon_stats(struct dsa_switch *ds, int port,
+ struct ethtool_rmon_stats *rmon_stats,
+ const struct ethtool_rmon_hist_range **ranges)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_get_rmon_stats(&priv->lib_priv, port, rmon_stats, ranges,
+ &an8855_rmon_hist_info);
+}
+
+static void an8855_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_ctrl_stats *ctrl_stats)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ mt7530_lib_get_eth_ctrl_stats(&priv->lib_priv, port, ctrl_stats);
+}
+
+static int an8855_port_mirror_add(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_mirror_add(&priv->lib_priv, port, mirror, ingress, extack);
+}
+
+static void an8855_port_mirror_del(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ mt7530_lib_port_mirror_del(&priv->lib_priv, port, mirror);
+}
+
+static int an8855_port_enable(struct dsa_switch *ds, int port,
+ struct phy_device *phy)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+ priv->ports[port].enable = true;
+ ret = regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+ mutex_unlock(&priv->reg_mutex);
+
+ return ret;
+}
+
+static void an8855_port_disable(struct dsa_switch *ds, int port)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+ priv->ports[port].enable = false;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ dev_err(priv->ds->dev, "failed to disable port: %d\n", ret);
+}
+
+static int an8855_set_mac_eee(struct dsa_switch *ds, int port,
+ struct ethtool_keee *e)
+{
+ if (e->tx_lpi_timer > 0xFFF)
+ return -EINVAL;
+
+ return 0;
+}
+
+static enum dsa_tag_protocol an8855_get_tag_protocol(struct dsa_switch *ds,
+ int port,
+ enum dsa_tag_protocol mp)
+{
+ return DSA_TAG_PROTO_AIROHA;
+}
+
+static int an8855_setup(struct dsa_switch *ds)
+{
+ struct an8855_priv *priv = ds->priv;
+ struct dsa_port *dp;
+ int ret;
+
+ /* Enable and reset MIB counters */
+ mt7530_lib_mib_reset(&priv->lib_priv);
+
+ dsa_switch_for_each_user_port(dp, ds) {
+ /* Disable MAC by default on all user ports */
+ an8855_port_disable(ds, dp->index);
+
+ /* Individual user ports get connected to CPU port only */
+ ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(dp->index),
+ FIELD_PREP(AN8855_PORTMATRIX_MASK, BIT(AN8855_CPU_PORT)));
+ if (ret)
+ return ret;
+
+ /* Disable Broadcast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_BCF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Disable Unknown Unicast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNUF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Disable Unknown Multicast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNMF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNIPMF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Set default PVID to on all user ports */
+ mt7530_port_set_pvid(&priv->lib_priv, dp->index, AN8855_PORT_VID_DEFAULT);
+ }
+
+ /* Enable Airoha header mode on the cpu port */
+ ret = regmap_write(priv->regmap, AN8855_PVC_P(AN8855_CPU_PORT),
+ AN8855_PORT_SPEC_REPLACE_MODE | AN8855_PORT_SPEC_TAG);
+ if (ret)
+ return ret;
+
+ /* Unknown multicast frame forwarding to the cpu port */
+ ret = regmap_write(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Set CPU port number */
+ ret = regmap_update_bits(priv->regmap, AN8855_MFC,
+ AN8855_CPU_EN | AN8855_CPU_PORT_IDX,
+ AN8855_CPU_EN |
+ FIELD_PREP(AN8855_CPU_PORT_IDX, AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* CPU port gets connected to all user ports of
+ * the switch.
+ */
+ ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(AN8855_CPU_PORT),
+ FIELD_PREP(AN8855_PORTMATRIX_MASK, dsa_user_ports(ds)));
+ if (ret)
+ return ret;
+
+ /* CPU port is set to fallback mode to let untagged
+ * frames pass through.
+ */
+ ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(AN8855_CPU_PORT),
+ AN8855_PORT_VLAN,
+ FIELD_PREP(AN8855_PORT_VLAN, AN8855_PORT_FALLBACK_MODE));
+ if (ret)
+ return ret;
+
+ /* Enable Broadcast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_BCF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Enable Unknown Unicast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_UNUF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Enable Unknown Multicast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_UNIPMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Setup Trap special frame to CPU rules */
+ mt7530_lib_trap_frames(&priv->lib_priv);
+
+ dsa_switch_for_each_port(dp, ds) {
+ /* Disable Learning on all ports.
+ * Learning on CPU is disabled for fdb isolation and handled by
+ * assisted_learning_on_cpu_port.
+ */
+ ret = regmap_set_bits(priv->regmap, AN8855_PSC_P(dp->index),
+ AN8855_SA_DIS);
+ if (ret)
+ return ret;
+
+ /* Enable consistent egress tag (for VLAN unware VLAN-passthrough) */
+ ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(dp->index),
+ AN8855_PVC_EG_TAG,
+ FIELD_PREP(AN8855_PVC_EG_TAG, AN8855_VLAN_EG_CONSISTENT));
+ if (ret)
+ return ret;
+ }
+
+ /* Setup VLAN for Default PVID */
+ ret = mt7530_lib_setup_vlan0(&priv->lib_priv);
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_CKGCR,
+ AN8855_CKG_LNKDN_GLB_STOP | AN8855_CKG_LNKDN_PORT_STOP);
+ if (ret)
+ return ret;
+
+ /* Flush the FDB table */
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+ AN8855_FDB_MAT_ALL, NULL);
+ if (ret < 0)
+ return ret;
+
+ /* Set min a max ageing value supported */
+ ds->ageing_time_min = AN8855_L2_AGING_MS_CONSTANT;
+ ds->ageing_time_max = FIELD_MAX(AN8855_AGE_CNT) *
+ FIELD_MAX(AN8855_AGE_UNIT) *
+ AN8855_L2_AGING_MS_CONSTANT;
+
+ /* User reported problem with WiFi roaming and
+ * ethernet port. Enabling assisted learning fix
+ * the issue.
+ */
+ ds->assisted_learning_on_cpu_port = true;
+
+ return 0;
+}
+
+static struct phylink_pcs *an8855_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return &priv->pcs;
+ default:
+ return NULL;
+ }
+}
+
+static void an8855_phylink_mac_config(struct phylink_config *config,
+ unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+ struct an8855_priv *priv;
+ int port = dp->index;
+
+ priv = ds->priv;
+
+ /* Nothing to configure for internal ports */
+ if (port != 5)
+ return;
+
+ mutex_lock(&priv->reg_mutex);
+ regmap_update_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_IFG_XMIT | AN8855_PMCR_MAC_MODE |
+ AN8855_PMCR_BACKOFF_EN | AN8855_PMCR_BACKPR_EN,
+ FIELD_PREP(AN8855_PMCR_IFG_XMIT, 0x1) |
+ AN8855_PMCR_MAC_MODE | AN8855_PMCR_BACKOFF_EN |
+ AN8855_PMCR_BACKPR_EN);
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+{
+ struct an8855_priv *priv = ds->priv;
+ u32 reg = 0;
+ int ret;
+
+ switch (port) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
+ case 5:
+ phy_interface_set_rgmii(config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ config->supported_interfaces);
+ break;
+ }
+
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;
+
+ ret = regmap_read(priv->regmap, AN8855_CKGCR, ®);
+ if (ret)
+ dev_err(ds->dev, "failed to read EEE LPI timer\n");
+
+ memcpy(config->lpi_interfaces, config->supported_interfaces,
+ sizeof(config->lpi_interfaces));
+ config->lpi_capabilities = MAC_100FD | MAC_1000FD;
+ /* Global LPI TXIDLE Threshold, default 60ms (unit 2us) */
+ config->lpi_timer_default = FIELD_GET(AN8855_LPI_TXIDLE_THD_MASK, reg) *
+ AN8855_TX_LPI_UNIT;
+
+ config->eee_enabled_default = true;
+}
+
+static void an8855_phylink_mac_link_down(struct phylink_config *config,
+ unsigned int mode,
+ phy_interface_t interface)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* With autoneg just disable TX/RX else also force link down */
+ if (phylink_autoneg_inband(mode)) {
+ regmap_clear_bits(priv->regmap, AN8855_PMCR_P(dp->index),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+ } else {
+ regmap_update_bits(priv->regmap, AN8855_PMCR_P(dp->index),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN |
+ AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK,
+ AN8855_PMCR_FORCE_MODE);
+ }
+
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_mac_link_up(struct phylink_config *config,
+ struct phy_device *phydev, unsigned int mode,
+ phy_interface_t interface, int speed,
+ int duplex, bool tx_pause, bool rx_pause)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+ int port = dp->index;
+ u32 reg = 0;
+
+ mutex_lock(&priv->reg_mutex);
+
+ regmap_read(priv->regmap, AN8855_PMCR_P(port), ®);
+ if (phylink_autoneg_inband(mode)) {
+ reg &= ~AN8855_PMCR_FORCE_MODE;
+ } else {
+ reg |= AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK;
+
+ reg &= ~AN8855_PMCR_FORCE_SPEED;
+ switch (speed) {
+ case SPEED_10:
+ reg |= AN8855_PMCR_FORCE_SPEED_10;
+ break;
+ case SPEED_100:
+ reg |= AN8855_PMCR_FORCE_SPEED_100;
+ break;
+ case SPEED_1000:
+ reg |= AN8855_PMCR_FORCE_SPEED_1000;
+ break;
+ case SPEED_2500:
+ reg |= AN8855_PMCR_FORCE_SPEED_2500;
+ break;
+ case SPEED_5000:
+ dev_err(priv->ds->dev, "Missing support for 5G speed. Aborting...\n");
+ goto exit;
+ }
+
+ reg &= ~AN8855_PMCR_FORCE_FDX;
+ if (duplex == DUPLEX_FULL)
+ reg |= AN8855_PMCR_FORCE_FDX;
+
+ reg &= ~AN8855_PMCR_RX_FC_EN;
+ if (rx_pause || dsa_port_is_cpu(dp))
+ reg |= AN8855_PMCR_RX_FC_EN;
+
+ reg &= ~AN8855_PMCR_TX_FC_EN;
+ if (tx_pause || dsa_port_is_cpu(dp))
+ reg |= AN8855_PMCR_TX_FC_EN;
+ }
+
+ reg |= AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN;
+
+ regmap_write(priv->regmap, AN8855_PMCR_P(port), reg);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_mac_disable_tx_lpi(struct phylink_config *config)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+ int port = dp->index;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+ priv->tx_lpi_timer_ports[port] = 0;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_FORCE_EEE1G |
+ AN8855_PMCR_FORCE_EEE100);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ dev_err(dp->ds->dev, "failed to disable EEE for port %d\n",
+ port);
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_PMEEECR_P(port),
+ AN8855_LPI_MODE_EN);
+ if (ret)
+ dev_err(dp->ds->dev, "failed to disable LPI for port %d\n",
+ port);
+}
+
+static int an8855_phylink_mac_enable_tx_lpi(struct phylink_config *config,
+ u32 timer, bool tx_clock_stop)
+{
+ struct an8855_priv *priv;
+ struct dsa_switch *ds;
+ struct dsa_port *dp;
+ int port;
+ u32 val;
+ int ret;
+
+ dp = dsa_phylink_to_port(config);
+ port = dp->index;
+ ds = dp->ds;
+ priv = ds->priv;
+
+ /* TX LPI timer is global, find the highest timer
+ * across all port.
+ * If requested timer is 0, set to enter LPI immediately
+ * for the single port.
+ */
+ if (timer) {
+ int i;
+
+ /* Save requested timer and search the highest one */
+ mutex_lock(&priv->reg_mutex);
+ priv->tx_lpi_timer_ports[port] = timer;
+ for (i = 0; i < AN8855_NUM_PORTS; i++) {
+ if (!priv->ports[i].enable)
+ continue;
+
+ if (i == port)
+ continue;
+
+ if (timer < priv->tx_lpi_timer_ports[i])
+ timer = priv->tx_lpi_timer_ports[i];
+ }
+
+ timer /= AN8855_TX_LPI_UNIT;
+ if (FIELD_FIT(AN8855_LPI_TXIDLE_THD_MASK, timer))
+ val = FIELD_PREP(AN8855_LPI_TXIDLE_THD_MASK, timer);
+ else
+ val = AN8855_LPI_TXIDLE_THD_MASK;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_CKGCR,
+ AN8855_LPI_TXIDLE_THD_MASK, val);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret) {
+ dev_err(dp->ds->dev, "failed to set global LPI timer\n");
+ return ret;
+ }
+ } else {
+ ret = regmap_set_bits(priv->regmap, AN8855_PMEEECR_P(port),
+ AN8855_LPI_MODE_EN);
+ if (ret) {
+ dev_err(dp->ds->dev, "failed to enable LPI for port %d\n",
+ port);
+ return ret;
+ }
+ }
+
+ mutex_lock(&priv->reg_mutex);
+ ret = regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_FORCE_EEE1G |
+ AN8855_PMCR_FORCE_EEE100);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ dev_err(dp->ds->dev, "failed to enable EEE for port %d\n",
+ port);
+
+ return ret;
+}
+
+static unsigned int an8855_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ /* SGMII can be configured to use inband with AN result */
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
+
+ /* inband is not supported in 2500-baseX and must be disabled */
+ return LINK_INBAND_DISABLE;
+}
+
+static void an8855_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);
+ u32 val;
+ int ret;
+
+ ret = regmap_read(priv->regmap, AN8855_PMSR_P(AN8855_CPU_PORT), &val);
+ if (ret < 0) {
+ state->link = false;
+ return;
+ }
+
+ state->link = !!(val & AN8855_PMSR_LNK);
+ state->an_complete = state->link;
+ state->duplex = (val & AN8855_PMSR_DPX) ? DUPLEX_FULL :
+ DUPLEX_HALF;
+
+ switch (val & AN8855_PMSR_SPEED) {
+ case AN8855_PMSR_SPEED_10:
+ state->speed = SPEED_10;
+ break;
+ case AN8855_PMSR_SPEED_100:
+ state->speed = SPEED_100;
+ break;
+ case AN8855_PMSR_SPEED_1000:
+ state->speed = SPEED_1000;
+ break;
+ case AN8855_PMSR_SPEED_2500:
+ state->speed = SPEED_2500;
+ break;
+ case AN8855_PMSR_SPEED_5000:
+ dev_err(priv->ds->dev, "Switch doesn't support 5G speed. Setting Unknown.\n");
+ fallthrough;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ break;
+ }
+
+ if (val & AN8855_PMSR_RX_FC)
+ state->pause |= MLO_PAUSE_RX;
+ if (val & AN8855_PMSR_TX_FC)
+ state->pause |= MLO_PAUSE_TX;
+}
+
+static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);
+ u32 val;
+ int ret;
+
+ /* TX FIR - improve TX EYE */
+ ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_10,
+ AN8855_RG_DA_QP_TX_FIR_C2_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C2_FORCE |
+ AN8855_RG_DA_QP_TX_FIR_C1_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C1_FORCE,
+ AN8855_RG_DA_QP_TX_FIR_C2_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C2_FORCE, 0x4) |
+ AN8855_RG_DA_QP_TX_FIR_C1_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C1_FORCE, 0x0));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x0;
+ else
+ val = 0xd;
+ ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_11,
+ AN8855_RG_DA_QP_TX_FIR_C0B_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C0B_FORCE,
+ AN8855_RG_DA_QP_TX_FIR_C0B_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, val));
+ if (ret)
+ return ret;
+
+ /* RX CDR - improve RX Jitter Tolerance */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x5;
+ else
+ val = 0x6;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_BOT_LIM,
+ AN8855_RG_QP_CDR_LPF_KP_GAIN |
+ AN8855_RG_QP_CDR_LPF_KI_GAIN,
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_KP_GAIN, val) |
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_KI_GAIN, val));
+ if (ret)
+ return ret;
+
+ /* PLL */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x1;
+ else
+ val = 0x0;
+ ret = regmap_update_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_1,
+ AN8855_RG_TPHY_SPEED,
+ FIELD_PREP(AN8855_RG_TPHY_SPEED, val));
+ if (ret)
+ return ret;
+
+ /* PLL - LPF */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |
+ AN8855_RG_DA_QP_PLL_FBKSEL_INTF |
+ AN8855_RG_DA_QP_PLL_BR_INTF |
+ AN8855_RG_DA_QP_PLL_BPD_INTF |
+ AN8855_RG_DA_QP_PLL_BPA_INTF |
+ AN8855_RG_DA_QP_PLL_BC_INTF,
+ AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_FBKSEL_INTF, 0x0) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BR_INTF, 0x3) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BPD_INTF, 0x0) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BPA_INTF, 0x5) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BC_INTF, 0x1));
+ if (ret)
+ return ret;
+
+ /* PLL - ICO */
+ ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_4,
+ AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF);
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - CHP */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x6;
+ else
+ val = 0x4;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_IR_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_IR_INTF, val));
+ if (ret)
+ return ret;
+
+ /* PLL - PFD */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF |
+ AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF |
+ AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF, 0x1) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, 0x1));
+ if (ret)
+ return ret;
+
+ /* PLL - POSTDIV */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF |
+ AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF |
+ AN8855_RG_DA_QP_PLL_PCK_SEL_INTF,
+ AN8855_RG_DA_QP_PLL_PCK_SEL_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - SDM */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_SDM_HREN_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_SDM_IFM_INTF);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_SS_LCPLL_PWCTL_SETTING_2,
+ AN8855_RG_NCPO_ANA_MSB,
+ FIELD_PREP(AN8855_RG_NCPO_ANA_MSB, 0x1));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x7a000000;
+ else
+ val = 0x48000000;
+ ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_2,
+ FIELD_PREP(AN8855_RG_LCPLL_NCPO_VALUE, val));
+ if (ret)
+ return ret;
+ ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_PCW_1,
+ FIELD_PREP(AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_5,
+ AN8855_RG_LCPLL_NCPO_CHG);
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0,
+ AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - SS */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3,
+ AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_4,
+ AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3,
+ AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, 0x0));
+ if (ret)
+ return ret;
+
+ /* PLL - TDC */
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0,
+ AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD,
+ AN8855_RG_QP_PLL_SSC_TRI_EN);
+ if (ret)
+ return ret;
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD,
+ AN8855_RG_QP_PLL_SSC_PHASE_INI);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_RX_DAC_EN,
+ AN8855_RG_QP_SIGDET_HF,
+ FIELD_PREP(AN8855_RG_QP_SIGDET_HF, 0x2));
+ if (ret)
+ return ret;
+
+ /* TCL Disable (only for Co-SIM) */
+ ret = regmap_clear_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_0,
+ AN8855_RG_QP_EQ_RX500M_CK_SEL);
+ if (ret)
+ return ret;
+
+ /* TX Init */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x4;
+ else
+ val = 0x0;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_TX_MODE,
+ AN8855_RG_QP_TX_RESERVE |
+ AN8855_RG_QP_TX_MODE_16B_EN,
+ FIELD_PREP(AN8855_RG_QP_TX_RESERVE, val));
+ if (ret)
+ return ret;
+
+ /* RX Control/Init */
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_RXAFE_RESERVE,
+ AN8855_RG_QP_CDR_PD_10B_EN);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x1;
+ else
+ val = 0x2;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_MJV_LIM,
+ AN8855_RG_QP_CDR_LPF_RATIO,
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_RATIO, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_SETVALUE,
+ AN8855_RG_QP_CDR_PR_BUF_IN_SR |
+ AN8855_RG_QP_CDR_PR_BETA_SEL,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_BUF_IN_SR, 0x6) |
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_BETA_SEL, 0x1));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0xf;
+ else
+ val = 0xc;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,
+ AN8855_RG_QP_CDR_PR_DAC_BAND,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_DAC_BAND, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,
+ AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE |
+ AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, 0x19));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF,
+ AN8855_RG_QP_CDR_PHYCK_SEL |
+ AN8855_RG_QP_CDR_PHYCK_RSTB |
+ AN8855_RG_QP_CDR_PHYCK_DIV,
+ FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_SEL, 0x2) |
+ FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_DIV, 0x21));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,
+ AN8855_RG_QP_CDR_PR_XFICK_EN);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,
+ AN8855_RG_QP_CDR_PR_KBAND_DIV,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV, 0x4));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_26,
+ AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |
+ AN8855_RG_LINK_NE_EN |
+ AN8855_RG_LINK_ERRO_EN,
+ AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |
+ AN8855_RG_LINK_ERRO_EN);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_DLY_0,
+ AN8855_RG_QP_RX_SAOSC_EN_H_DLY |
+ AN8855_RG_QP_RX_PI_CAL_EN_H_DLY,
+ FIELD_PREP(AN8855_RG_QP_RX_SAOSC_EN_H_DLY, 0x3f) |
+ FIELD_PREP(AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, 0x6f));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_42,
+ AN8855_RG_QP_EQ_EN_DLY,
+ FIELD_PREP(AN8855_RG_QP_EQ_EN_DLY, 0x150));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_2,
+ AN8855_RG_QP_RX_EQ_EN_H_DLY,
+ FIELD_PREP(AN8855_RG_QP_RX_EQ_EN_H_DLY, 0x150));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_9,
+ AN8855_RG_QP_EQ_LEQOSC_DLYCNT,
+ FIELD_PREP(AN8855_RG_QP_EQ_LEQOSC_DLYCNT, 0x1));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_8,
+ AN8855_RG_DA_QP_SAOSC_DONE_TIME |
+ AN8855_RG_DA_QP_LEQOS_EN_TIME,
+ FIELD_PREP(AN8855_RG_DA_QP_SAOSC_DONE_TIME, 0x200) |
+ FIELD_PREP(AN8855_RG_DA_QP_LEQOS_EN_TIME, 0xfff));
+ if (ret)
+ return ret;
+
+ /* Frequency meter */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x10;
+ else
+ val = 0x28;
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_5,
+ AN8855_RG_FREDET_CHK_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_CHK_CYCLE, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_6,
+ AN8855_RG_FREDET_GOLDEN_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_GOLDEN_CYCLE, 0x64));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_7,
+ AN8855_RG_FREDET_TOLERATE_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_TOLERATE_CYCLE, 0x2710));
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_0,
+ AN8855_RG_PHYA_AUTO_INIT);
+ if (ret)
+ return ret;
+
+ /* PCS Init */
+ if (interface == PHY_INTERFACE_MODE_SGMII &&
+ neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) {
+ ret = regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0,
+ AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RG_HSGMII_PCS_CTROL_1,
+ AN8855_RG_TBI_10B_MODE);
+ if (ret)
+ return ret;
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ /* Set AN Ability - Interrupt */
+ ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN_FORCE_CL37,
+ AN8855_RG_FORCE_AN_DONE);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN_13,
+ AN8855_SGMII_REMOTE_FAULT_DIS |
+ AN8855_SGMII_IF_MODE,
+ AN8855_SGMII_REMOTE_FAULT_DIS |
+ FIELD_PREP(AN8855_SGMII_IF_MODE, 0xb));
+ if (ret)
+ return ret;
+ }
+
+ /* Rate Adaption - GMII path config. */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_DIS_MII_MODE);
+ if (ret)
+ return ret;
+ } else {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ ret = regmap_set_bits(priv->regmap, AN8855_MII_RA_AN_ENABLE,
+ AN8855_RG_P0_RA_AN_EN);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_AN_SGMII_MODE_FORCE,
+ AN8855_RG_FORCE_CUR_SGMII_MODE |
+ AN8855_RG_FORCE_CUR_SGMII_SEL,
+ AN8855_RG_FORCE_CUR_SGMII_SEL);
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_MII_RA_RX_EN |
+ AN8855_RG_P0_MII_RA_TX_EN |
+ AN8855_RG_P0_MII_RA_RX_MODE |
+ AN8855_RG_P0_MII_RA_TX_MODE);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_MII_MODE);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_RATE_ADAPT_CTRL_0,
+ AN8855_RG_RATE_ADAPT_RX_BYPASS |
+ AN8855_RG_RATE_ADAPT_TX_BYPASS |
+ AN8855_RG_RATE_ADAPT_RX_EN |
+ AN8855_RG_RATE_ADAPT_TX_EN);
+ if (ret)
+ return ret;
+
+ /* Disable AN if not in autoneg */
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN0, BMCR_ANENABLE,
+ neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE :
+ 0);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ /* Follow SDK init flow with restarting AN after AN enable */
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN0,
+ BMCR_ANRESTART);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_set_bits(priv->regmap, AN8855_PHY_RX_FORCE_CTRL_0,
+ AN8855_RG_FORCE_TXC_SEL);
+ if (ret)
+ return ret;
+ }
+ }
+
+ /* Force Speed with fixed-link or 2500base-x as doesn't support aneg */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX ||
+ neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = AN8855_RG_LINK_MODE_P0_SPEED_2500;
+ else
+ val = AN8855_RG_LINK_MODE_P0_SPEED_1000;
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_STS_CTRL_0,
+ AN8855_RG_LINK_MODE_P0 |
+ AN8855_RG_FORCE_SPD_MODE_P0,
+ val | AN8855_RG_FORCE_SPD_MODE_P0);
+ if (ret)
+ return ret;
+ }
+
+ /* bypass flow control to MAC */
+ ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_0,
+ AN8855_RG_DPX_STS_P3 | AN8855_RG_DPX_STS_P2 |
+ AN8855_RG_DPX_STS_P1 | AN8855_RG_TXFC_STS_P0 |
+ AN8855_RG_RXFC_STS_P0 | AN8855_RG_DPX_STS_P0);
+ if (ret)
+ return ret;
+ ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_2,
+ AN8855_RG_RXFC_AN_BYPASS_P3 |
+ AN8855_RG_RXFC_AN_BYPASS_P2 |
+ AN8855_RG_RXFC_AN_BYPASS_P1 |
+ AN8855_RG_TXFC_AN_BYPASS_P3 |
+ AN8855_RG_TXFC_AN_BYPASS_P2 |
+ AN8855_RG_TXFC_AN_BYPASS_P1 |
+ AN8855_RG_DPX_AN_BYPASS_P3 |
+ AN8855_RG_DPX_AN_BYPASS_P2 |
+ AN8855_RG_DPX_AN_BYPASS_P1 |
+ AN8855_RG_DPX_AN_BYPASS_P0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void an8855_pcs_an_restart(struct phylink_pcs *pcs)
+{
+}
+
+static const struct phylink_pcs_ops an8855_pcs_ops = {
+ .pcs_inband_caps = an8855_pcs_inband_caps,
+ .pcs_get_state = an8855_pcs_get_state,
+ .pcs_config = an8855_pcs_config,
+ .pcs_an_restart = an8855_pcs_an_restart,
+};
+
+static const struct phylink_mac_ops an8855_phylink_mac_ops = {
+ .mac_select_pcs = an8855_phylink_mac_select_pcs,
+ .mac_config = an8855_phylink_mac_config,
+ .mac_link_down = an8855_phylink_mac_link_down,
+ .mac_link_up = an8855_phylink_mac_link_up,
+ .mac_disable_tx_lpi = an8855_phylink_mac_disable_tx_lpi,
+ .mac_enable_tx_lpi = an8855_phylink_mac_enable_tx_lpi,
+};
+
+static const struct dsa_switch_ops an8855_switch_ops = {
+ .get_tag_protocol = an8855_get_tag_protocol,
+ .setup = an8855_setup,
+ .phylink_get_caps = an8855_phylink_get_caps,
+ .get_strings = an8855_get_strings,
+ .get_ethtool_stats = an8855_get_ethtool_stats,
+ .get_sset_count = an8855_get_sset_count,
+ .get_eth_mac_stats = an8855_get_eth_mac_stats,
+ .get_eth_ctrl_stats = an8855_get_eth_ctrl_stats,
+ .get_rmon_stats = an8855_get_rmon_stats,
+ .port_enable = an8855_port_enable,
+ .port_disable = an8855_port_disable,
+ .set_ageing_time = an8855_set_ageing_time,
+ .port_bridge_join = an8855_port_bridge_join,
+ .port_bridge_leave = an8855_port_bridge_leave,
+ .port_fast_age = an8855_port_fast_age,
+ .port_stp_state_set = an8855_port_stp_state_set,
+ .port_pre_bridge_flags = an8855_port_pre_bridge_flags,
+ .port_bridge_flags = an8855_port_bridge_flags,
+ .port_vlan_filtering = an8855_port_vlan_filtering,
+ .port_vlan_add = an8855_port_vlan_add,
+ .port_vlan_del = an8855_port_vlan_del,
+ .port_fdb_add = an8855_port_fdb_add,
+ .port_fdb_del = an8855_port_fdb_del,
+ .port_fdb_dump = an8855_port_fdb_dump,
+ .port_mdb_add = an8855_port_mdb_add,
+ .port_mdb_del = an8855_port_mdb_del,
+ .port_change_mtu = an8855_port_change_mtu,
+ .port_max_mtu = an8855_port_max_mtu,
+ .port_mirror_add = an8855_port_mirror_add,
+ .port_mirror_del = an8855_port_mirror_del,
+ .support_eee = dsa_supports_eee,
+ .set_mac_eee = an8855_set_mac_eee,
+};
+
+static int an8855_setup_lib_priv(struct an8855_priv *priv)
+{
+ struct mt7530_lib_priv *lib_priv = &priv->lib_priv;
+ int i;
+
+ lib_priv->dev = priv->ds->dev;
+ lib_priv->ds = priv->ds;
+ lib_priv->regmap = priv->regmap;
+ lib_priv->ports = priv->ports;
+ lib_priv->reg_mutex = &priv->reg_mutex;
+
+ for (i = 0; i < ARRAY_SIZE(an8855_fields); i++) {
+ const struct mt7530_reg_field *reg_field;
+ struct regmap_field *field;
+
+ reg_field = &an8855_fields[i];
+ field = devm_regmap_field_alloc(priv->ds->dev, priv->regmap,
+ reg_field->field);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ lib_priv->fields[reg_field->id] = field;
+ }
+
+ return 0;
+}
+
+static int an8855_switch_probe(struct platform_device *pdev)
+{
+ struct an8855_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ /* Get regmap from MFD */
+ priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!priv->regmap)
+ return -ENOENT;
+
+ priv->ds = devm_kzalloc(&pdev->dev, sizeof(*priv->ds), GFP_KERNEL);
+ if (!priv->ds)
+ return -ENOMEM;
+
+ priv->ds->dev = &pdev->dev;
+ priv->ds->num_ports = AN8855_NUM_PORTS;
+ priv->ds->priv = priv;
+ priv->ds->ops = &an8855_switch_ops;
+ ret = devm_mutex_init(&pdev->dev, &priv->reg_mutex);
+ if (ret)
+ return ret;
+ priv->ds->phylink_mac_ops = &an8855_phylink_mac_ops;
+
+ priv->pcs.ops = &an8855_pcs_ops;
+ priv->pcs.poll = true;
+
+ ret = an8855_setup_lib_priv(priv);
+ if (ret)
+ return ret;
+
+ dev_set_drvdata(&pdev->dev, priv);
+
+ return dsa_register_switch(priv->ds);
+}
+
+static void an8855_switch_remove(struct platform_device *pdev)
+{
+ struct an8855_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ if (!priv)
+ return;
+
+ dsa_unregister_switch(priv->ds);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+}
+
+static void an8855_switch_shutdown(struct platform_device *pdev)
+{
+ struct an8855_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ if (!priv)
+ return;
+
+ dsa_switch_shutdown(priv->ds);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+}
+
+static const struct of_device_id an8855_switch_of_match[] = {
+ { .compatible = "airoha,an8855-switch" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_switch_of_match);
+
+static struct platform_driver an8855_switch_driver = {
+ .probe = an8855_switch_probe,
+ .remove = an8855_switch_remove,
+ .shutdown = an8855_switch_shutdown,
+ .driver = {
+ .name = "an8855-switch",
+ .of_match_table = an8855_switch_of_match,
+ },
+};
+module_platform_driver(an8855_switch_driver);
+
+MODULE_AUTHOR("Min Yao <min.yao@airoha.com>");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for Airoha AN8855 Switch");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/mediatek/an8855.h b/drivers/net/dsa/mediatek/an8855.h
new file mode 100644
index 000000000000..85003e568450
--- /dev/null
+++ b/drivers/net/dsa/mediatek/an8855.h
@@ -0,0 +1,755 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Min Yao <min.yao@airoha.com>
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#ifndef __AN8855_H
+#define __AN8855_H
+
+#include <linux/bitfield.h>
+
+#include "mt7530-lib.h"
+
+#define AN8855_NUM_PORTS 6
+#define AN8855_CPU_PORT 5
+#define AN8855_NUM_FDB_RECORDS 2048
+#define AN8855_GPHY_SMI_ADDR_DEFAULT 1
+#define AN8855_PORT_VID_DEFAULT 0
+
+#define MTK_TAG_LEN 4
+#define AN8855_MAX_MTU (15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN)
+
+#define AN8855_L2_AGING_MS_CONSTANT 1024
+
+#define AN8855_TX_LPI_UNIT 2 /* us */
+
+/* AN8855_SCU 0x10000000 */
+#define AN8855_RG_GPIO_LED_MODE 0x10000054
+#define AN8855_RG_GPIO_LED_SEL(i) (0x10000000 + (0x0058 + ((i) * 4)))
+#define AN8855_RG_INTB_MODE 0x10000080
+#define AN8855_RG_RGMII_TXCK_C 0x100001d0
+
+#define AN8855_PKG_SEL 0x10000094
+#define AN8855_PAG_SEL_AN8855H 0x2
+
+#define AN8855_RG_GPIO_L_INV 0x10000010
+#define AN8855_RG_GPIO_CTRL 0x1000a300
+#define AN8855_RG_GPIO_DATA 0x1000a304
+#define AN8855_RG_GPIO_OE 0x1000a314
+
+/* Register for system reset */
+#define AN8855_RST_CTRL 0x100050c0
+#define AN8855_SYS_CTRL_SYS_RST BIT(31)
+
+#define AN8855_INT_MASK 0x100050f0
+#define AN8855_INT_SYS BIT(15)
+
+#define AN8855_RG_CLK_CPU_ICG 0x10005034
+#define AN8855_MCU_ENABLE BIT(3)
+
+#define AN8855_RG_TIMER_CTL 0x1000a100
+#define AN8855_WDOG_ENABLE BIT(25)
+
+#define AN8855_RG_GDMP_RAM 0x10010000
+
+/* Registers to mac forward control for unknown frames */
+#define AN8855_MFC 0x10200010
+#define AN8855_CPU_EN BIT(15)
+#define AN8855_CPU_PORT_IDX GENMASK(12, 8)
+
+#define AN8855_PAC 0x10200024
+#define AN8855_TAG_PAE_MANG_FR BIT(30)
+#define AN8855_TAG_PAE_BPDU_FR BIT(28)
+#define AN8855_TAG_PAE_EG_TAG GENMASK(27, 25)
+#define AN8855_TAG_PAE_LKY_VLAN BIT(24)
+#define AN8855_TAG_PAE_PRI_HIGH BIT(23)
+#define AN8855_TAG_PAE_MIR GENMASK(20, 19)
+#define AN8855_TAG_PAE_PORT_FW GENMASK(18, 16)
+#define AN8855_PAE_MANG_FR BIT(14)
+#define AN8855_PAE_BPDU_FR BIT(12)
+#define AN8855_PAE_EG_TAG GENMASK(11, 9)
+#define AN8855_PAE_LKY_VLAN BIT(8)
+#define AN8855_PAE_PRI_HIGH BIT(7)
+#define AN8855_PAE_MIR GENMASK(4, 3)
+#define AN8855_PAE_PORT_FW GENMASK(2, 0)
+
+#define AN8855_RGAC1 0x10200028
+#define AN8855_R02_MANG_FR BIT(30)
+#define AN8855_R02_BPDU_FR BIT(28)
+#define AN8855_R02_EG_TAG GENMASK(27, 25)
+#define AN8855_R02_LKY_VLAN BIT(24)
+#define AN8855_R02_PRI_HIGH BIT(23)
+#define AN8855_R02_MIR GENMASK(20, 19)
+#define AN8855_R02_PORT_FW GENMASK(18, 16)
+#define AN8855_R01_MANG_FR BIT(14)
+#define AN8855_R01_BPDU_FR BIT(12)
+#define AN8855_R01_EG_TAG GENMASK(11, 9)
+#define AN8855_R01_LKY_VLAN BIT(8)
+#define AN8855_R01_PRI_HIGH BIT(7)
+#define AN8855_R01_MIR GENMASK(4, 3)
+#define AN8855_R01_PORT_FW GENMASK(2, 0)
+
+#define AN8855_RGAC2 0x1020002c
+#define AN8855_R0E_MANG_FR BIT(30)
+#define AN8855_R0E_BPDU_FR BIT(28)
+#define AN8855_R0E_EG_TAG GENMASK(27, 25)
+#define AN8855_R0E_LKY_VLAN BIT(24)
+#define AN8855_R0E_PRI_HIGH BIT(23)
+#define AN8855_R0E_MIR GENMASK(20, 19)
+#define AN8855_R0E_PORT_FW GENMASK(18, 16)
+#define AN8855_R03_MANG_FR BIT(14)
+#define AN8855_R03_BPDU_FR BIT(12)
+#define AN8855_R03_EG_TAG GENMASK(11, 9)
+#define AN8855_R03_LKY_VLAN BIT(8)
+#define AN8855_R03_PRI_HIGH BIT(7)
+#define AN8855_R03_MIR GENMASK(4, 3)
+#define AN8855_R03_PORT_FW GENMASK(2, 0)
+
+#define AN8855_AAC 0x102000a0
+#define AN8855_MAC_AUTO_FLUSH BIT(28)
+/* Control Address Table Age time.
+ * (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT
+ */
+#define AN8855_AGE_CNT GENMASK(20, 12)
+/* Value in seconds. Value is always incremented of 1 */
+#define AN8855_AGE_UNIT GENMASK(10, 0)
+
+/* Registers for ARL Unknown Unicast Forward control */
+#define AN8855_UNUF 0x102000b4
+
+/* Registers for ARL Unknown Multicast Forward control */
+#define AN8855_UNMF 0x102000b8
+
+/* Registers for ARL Broadcast forward control */
+#define AN8855_BCF 0x102000bc
+
+/* Registers for port address age disable */
+#define AN8855_AGDIS 0x102000c0
+
+/* Registers for mirror port control */
+#define AN8855_MIR 0x102000cc
+#define AN8855_MIRROR_EN BIT(7)
+#define AN8855_MIRROR_PORT GENMASK(4, 0)
+
+/* Registers for BPDU and PAE frame control*/
+#define AN8855_BPC 0x102000d0
+#define AN8855_BPDU_MANG_FR BIT(14)
+#define AN8855_BPDU_BPDU_FR BIT(12)
+#define AN8855_BPDU_EG_TAG GENMASK(11, 9)
+#define AN8855_BPDU_LKY_VLAN BIT(8)
+#define AN8855_BPDU_PRI_HIGH BIT(7)
+#define AN8855_BPDU_MIR GENMASK(4, 3)
+#define AN8855_BPDU_PORT_FW GENMASK(2, 0)
+
+/* Registers for IP Unknown Multicast Forward control */
+#define AN8855_UNIPMF 0x102000dc
+
+enum an8855_bpdu_port_fw {
+ AN8855_BPDU_FOLLOW_MFC = 0,
+ AN8855_BPDU_CPU_EXCLUDE = 4,
+ AN8855_BPDU_CPU_INCLUDE = 5,
+ AN8855_BPDU_CPU_ONLY = 6,
+ AN8855_BPDU_DROP = 7,
+};
+
+/* Register for address table control */
+#define AN8855_ATC 0x10200300
+#define AN8855_ATC_BUSY BIT(31)
+#define AN8855_ATC_HASH GENMASK(24, 16)
+#define AN8855_ATC_HIT GENMASK(15, 12)
+#define AN8855_ATC_MAT_MASK GENMASK(11, 7)
+#define AN8855_ATC_MAT(x) FIELD_PREP(AN8855_ATC_MAT_MASK, x)
+#define AN8855_ATC_SAT GENMASK(5, 4)
+#define AN8855_ATC_CMD GENMASK(2, 0)
+
+enum an8855_fdb_mat_cmds {
+ AN8855_FDB_MAT_ALL = 0,
+ AN8855_FDB_MAT_MAC, /* All MAC address */
+ AN8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */
+ AN8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */
+ AN8855_FDB_MAT_DIP, /* All DIP/GA address */
+ AN8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */
+ AN8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */
+ AN8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */
+ AN8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */
+ AN8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */
+ AN8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */
+ AN8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */
+ AN8855_FDB_MAT_MAC_PORT, /* All MAC address with port */
+ AN8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */
+ AN8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */
+ AN8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */
+ AN8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */
+ /* All MAC address with MAC type (dynamic or static) with CVID */
+ AN8855_FDB_MAT_MAC_TYPE_CVID,
+ /* All MAC address with MAC type (dynamic or static) with Filter ID */
+ AN8855_FDB_MAT_MAC_TYPE_FID,
+ /* All MAC address with MAC type (dynamic or static) with port */
+ AN8855_FDB_MAT_MAC_TYPE_PORT,
+};
+
+/* Registers for address table access */
+#define AN8855_ATA1 0x10200304
+#define AN8855_ATA1_MAC0 GENMASK(31, 24)
+#define AN8855_ATA1_MAC1 GENMASK(23, 16)
+#define AN8855_ATA1_MAC2 GENMASK(15, 8)
+#define AN8855_ATA1_MAC3 GENMASK(7, 0)
+#define AN8855_ATA2 0x10200308
+#define AN8855_ATA2_MAC4 GENMASK(31, 24)
+#define AN8855_ATA2_MAC5 GENMASK(23, 16)
+#define AN8855_ATA2_UNAUTH BIT(10)
+#define AN8855_ATA2_TYPE BIT(9) /* 1: dynamic, 0: static */
+#define AN8855_ATA2_AGE GENMASK(8, 0)
+
+/* Register for address table write data */
+#define AN8855_ATWD 0x10200324
+#define AN8855_ATWD_FID GENMASK(31, 28)
+#define AN8855_ATWD_VID GENMASK(27, 16)
+#define AN8855_ATWD_IVL BIT(15)
+#define AN8855_ATWD_EG_TAG GENMASK(14, 12)
+#define AN8855_ATWD_SA_MIR GENMASK(9, 8)
+#define AN8855_ATWD_SA_FWD GENMASK(7, 5)
+#define AN8855_ATWD_UPRI GENMASK(4, 2)
+#define AN8855_ATWD_LEAKY BIT(1)
+#define AN8855_ATWD_VLD_MASK BIT(0) /* vid LOAD */
+#define AN8855_ATWD2 0x10200328
+#define AN8855_ATWD2_PORT GENMASK(7, 0)
+
+/* Registers for table search read address */
+#define AN8855_ATRDS 0x10200330
+#define AN8855_ATRD_SEL GENMASK(1, 0)
+#define AN8855_ATRD0 0x10200334
+#define AN8855_ATRD0_FID GENMASK(28, 25)
+#define AN8855_ATRD0_VID GENMASK(21, 10)
+#define AN8855_ATRD0_IVL BIT(9)
+#define AN8855_ATRD0_TYPE GENMASK(4, 3)
+#define AN8855_ATRD0_ARP GENMASK(2, 1)
+#define AN8855_ATRD0_LIVE BIT(0)
+#define AN8855_ATRD1 0x10200338
+#define AN8855_ATRD1_MAC4 GENMASK(31, 24)
+#define AN8855_ATRD1_MAC5 GENMASK(23, 16)
+#define AN8855_ATRD1_AGING GENMASK(11, 3)
+#define AN8855_ATRD2 0x1020033c
+#define AN8855_ATRD2_MAC0 GENMASK(31, 24)
+#define AN8855_ATRD2_MAC1 GENMASK(23, 16)
+#define AN8855_ATRD2_MAC2 GENMASK(15, 8)
+#define AN8855_ATRD2_MAC3 GENMASK(7, 0)
+#define AN8855_ATRD3 0x10200340
+#define AN8855_ATRD3_PORTMASK GENMASK(7, 0)
+
+enum an8855_fdb_type {
+ AN8855_MAC_TB_TY_MAC = 0,
+ AN8855_MAC_TB_TY_DIP = 1,
+ AN8855_MAC_TB_TY_DIP_SIP = 2,
+};
+
+/* Register for vlan table control */
+#define AN8855_VTCR 0x10200600
+#define AN8855_VTCR_BUSY BIT(31)
+#define AN8855_VTCR_FUNC GENMASK(15, 12)
+#define AN8855_VTCR_VID GENMASK(11, 0)
+
+enum an8855_vlan_cmd {
+ /* Read/Write the specified VID entry from VAWD register based
+ * on VID.
+ */
+ AN8855_VTCR_RD_VID = 0,
+ AN8855_VTCR_WR_VID = 1,
+};
+
+/* Register for setup vlan write data */
+#define AN8855_VAWD0 0x10200604
+/* VLAN Member Control */
+#define AN8855_VA0_PORT GENMASK(31, 26)
+/* Egress Tag Control */
+#define AN8855_VA0_ETAG GENMASK(23, 12)
+#define AN8855_VA0_ETAG_PORT GENMASK(13, 12)
+#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2)
+#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \
+ AN8855_VA0_ETAG_PORT_SHIFT(port))
+#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) << \
+ AN8855_VA0_ETAG_PORT_SHIFT(port))
+#define AN8855_VA0_EG_CON BIT(11)
+#define AN8855_VA0_VTAG_EN BIT(10) /* Per VLAN Egress Tag Control */
+#define AN8855_VA0_IVL_MAC BIT(5) /* Independent VLAN Learning */
+#define AN8855_VA0_FID GENMASK(4, 1)
+#define AN8855_VA0_VLAN_VALID BIT(0) /* VLAN Entry Valid */
+#define AN8855_VAWD1 0x10200608
+#define AN8855_VA1_PORT_STAG BIT(1)
+
+enum an8855_fid {
+ AN8855_FID_STANDALONE = 0,
+ AN8855_FID_BRIDGED = 1,
+};
+
+/* Same register field of VAWD0 */
+#define AN8855_VARD0 0x10200618
+
+enum an8855_vlan_egress_attr {
+ AN8855_VLAN_EGRESS_UNTAG = 0,
+ AN8855_VLAN_EGRESS_TAG = 2,
+ AN8855_VLAN_EGRESS_STACK = 3,
+};
+
+/* Register for port STP state control */
+#define AN8855_SSP 0x10208000
+#define AN8855_SSP_P(x) (AN8855_SSP + ((x) * 0x200))
+/* Up to 16 FID supported, each with the same mask */
+#define AN8855_FID_PST GENMASK(1, 0)
+#define AN8855_FID_PST_SHIFT(fid) (2 * (fid))
+#define AN8855_FID_PST_MASK(fid) (AN8855_FID_PST << \
+ AN8855_FID_PST_SHIFT(fid))
+#define AN8855_FID_PST_VAL(fid, val) (FIELD_PREP(AN8855_FID_PST, (val)) << \
+ AN8855_FID_PST_SHIFT(fid))
+
+enum an8855_stp_state {
+ AN8855_STP_DISABLED = 0,
+ AN8855_STP_BLOCKING = 1,
+ AN8855_STP_LISTENING = AN8855_STP_BLOCKING,
+ AN8855_STP_LEARNING = 2,
+ AN8855_STP_FORWARDING = 3
+};
+
+/* Register for port control */
+#define AN8855_PCR 0x10208004
+#define AN8855_PCR_P(x) (AN8855_PCR + ((x) * 0x200))
+#define AN8855_EG_TAG GENMASK(29, 28)
+#define AN8855_PORT_PRI GENMASK(26, 24)
+#define AN8855_PORT_TX_MIR BIT(20)
+#define AN8855_PORT_RX_MIR BIT(16)
+#define AN8855_PORT_VLAN GENMASK(1, 0)
+
+enum an8855_port_mode {
+ /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
+ AN8855_PORT_MATRIX_MODE = 0,
+
+ /* Fallback Mode: Forward received frames with ingress ports that do
+ * not belong to the VLAN member. Frames whose VID is not listed on
+ * the VLAN table are forwarded by the PCR_MATRIX members.
+ */
+ AN8855_PORT_FALLBACK_MODE = 1,
+
+ /* Check Mode: Forward received frames whose ingress do not
+ * belong to the VLAN member. Discard frames if VID ismiddes on the
+ * VLAN table.
+ */
+ AN8855_PORT_CHECK_MODE = 2,
+
+ /* Security Mode: Discard any frame due to ingress membership
+ * violation or VID missed on the VLAN table.
+ */
+ AN8855_PORT_SECURITY_MODE = 3,
+};
+
+/* Register for port security control */
+#define AN8855_PSC 0x1020800c
+#define AN8855_PSC_P(x) (AN8855_PSC + ((x) * 0x200))
+#define AN8855_SA_DIS BIT(4)
+
+/* Register for port vlan control */
+#define AN8855_PVC 0x10208010
+#define AN8855_PVC_P(x) (AN8855_PVC + ((x) * 0x200))
+#define AN8855_PORT_SPEC_REPLACE_MODE BIT(11)
+#define AN8855_PVC_EG_TAG GENMASK(10, 8)
+#define AN8855_VLAN_ATTR GENMASK(7, 6)
+#define AN8855_PORT_SPEC_TAG BIT(5)
+#define AN8855_ACC_FRM GENMASK(1, 0)
+
+enum an8855_vlan_port_eg_tag {
+ AN8855_VLAN_EG_DISABLED = 0,
+ AN8855_VLAN_EG_CONSISTENT = 1,
+ AN8855_VLAN_EG_UNTAGGED = 4,
+ AN8855_VLAN_EG_SWAP = 5,
+ AN8855_VLAN_EG_TAGGED = 6,
+ AN8855_VLAN_EG_STACK = 7,
+};
+
+enum an8855_vlan_port_attr {
+ AN8855_VLAN_USER = 0,
+ AN8855_VLAN_STACK = 1,
+ AN8855_VLAN_TRANSPARENT = 3,
+};
+
+enum an8855_vlan_port_acc_frm {
+ AN8855_VLAN_ACC_ALL = 0,
+ AN8855_VLAN_ACC_TAGGED = 1,
+ AN8855_VLAN_ACC_UNTAGGED = 2,
+};
+
+#define AN8855_PPBV1 0x10208014
+#define AN8855_PPBV1_P(x) (AN8855_PPBV1 + ((x) * 0x200))
+#define AN8855_PPBV_G0_PORT_VID GENMASK(11, 0)
+
+#define AN8855_PORTMATRIX 0x10208044
+#define AN8855_PORTMATRIX_P(x) (AN8855_PORTMATRIX + ((x) * 0x200))
+#define AN8855_PORTMATRIX_MASK GENMASK(5, 0)
+/* Port matrix without the CPU port that should never be removed */
+#define AN8855_USER_PORTMATRIX GENMASK(4, 0)
+
+/* Register for port PVID */
+#define AN8855_PVID 0x10208048
+#define AN8855_PVID_P(x) (AN8855_PVID + ((x) * 0x200))
+#define AN8855_G0_PORT_VID GENMASK(11, 0)
+
+/* Register for port MAC control register */
+#define AN8855_PMCR_P(x) (0x10210000 + ((x) * 0x200))
+#define AN8855_PMCR_FORCE_MODE BIT(31)
+#define AN8855_PMCR_FORCE_SPEED GENMASK(30, 28)
+#define AN8855_PMCR_FORCE_SPEED_5000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4)
+#define AN8855_PMCR_FORCE_SPEED_2500 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3)
+#define AN8855_PMCR_FORCE_SPEED_1000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2)
+#define AN8855_PMCR_FORCE_SPEED_100 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)
+#define AN8855_PMCR_FORCE_SPEED_10 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x0)
+#define AN8855_PMCR_FORCE_FDX BIT(25)
+#define AN8855_PMCR_FORCE_LNK BIT(24)
+#define AN8855_PMCR_IFG_XMIT GENMASK(21, 20)
+#define AN8855_PMCR_EXT_PHY BIT(19)
+#define AN8855_PMCR_MAC_MODE BIT(18)
+#define AN8855_PMCR_TX_EN BIT(16)
+#define AN8855_PMCR_RX_EN BIT(15)
+#define AN8855_PMCR_BACKOFF_EN BIT(12)
+#define AN8855_PMCR_BACKPR_EN BIT(11)
+#define AN8855_PMCR_FORCE_EEE5G BIT(9)
+#define AN8855_PMCR_FORCE_EEE2P5G BIT(8)
+#define AN8855_PMCR_FORCE_EEE1G BIT(7)
+#define AN8855_PMCR_FORCE_EEE100 BIT(6)
+#define AN8855_PMCR_RX_FC_EN BIT(5)
+#define AN8855_PMCR_TX_FC_EN BIT(4)
+
+#define AN8855_PMSR_P(x) (0x10210010 + (x) * 0x200)
+#define AN8855_PMSR_SPEED GENMASK(30, 28)
+#define AN8855_PMSR_SPEED_5000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4)
+#define AN8855_PMSR_SPEED_2500 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3)
+#define AN8855_PMSR_SPEED_1000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2)
+#define AN8855_PMSR_SPEED_100 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1)
+#define AN8855_PMSR_SPEED_10 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0)
+#define AN8855_PMSR_DPX BIT(25)
+#define AN8855_PMSR_LNK BIT(24)
+#define AN8855_PMSR_EEE1G BIT(7)
+#define AN8855_PMSR_EEE100M BIT(6)
+#define AN8855_PMSR_RX_FC BIT(5)
+#define AN8855_PMSR_TX_FC BIT(4)
+
+#define AN8855_PMEEECR_P(x) (0x10210004 + (x) * 0x200)
+#define AN8855_LPI_MODE_EN BIT(31)
+#define AN8855_WAKEUP_TIME_2500 GENMASK(23, 16)
+#define AN8855_WAKEUP_TIME_1000 GENMASK(15, 8)
+#define AN8855_WAKEUP_TIME_100 GENMASK(7, 0)
+#define AN8855_PMEEECR2_P(x) (0x10210008 + (x) * 0x200)
+#define AN8855_WAKEUP_TIME_5000 GENMASK(7, 0)
+
+#define AN8855_GMACCR 0x10213e00
+#define AN8855_MAX_RX_JUMBO GENMASK(7, 4)
+/* 2K for 0x0, 0x1, 0x2 */
+#define AN8855_MAX_RX_JUMBO_2K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0)
+#define AN8855_MAX_RX_JUMBO_3K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3)
+#define AN8855_MAX_RX_JUMBO_4K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4)
+#define AN8855_MAX_RX_JUMBO_5K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5)
+#define AN8855_MAX_RX_JUMBO_6K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6)
+#define AN8855_MAX_RX_JUMBO_7K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7)
+#define AN8855_MAX_RX_JUMBO_8K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8)
+#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9)
+#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa)
+#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb)
+#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc)
+#define AN8855_MAX_RX_PKT_LEN GENMASK(1, 0)
+#define AN8855_MAX_RX_PKT_1518_1522 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0)
+#define AN8855_MAX_RX_PKT_1536 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1)
+#define AN8855_MAX_RX_PKT_1552 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2)
+#define AN8855_MAX_RX_PKT_JUMBO FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3)
+
+#define AN8855_CKGCR 0x10213e1c
+#define AN8855_LPI_TXIDLE_THD_MASK GENMASK(31, 14)
+#define AN8855_CKG_LNKDN_PORT_STOP BIT(1)
+#define AN8855_CKG_LNKDN_GLB_STOP BIT(0)
+
+/* Register for MIB */
+#define AN8855_MIB_COUNTER 0x10214000
+#define AN8855_PORT_MIB_COUNTER(x) (AN8855_MIB_COUNTER + (x) * 0x200)
+/* Each define is an offset of AN8855_PORT_MIB_COUNTER */
+#define AN8855_PORT_MIB_TX_DROP (AN8855_MIB_COUNTER + 0x00)
+#define AN8855_PORT_MIB_TX_CRC_ERR (AN8855_MIB_COUNTER + 0x04)
+#define AN8855_PORT_MIB_TX_UNICAST (AN8855_MIB_COUNTER + 0x08)
+#define AN8855_PORT_MIB_TX_MULTICAST (AN8855_MIB_COUNTER + 0x0c)
+#define AN8855_PORT_MIB_TX_BROADCAST (AN8855_MIB_COUNTER + 0x10)
+#define AN8855_PORT_MIB_TX_COLLISION (AN8855_MIB_COUNTER + 0x14)
+#define AN8855_PORT_MIB_TX_SINGLE_COLLISION (AN8855_MIB_COUNTER + 0x18)
+#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION (AN8855_MIB_COUNTER + 0x1c)
+#define AN8855_PORT_MIB_TX_DEFERRED (AN8855_MIB_COUNTER + 0x20)
+#define AN8855_PORT_MIB_TX_LATE_COLLISION (AN8855_MIB_COUNTER + 0x24)
+#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION (AN8855_MIB_COUNTER + 0x28)
+#define AN8855_PORT_MIB_TX_PAUSE (AN8855_MIB_COUNTER + 0x2c)
+#define AN8855_PORT_MIB_TX_PKT_SZ_64 (AN8855_MIB_COUNTER + 0x30)
+#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0x34)
+#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0x38)
+#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0x3c)
+#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0x40)
+#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0x44)
+#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0x48)
+#define AN8855_PORT_MIB_TX_BYTES_LOW (AN8855_MIB_COUNTER + 0x4c) /* 64 bytes */
+#define AN8855_PORT_MIB_TX_BYTES_HIGH (AN8855_MIB_COUNTER + 0x50)
+#define AN8855_PORT_MIB_TX_OVERSIZE_DROP (AN8855_MIB_COUNTER + 0x54)
+#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0x58) /* 64 bytes */
+#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0x5c)
+#define AN8855_PORT_MIB_RX_DROP (AN8855_MIB_COUNTER + 0x80)
+#define AN8855_PORT_MIB_RX_FILTERING (AN8855_MIB_COUNTER + 0x84)
+#define AN8855_PORT_MIB_RX_UNICAST (AN8855_MIB_COUNTER + 0x88)
+#define AN8855_PORT_MIB_RX_MULTICAST (AN8855_MIB_COUNTER + 0x8c)
+#define AN8855_PORT_MIB_RX_BROADCAST (AN8855_MIB_COUNTER + 0x90)
+#define AN8855_PORT_MIB_RX_ALIGN_ERR (AN8855_MIB_COUNTER + 0x94)
+#define AN8855_PORT_MIB_RX_CRC_ERR (AN8855_MIB_COUNTER + 0x98)
+#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR (AN8855_MIB_COUNTER + 0x9c)
+#define AN8855_PORT_MIB_RX_FRAG_ERR (AN8855_MIB_COUNTER + 0xa0)
+#define AN8855_PORT_MIB_RX_OVER_SZ_ERR (AN8855_MIB_COUNTER + 0xa4)
+#define AN8855_PORT_MIB_RX_JABBER_ERR (AN8855_MIB_COUNTER + 0xa8)
+#define AN8855_PORT_MIB_RX_PAUSE (AN8855_MIB_COUNTER + 0xac)
+#define AN8855_PORT_MIB_RX_PKT_SZ_64 (AN8855_MIB_COUNTER + 0xb0)
+#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0xb4)
+#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0xb8)
+#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0xbc)
+#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0xc0)
+#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0xc4)
+#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0xc8)
+#define AN8855_PORT_MIB_RX_BYTES_LOW (AN8855_MIB_COUNTER + 0xcc) /* 64 bytes */
+#define AN8855_PORT_MIB_RX_BYTES_HIGH (AN8855_MIB_COUNTER + 0xd0)
+#define AN8855_PORT_MIB_RX_CTRL_DROP (AN8855_MIB_COUNTER + 0xd4)
+#define AN8855_PORT_MIB_RX_INGRESS_DROP (AN8855_MIB_COUNTER + 0xd8)
+#define AN8855_PORT_MIB_RX_ARL_DROP (AN8855_MIB_COUNTER + 0xdc)
+#define AN8855_PORT_MIB_FLOW_CONTROL_DROP (AN8855_MIB_COUNTER + 0xe0)
+#define AN8855_PORT_MIB_WRED_DROP (AN8855_MIB_COUNTER + 0xe4)
+#define AN8855_PORT_MIB_MIRROR_DROP (AN8855_MIB_COUNTER + 0xe8)
+#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0xec) /* 64 bytes */
+#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0xf0)
+#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP (AN8855_MIB_COUNTER + 0xf4)
+#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP (AN8855_MIB_COUNTER + 0xf8)
+#define AN8855_PORT_MIB_PORT_CONTROL_DROP (AN8855_MIB_COUNTER + 0xfc)
+#define AN8855_MIB_CCR 0x10213e30
+#define AN8855_CCR_MIB_ENABLE BIT(31)
+#define AN8855_CCR_RX_OCT_CNT_GOOD BIT(7)
+#define AN8855_CCR_RX_OCT_CNT_BAD BIT(6)
+#define AN8855_CCR_TX_OCT_CNT_GOOD BIT(5)
+#define AN8855_CCR_TX_OCT_CNT_BAD BIT(4)
+#define AN8855_CCR_RX_OCT_CNT_GOOD_2 BIT(3)
+#define AN8855_CCR_RX_OCT_CNT_BAD_2 BIT(2)
+#define AN8855_CCR_TX_OCT_CNT_GOOD_2 BIT(1)
+#define AN8855_CCR_TX_OCT_CNT_BAD_2 BIT(0)
+#define AN8855_CCR_MIB_ACTIVATE (AN8855_CCR_MIB_ENABLE | \
+ AN8855_CCR_RX_OCT_CNT_GOOD | \
+ AN8855_CCR_RX_OCT_CNT_BAD | \
+ AN8855_CCR_TX_OCT_CNT_GOOD | \
+ AN8855_CCR_TX_OCT_CNT_BAD | \
+ AN8855_CCR_RX_OCT_CNT_BAD_2 | \
+ AN8855_CCR_TX_OCT_CNT_BAD_2)
+#define AN8855_MIB_CLR 0x10213e34
+#define AN8855_MIB_PORT6_CLR BIT(6)
+#define AN8855_MIB_PORT5_CLR BIT(5)
+#define AN8855_MIB_PORT4_CLR BIT(4)
+#define AN8855_MIB_PORT3_CLR BIT(3)
+#define AN8855_MIB_PORT2_CLR BIT(2)
+#define AN8855_MIB_PORT1_CLR BIT(1)
+#define AN8855_MIB_PORT0_CLR BIT(0)
+
+/* HSGMII/SGMII Configuration register */
+/* AN8855_HSGMII_AN_CSR_BASE 0x10220000 */
+#define AN8855_SGMII_REG_AN0 0x10220000
+/* AN8855_SGMII_AN_ENABLE BMCR_ANENABLE */
+/* AN8855_SGMII_AN_RESTART BMCR_ANRESTART */
+#define AN8855_SGMII_REG_AN_13 0x10220034
+#define AN8855_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define AN8855_SGMII_IF_MODE GENMASK(5, 0)
+#define AN8855_SGMII_REG_AN_FORCE_CL37 0x10220060
+#define AN8855_RG_FORCE_AN_DONE BIT(0)
+
+/* AN8855_HSGMII_CSR_PCS_BASE 0x10220000 */
+#define AN8855_RG_HSGMII_PCS_CTROL_1 0x10220a00
+#define AN8855_RG_TBI_10B_MODE BIT(30)
+#define AN8855_RG_AN_SGMII_MODE_FORCE 0x10220a24
+#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define AN8855_RG_FORCE_CUR_SGMII_SEL BIT(0)
+
+/* AN8855_MULTI_SGMII_CSR_BASE 0x10224000 */
+#define AN8855_SGMII_STS_CTRL_0 0x10224018
+#define AN8855_RG_LINK_MODE_P0 GENMASK(5, 4)
+#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3)
+#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2)
+#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1)
+#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0)
+#define AN8855_RG_FORCE_SPD_MODE_P0 BIT(2)
+#define AN8855_MSG_RX_CTRL_0 0x10224100
+#define AN8855_MSG_RX_LIK_STS_0 0x10224514
+#define AN8855_RG_DPX_STS_P3 BIT(24)
+#define AN8855_RG_DPX_STS_P2 BIT(16)
+#define AN8855_RG_EEE1G_STS_P1 BIT(12)
+#define AN8855_RG_DPX_STS_P1 BIT(8)
+#define AN8855_RG_TXFC_STS_P0 BIT(2)
+#define AN8855_RG_RXFC_STS_P0 BIT(1)
+#define AN8855_RG_DPX_STS_P0 BIT(0)
+#define AN8855_MSG_RX_LIK_STS_2 0x1022451c
+#define AN8855_RG_RXFC_AN_BYPASS_P3 BIT(11)
+#define AN8855_RG_RXFC_AN_BYPASS_P2 BIT(10)
+#define AN8855_RG_RXFC_AN_BYPASS_P1 BIT(9)
+#define AN8855_RG_TXFC_AN_BYPASS_P3 BIT(7)
+#define AN8855_RG_TXFC_AN_BYPASS_P2 BIT(6)
+#define AN8855_RG_TXFC_AN_BYPASS_P1 BIT(5)
+#define AN8855_RG_DPX_AN_BYPASS_P3 BIT(3)
+#define AN8855_RG_DPX_AN_BYPASS_P2 BIT(2)
+#define AN8855_RG_DPX_AN_BYPASS_P1 BIT(1)
+#define AN8855_RG_DPX_AN_BYPASS_P0 BIT(0)
+#define AN8855_PHY_RX_FORCE_CTRL_0 0x10224520
+#define AN8855_RG_FORCE_TXC_SEL BIT(4)
+
+/* AN8855_XFI_CSR_PCS_BASE 0x10225000 */
+#define AN8855_RG_USXGMII_AN_CONTROL_0 0x10225bf8
+
+/* AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 */
+#define AN8855_RG_RATE_ADAPT_CTRL_0 0x10226000
+#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27)
+#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26)
+#define AN8855_RG_RATE_ADAPT_RX_EN BIT(4)
+#define AN8855_RG_RATE_ADAPT_TX_EN BIT(0)
+#define AN8855_RATE_ADP_P0_CTRL_0 0x10226100
+#define AN8855_RG_P0_DIS_MII_MODE BIT(31)
+#define AN8855_RG_P0_MII_MODE BIT(28)
+#define AN8855_RG_P0_MII_RA_RX_EN BIT(3)
+#define AN8855_RG_P0_MII_RA_TX_EN BIT(2)
+#define AN8855_RG_P0_MII_RA_RX_MODE BIT(1)
+#define AN8855_RG_P0_MII_RA_TX_MODE BIT(0)
+#define AN8855_MII_RA_AN_ENABLE 0x10226300
+#define AN8855_RG_P0_RA_AN_EN BIT(0)
+
+/* AN8855_QP_DIG_CSR_BASE 0x1022a000 */
+#define AN8855_QP_CK_RST_CTRL_4 0x1022a310
+#define AN8855_QP_DIG_MODE_CTRL_0 0x1022a324
+#define AN8855_RG_SGMII_MODE GENMASK(5, 4)
+#define AN8855_RG_SGMII_AN_EN BIT(0)
+#define AN8855_QP_DIG_MODE_CTRL_1 0x1022a330
+#define AN8855_RG_TPHY_SPEED GENMASK(3, 2)
+
+/* AN8855_SERDES_WRAPPER_BASE 0x1022c000 */
+#define AN8855_USGMII_CTRL_0 0x1022c000
+
+/* AN8855_QP_PMA_TOP_BASE 0x1022e000 */
+#define AN8855_PON_RXFEDIG_CTRL_0 0x1022e100
+#define AN8855_RG_QP_EQ_RX500M_CK_SEL BIT(12)
+#define AN8855_PON_RXFEDIG_CTRL_9 0x1022e124
+#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT GENMASK(2, 0)
+
+#define AN8855_SS_LCPLL_PWCTL_SETTING_2 0x1022e208
+#define AN8855_RG_NCPO_ANA_MSB GENMASK(17, 16)
+#define AN8855_SS_LCPLL_TDC_FLT_2 0x1022e230
+#define AN8855_RG_LCPLL_NCPO_VALUE GENMASK(30, 0)
+#define AN8855_SS_LCPLL_TDC_FLT_5 0x1022e23c
+#define AN8855_RG_LCPLL_NCPO_CHG BIT(24)
+#define AN8855_SS_LCPLL_TDC_PCW_1 0x1022e248
+#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0)
+#define AN8855_INTF_CTRL_8 0x1022e320
+#define AN8855_INTF_CTRL_9 0x1022e324
+#define AN8855_INTF_CTRL_10 0x1022e328
+#define AN8855_RG_DA_QP_TX_FIR_C2_SEL BIT(29)
+#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24)
+#define AN8855_RG_DA_QP_TX_FIR_C1_SEL BIT(21)
+#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16)
+#define AN8855_INTF_CTRL_11 0x1022e32c
+#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6)
+#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0)
+#define AN8855_PLL_CTRL_0 0x1022e400
+#define AN8855_RG_PHYA_AUTO_INIT BIT(0)
+#define AN8855_PLL_CTRL_2 0x1022e408
+#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30)
+#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29)
+#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28)
+#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27)
+#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26)
+#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24)
+#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22)
+#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20)
+#define AN8855_RG_DA_QP_PLL_IR_INTF GENMASK(19, 16)
+#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14)
+#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12)
+#define AN8855_RG_DA_QP_PLL_BR_INTF GENMASK(10, 8)
+#define AN8855_RG_DA_QP_PLL_BPD_INTF GENMASK(7, 6)
+#define AN8855_RG_DA_QP_PLL_BPA_INTF GENMASK(4, 2)
+#define AN8855_RG_DA_QP_PLL_BC_INTF GENMASK(1, 0)
+#define AN8855_PLL_CTRL_3 0x1022e40c
+#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16)
+#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0)
+#define AN8855_PLL_CTRL_4 0x1022e410
+#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)
+#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2)
+#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0)
+#define AN8855_PLL_CK_CTRL_0 0x1022e414
+#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9)
+#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8)
+#define AN8855_RX_DLY_0 0x1022e614
+#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8)
+#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0)
+#define AN8855_RX_CTRL_2 0x1022e630
+#define AN8855_RG_QP_RX_EQ_EN_H_DLY GENMASK(28, 16)
+#define AN8855_RX_CTRL_5 0x1022e63c
+#define AN8855_RG_FREDET_CHK_CYCLE GENMASK(29, 10)
+#define AN8855_RX_CTRL_6 0x1022e640
+#define AN8855_RG_FREDET_GOLDEN_CYCLE GENMASK(19, 0)
+#define AN8855_RX_CTRL_7 0x1022e644
+#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0)
+#define AN8855_RX_CTRL_8 0x1022e648
+#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16)
+#define AN8855_RG_DA_QP_LEQOS_EN_TIME GENMASK(14, 0)
+#define AN8855_RX_CTRL_26 0x1022e690
+#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26)
+#define AN8855_RG_LINK_NE_EN BIT(24)
+#define AN8855_RG_LINK_ERRO_EN BIT(23)
+#define AN8855_RX_CTRL_42 0x1022e6d0
+#define AN8855_RG_QP_EQ_EN_DLY GENMASK(12, 0)
+
+/* AN8855_QP_ANA_CSR_BASE 0x1022f000 */
+#define AN8855_RG_QP_RX_DAC_EN 0x1022f000
+#define AN8855_RG_QP_SIGDET_HF GENMASK(17, 16)
+#define AN8855_RG_QP_RXAFE_RESERVE 0x1022f004
+#define AN8855_RG_QP_CDR_PD_10B_EN BIT(11)
+#define AN8855_RG_QP_CDR_LPF_BOT_LIM 0x1022f008
+#define AN8855_RG_QP_CDR_LPF_KP_GAIN GENMASK(26, 24)
+#define AN8855_RG_QP_CDR_LPF_KI_GAIN GENMASK(22, 20)
+#define AN8855_RG_QP_CDR_LPF_MJV_LIM 0x1022f00c
+#define AN8855_RG_QP_CDR_LPF_RATIO GENMASK(5, 4)
+#define AN8855_RG_QP_CDR_LPF_SETVALUE 0x1022f014
+#define AN8855_RG_QP_CDR_PR_BUF_IN_SR GENMASK(31, 29)
+#define AN8855_RG_QP_CDR_PR_BETA_SEL GENMASK(28, 25)
+#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 0x1022f018
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV GENMASK(26, 24)
+#define AN8855_RG_QP_CDR_PR_DAC_BAND GENMASK(12, 8)
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c
+#define AN8855_RG_QP_CDR_PR_XFICK_EN BIT(30)
+#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6)
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0)
+#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020
+#define AN8855_RG_QP_CDR_PHYCK_SEL GENMASK(17, 16)
+#define AN8855_RG_QP_CDR_PHYCK_RSTB BIT(13)
+#define AN8855_RG_QP_CDR_PHYCK_DIV GENMASK(12, 6)
+#define AN8855_RG_QP_TX_MODE 0x1022f028
+#define AN8855_RG_QP_TX_RESERVE GENMASK(31, 16)
+#define AN8855_RG_QP_TX_MODE_16B_EN BIT(0)
+#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c
+#define AN8855_RG_QP_PLL_SDM_ORD 0x1022f040
+#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4)
+#define AN8855_RG_QP_PLL_SSC_TRI_EN BIT(3)
+
+/* AN8855_ETHER_SYS_BASE 0x1028c800 */
+#define AN8855_RG_GPHY_AFE_PWD 0x1028c840
+#define AN8855_RG_GPHY_SMI_ADDR 0x1028c848
+
+struct an8855_priv {
+ struct dsa_switch *ds;
+ struct regmap *regmap;
+ /* Protect ATU or VLAN table access */
+ struct mutex reg_mutex;
+
+ struct phylink_pcs pcs;
+
+ struct mt7530_port ports[AN8855_NUM_PORTS];
+ u32 tx_lpi_timer_ports[AN8855_NUM_PORTS];
+
+ struct mt7530_lib_priv lib_priv;
+};
+
+#endif /* __AN8855_H */
diff --git a/drivers/net/dsa/mediatek/mt7530-lib.c b/drivers/net/dsa/mediatek/mt7530-lib.c
index 098dd45d3ee9..432576803332 100644
--- a/drivers/net/dsa/mediatek/mt7530-lib.c
+++ b/drivers/net/dsa/mediatek/mt7530-lib.c
@@ -423,9 +423,11 @@ int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,
return ret;
}
- regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
- if (cmd == MT7530_FDB_READ && val)
- return -EINVAL;
+ if (priv->fields[MT7530_ATC_INVALID]) {
+ regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
+ if (cmd == MT7530_FDB_READ && val)
+ return -EINVAL;
+ }
if (rsp)
regmap_field_read(priv->fields[__MT7530_ATC], rsp);
@@ -442,6 +444,8 @@ static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid,
regmap_field_write(priv->fields[__MT7530_ATWD1], 0);
regmap_field_write(priv->fields[__MT7530_ATWD2], 0);
regmap_field_write(priv->fields[__MT7530_ATWD3], 0);
+ if (priv->fields[__MT7530_ATWD4])
+ regmap_field_write(priv->fields[__MT7530_ATWD4], 0);
regmap_field_write(priv->fields[MT7530_ATWD_CVID], vid);
regmap_field_write(priv->fields[MT7530_ATWD_IVL], 1);
@@ -452,7 +456,17 @@ static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid,
* be aged out and STATIC_EMP specified as erasing an
* entry
*/
- regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type);
+ if (priv->fields[MT7530_ATWD_ENT_STATUS])
+ regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type);
+ if (priv->fields[AN8855_ATWD_TYPE]) {
+ /* Default to static entry (0) */
+ regmap_field_write(priv->fields[AN8855_ATWD_TYPE], 0);
+ }
+ if (priv->fields[AN8855_ATWD_VLD]) {
+ /* Load entry if STATIC_ENT */
+ regmap_field_write(priv->fields[AN8855_ATWD_VLD],
+ type == STATIC_ENT);
+ }
regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_5], mac[5]);
regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_4], mac[4]);
regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_3], mac[3]);
@@ -483,8 +497,14 @@ void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb)
fdb->mac[1] = val;
regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_0], &val);
fdb->mac[0] = val;
- regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
- fdb->noarp = val == STATIC_ENT;
+ if (priv->fields[MT7530_ATRD_ENT_STATUS]) {
+ regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
+ fdb->noarp = val == STATIC_ENT;
+ }
+ if (priv->fields[AN8855_ATRD_ARP]) {
+ regmap_field_read(priv->fields[AN8855_ATRD_ARP], &val);
+ fdb->noarp = !!val;
+ }
}
EXPORT_SYMBOL_GPL(mt7530_lib_fdb_read);
@@ -787,6 +807,17 @@ void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port,
}
EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_leave);
+void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port,
+ u16 pvid)
+{
+ regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
+ port, pvid);
+ if (priv->fields[AN8855_PVID_G0_PORT_VID])
+ regmap_fields_write(priv->fields[AN8855_PVID_G0_PORT_VID],
+ port, pvid);
+}
+EXPORT_SYMBOL_GPL(mt7530_port_set_pvid);
+
static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int port)
{
struct dsa_switch *ds = priv->ds;
@@ -807,8 +838,7 @@ static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int port)
regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
port, MT7530_VLAN_ACC_ALL);
- regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
- port, G0_PORT_VID_DEF);
+ mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
for (i = 0; i < priv->ds->num_ports; i++) {
if (i == port)
@@ -840,8 +870,7 @@ static void mt7530_port_set_vlan_aware(struct mt7530_lib_priv *priv, int port)
if (dsa_is_user_port(ds, port)) {
regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
port, MT7530_PORT_SECURITY_MODE);
- regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
- port, priv->ports[port].pvid);
+ mt7530_port_set_pvid(priv, port, priv->ports[port].pvid);
/* Only accept tagged frames if PVID is not set */
if (!priv->ports[port].pvid)
@@ -919,10 +948,12 @@ static int mt7530_vlan_cmd(struct mt7530_lib_priv *priv, enum mt7530_vlan_cmd cm
return ret;
}
- regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val);
- if (val) {
- dev_err(priv->dev, "read VTCR invalid\n");
- return -EINVAL;
+ if (priv->fields[MT7530_VTCR_INVALID]) {
+ regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val);
+ if (val) {
+ dev_err(priv->dev, "read VTCR invalid\n");
+ return -EINVAL;
+ }
}
return 0;
@@ -1044,8 +1075,7 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
/* Only configure PVID if VLAN filtering is enabled */
if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
- port, vlan->vid);
+ mt7530_port_set_pvid(priv, port, vlan->vid);
} else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
/* This VLAN is overwritten without PVID, so unset it */
priv->ports[port].pvid = G0_PORT_VID_DEF;
@@ -1055,8 +1085,7 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
port, MT7530_VLAN_ACC_TAGGED);
- regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
- port, G0_PORT_VID_DEF);
+ mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
}
mutex_unlock(priv->reg_mutex);
@@ -1093,8 +1122,7 @@ int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,
regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
port, MT7530_VLAN_ACC_TAGGED);
- regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
- port, G0_PORT_VID_DEF);
+ mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
}
mutex_unlock(priv->reg_mutex);
diff --git a/drivers/net/dsa/mediatek/mt7530-lib.h b/drivers/net/dsa/mediatek/mt7530-lib.h
index da2ee781f7e6..1465eb49f4cb 100644
--- a/drivers/net/dsa/mediatek/mt7530-lib.h
+++ b/drivers/net/dsa/mediatek/mt7530-lib.h
@@ -159,6 +159,8 @@ enum mt7530_regmap_field {
MT7530_ATWD_AGE_TIMER,
MT7530_ATWD_PORT_MAP,
MT7530_ATWD_ENT_STATUS,
+ AN8855_ATWD_TYPE,
+ AN8855_ATWD_VLD,
MT7530_ATWD_MAC_BYTE_5,
MT7530_ATWD_MAC_BYTE_4,
MT7530_ATWD_MAC_BYTE_3,
@@ -169,11 +171,13 @@ enum mt7530_regmap_field {
__MT7530_ATWD1,
__MT7530_ATWD2,
__MT7530_ATWD3,
+ __MT7530_ATWD4,
MT7530_ATRD_CVID,
MT7530_ATRD_AGE_TIMER,
MT7530_ATRD_PORT_MAP,
MT7530_ATRD_ENT_STATUS,
+ AN8855_ATRD_ARP,
MT7530_ATRD_MAC_BYTE_5,
MT7530_ATRD_MAC_BYTE_4,
MT7530_ATRD_MAC_BYTE_3,
@@ -201,6 +205,7 @@ enum mt7530_regmap_field {
MT7530_PVC_ACC_FRM,
MT7530_PPBV1_G0_PORT_VID,
+ AN8855_PVID_G0_PORT_VID,
MT7530_GMACCR_MAX_RX_JUMBO,
MT7530_GMACCR_MAX_RX_PKT_LEN,
@@ -223,8 +228,13 @@ enum mt7530_regmap_field {
MT7530_MIB_TX_PKT_SZ_256_TO_511,
MT7530_MIB_TX_PKT_SZ_512_TO_1023,
MT7530_MIB_TX_PKT_SZ_1024_TO_MAX,
+ AN8855_MIB_TX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_TX_PKT_SZ_1519_TO_MAX,
MT7530_MIB_TX_BYTES_LOW,
MT7530_MIB_TX_BYTES_HIGH,
+ AN8855_MIB_TX_OVERSIZE_DROP,
+ AN8855_MIB_TX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_TX_BAD_PKT_BYTES_HIGH,
MT7530_MIB_RX_DROP,
MT7530_MIB_RX_FILTERING,
MT7530_MIB_RX_UNICAST,
@@ -243,11 +253,21 @@ enum mt7530_regmap_field {
MT7530_MIB_RX_PKT_SZ_256_TO_511,
MT7530_MIB_RX_PKT_SZ_512_TO_1023,
MT7530_MIB_RX_PKT_SZ_1024_TO_MAX,
+ AN8855_MIB_RX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_RX_PKT_SZ_1519_TO_MAX,
MT7530_MIB_RX_BYTES_LOW,
MT7530_MIB_RX_BYTES_HIGH,
MT7530_MIB_RX_CTRL_DROP,
MT7530_MIB_RX_INGRESS_DROP,
MT7530_MIB_RX_ARL_DROP,
+ AN8855_MIB_FLOW_CONTROL_DROP,
+ AN8855_MIB_WRED_DROP,
+ AN8855_MIB_MIRROR_DROP,
+ AN8855_MIB_RX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_RX_BAD_PKT_BYTES_HIGH,
+ AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP,
+ AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP,
+ AN8855_MIB_PORT_CONTROL_DROP,
MT7530_FIELD_MAX,
};
@@ -385,6 +405,8 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,
const struct switchdev_obj_port_vlan *vlan);
+void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port,
+ u16 pvid);
int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv);
#endif /* __MT7530_LIB_H */
--
2.55.0
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH net-next v24 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch
2026-09-28 19:45 ` [PATCH net-next v24 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Christian Marangi
@ 2026-10-01 4:45 ` netdev-bot+sashiko
0 siblings, 0 replies; 17+ messages in thread
From: netdev-bot+sashiko @ 2026-10-01 4:45 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found more severe
issue(s) in other patches of this series. This mail is only an FYI, in case
you want to address the nit picks below when you respin.
Low priority / nit picks for your consideration:
- [Low]
Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml…
--
dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch
This commit adds a YAML binding for the Airoha AN8855 5-port Gigabit
Switch. The binding references the generic DSA ethernet-ports
definition and adds a single compatible string.
> diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
> new file mode 100644
> index 0000000000000..5ad9b9e139831
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
[ ... ]
> +description: >
> + Airoha AN8855 is a 5-port Gigabit Switch.
> +
> + It does expose the 5 Internal PHYs on the MDIO bus and each port
> + can access the Switch register space by configuring the PHY page.
> +
> +$ref: dsa.yaml#/$defs/ethernet-ports
[Severity: Low]
Should the port unit addresses be limited to what the hardware has?
This binding inherits the generic port node pattern from
dsa.yaml#/$defs/ethernet-ports without narrowing it:
Documentation/devicetree/bindings/net/dsa/dsa.yaml:
"^(ethernet-)?port@[0-9a-f]+$":
The AN8855 has 6 ports. Ports 0-4 are user ports with internal PHYs and
port 5 is the CPU port, and the driver later in the series sets
ds->num_ports = AN8855_NUM_PORTS.
As a result, a DT with port@7 or port@1f still passes dt_binding_check
and dtbs_check. It is only rejected at probe time, and then the whole
switch fails to probe:
net/dsa/dsa.c:dsa_switch_parse_ports_of() {
...
if (reg >= ds->num_ports) {
dev_err(ds->dev, "port %pOF index %u exceeds num_ports (%u)\n",
...
}
Other DSA bindings with a fixed port count narrow the pattern under
ports: patternProperties. For example, mediatek,mt7530.yaml and
qca8k.yaml use "^(ethernet-)?port@[0-6]$", and renesas,rzn1-a5psw.yaml
uses "^(ethernet-)?port@[0-4]$".
Would something like "^(ethernet-)?port@[0-5]$" make sense here? This
file is unchanged at the end of the series.
[ ... ]
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260928194511.41878-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH net-next v24 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY
2026-09-28 19:45 ` [PATCH net-next v24 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY Christian Marangi
@ 2026-10-01 4:45 ` netdev-bot+sashiko
0 siblings, 0 replies; 17+ messages in thread
From: netdev-bot+sashiko @ 2026-10-01 4:45 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 2 potential
issue(s) to consider.
Critical: 0 · High: 0 · Medium: 1 · Low: 1
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [Medium] Both PHY nodes in the example in
Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml list…
- [Low] The example in
Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml gives…
--
dt-bindings: net: Document support for AN8855 Switch Internal PHY
This patch adds a DT binding for the internal PHYs of the Airoha AN8855
5-port Gigabit Switch, which are exposed on the MDIO bus. Each PHY can
optionally reference four eFUSE NVMEM cells (tx_a..tx_d) that hold TX
calibration data.
> diff --git a/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
> new file mode 100644
> index 0000000000000..d2f86116badf4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
[ ... ]
> +examples:
> + - |
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethernet-phy@1 {
> + compatible = "ethernet-phy-idc0ff.0410",
> + "ethernet-phy-ieee802.3-c45";
[Severity: Medium]
Should these PHYs be described as "ethernet-phy-ieee802.3-c22" and not
c45? Both example nodes use the c45 compatible.
In fwnode_mdiobus_register_phy(), the c45 compatible makes phylib ignore
the explicit PHY ID and probe the device using Clause 45:
drivers/net/mdio/fwnode_mdio.c:fwnode_mdiobus_register_phy() {
...
is_c45 = fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45");
if (is_c45 || fwnode_get_phy_id(child, &phy_id))
phy = get_phy_device(bus, addr, is_c45);
...
}
Each AN8855 PHY is on a per-PHY bus that an8855_phy_bus_register()
creates via devm_mdio_regmap_register(). That bus provides only C22
accessors:
drivers/net/mdio/mdio-regmap.c:devm_mdio_regmap_register() {
...
mii->read = mdio_regmap_read_c22;
mii->write = mdio_regmap_write_c22;
...
}
That means get_phy_c45_ids()->get_phy_c45_devs_in_pkg() gets -EOPNOTSUPP
and returns -EIO. The PHY registration then fails, and
an8855_core_probe() in drivers/mfd/airoha-an8855.c goes to
err_put_fwnodes. As a result, neither the PHYs nor the switch/efuse MFD
cells are registered.
The PHY driver in drivers/net/phy/air_an8855.c matches the C22 ID with
PHY_ID_MATCH_EXACT(0xc0ff0410) and uses C22 paged access. Also, the MFD
binding example in the same series (airoha,an8855.yaml) uses
"ethernet-phy-ieee802.3-c22" for these PHYs.
If a board DT follows this example, won't the whole AN8855 probe fail?
> +
> + reg = <1>;
> + };
> +
> + ethernet-phy@2 {
> + compatible = "ethernet-phy-idc0ff.0410",
> + "ethernet-phy-ieee802.3-c45";
> +
> + reg = <2>;
> +
> + nvmem-cells = <&shift_sel_port0_tx_a>,
> + <&shift_sel_port0_tx_b>,
> + <&shift_sel_port0_tx_c>,
> + <&shift_sel_port0_tx_d>;
[Severity: Low]
Is ethernet-phy@2 meant to get port 0's calibration cells here, while
ethernet-phy@1 gets none?
an8855_phy_bus_register() in drivers/mfd/airoha-an8855.c maps the MDIO
address to a port relative to the switch address:
phy_offset = addr - priv->switch_addr;
if (phy_offset >= AN8855_MAX_PHY_PORT)
return -EINVAL;
Because ethernet-phy@1 is present, switch_addr has to be 0 or 1. That
makes address 2 port 1 or port 2, and never port 0.
The eFUSE binding (airoha,an8855-efuse.yaml) has a separate tx_a..tx_d
set for each port, for example shift_sel_port0_tx_a@c and
shift_sel_port1_tx_a@1c. The MFD binding example in the same series
wires internal_phy1 (reg 1) to shift_sel_port0_* and internal_phy2
(reg 2) to shift_sel_port1_*, which does not match this example.
A DT copied from this example would have an8855_probe() read port 0's
R50-ohm values. an8855_config_init() would then write them into the
second PHY's AN8855_PHY_R50OHM_RSEL_TX_AB/CD registers, and the first
PHY would stay uncalibrated. No error would be reported.
Should the cells move to ethernet-phy@1, or should ethernet-phy@2 use
the shift_sel_port1_* cells?
> + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
> + };
> + };
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260928194511.41878-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH net-next v24 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC
2026-09-28 19:45 ` [PATCH net-next v24 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi
@ 2026-10-01 4:45 ` netdev-bot+sashiko
0 siblings, 0 replies; 17+ messages in thread
From: netdev-bot+sashiko @ 2026-10-01 4:45 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 3 potential
issue(s) to consider.
Critical: 0 · High: 0 · Medium: 2 · Low: 1
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [Medium] The series documents two different MDIO clauses for the same
AN8855 internal PHY (ethernet-phy-idc0ff.0410).
- [Medium] The binding defines reset-gpios with only 'maxItems: 1'
(airoha,an8855.yaml lines 26-27).
- [Low] The two binding examples in the series map the per-port eFUSE TX
calibration cells to PHY addresses in incompatible ways.
--
dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC
This adds a new YAML binding for the Airoha AN8855 Switch SoC MFD node.
The node has efuse, ethernet-switch and mdio children and an optional
reset-gpios property.
> diff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
> new file mode 100644
> index 0000000000000..48127e956c965
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
> @@ -0,0 +1,176 @@
[ ... ]
> + reg:
> + maxItems: 1
> +
> + reset-gpios:
> + maxItems: 1
[Severity: Medium]
The reset-gpios property doesn't describe the pin or its active level. The
only example uses:
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
Does anything in the series read this property?
drivers/mfd/airoha-an8855.c includes linux/gpio/consumer.h but never calls
gpiod_get*(). drivers/net/dsa/mediatek/an8855.c has no reset GPIO handling
either.
The MDIO core doesn't handle it for this node. The airoha,an8855 node is
registered as a non-PHY mdio_device, and the reset GPIO is only requested
for PHYs:
drivers/net/phy/mdio_device.c:mdiobus_register_device() {
...
if (mdiodev->flags & MDIO_DEVICE_FLAG_PHY) {
err = mdio_device_register_reset(mdiodev);
...
}
If the board's GPIO default holds RESET_N asserted, would the chip stay in
reset and cause an8855_read_switch_id() to fail?
Could the binding also state the expected polarity? When a consumer is
added, there are two options:
- It follows gpiod semantics (1 = assert). Then an ACTIVE_HIGH flag on an
active-low RESET_N would hold the chip in reset.
- It follows the inverted mt7530 convention. Then the DT ABI is tied to an
inverted flag.
I couldn't confirm the AN8855 pin polarity from a datasheet or from in-tree
code.
[ ... ]
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + internal_phy1: ethernet-phy@1 {
> + compatible = "ethernet-phy-idc0ff.0410",
> + "ethernet-phy-ieee802.3-c22";
[Severity: Medium]
This example declares the internal PHYs as Clause 22. The PHY binding
added earlier in the series ("dt-bindings: net: Document support for AN8855
Switch Internal PHY") uses Clause 45 for the same PHY ID in
Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml:
compatible = "ethernet-phy-idc0ff.0410",
"ethernet-phy-ieee802.3-c45";
Which one is intended?
With the MFD driver added later in the series, only c22 seems to work.
The bus comes from devm_mdio_regmap_register(), which only sets C22
accessors:
drivers/net/mdio/mdio-regmap.c:devm_mdio_regmap_register() {
...
mii->read = mdio_regmap_read_c22;
mii->write = mdio_regmap_write_c22;
...
}
If a board DT copies the PHY binding example, fwnode_mdiobus_register_phy()
sets is_c45 and the probe goes:
an8855_core_probe()
fwnode_mdiobus_register_phy()
get_phy_device(bus, addr, true)
get_phy_c45_ids()
get_phy_c45_devs_in_pkg()
__mdiobus_c45_read() <- -EOPNOTSUPP, no read_c45
get_phy_c45_ids() turns this into -EIO. an8855_core_probe() then takes the
err_put_fwnodes path, and none of the switch, efuse or PHY functions come
up.
dt_binding_check won't catch this, because ethernet-phy.yaml accepts both
compatibles. Should the PHY binding example use
ethernet-phy-ieee802.3-c22 to match this one?
> + reg = <1>;
> +
> + nvmem-cells = <&shift_sel_port0_tx_a>,
> + <&shift_sel_port0_tx_b>,
> + <&shift_sel_port0_tx_c>,
> + <&shift_sel_port0_tx_d>;
> + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
> + };
> +
> + internal_phy2: ethernet-phy@2 {
> + compatible = "ethernet-phy-idc0ff.0410",
> + "ethernet-phy-ieee802.3-c22";
> + reg = <2>;
> +
> + nvmem-cells = <&shift_sel_port1_tx_a>,
> + <&shift_sel_port1_tx_b>,
> + <&shift_sel_port1_tx_c>,
> + <&shift_sel_port1_tx_d>;
> + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
> + };
[Severity: Low]
Here, ethernet-phy@1 (the phy-handle of port@0) gets the
shift_sel_port0_tx_* cells and ethernet-phy@2 gets shift_sel_port1_tx_*.
The example in net/airoha,an8855-phy.yaml is different: ethernet-phy@2
references shift_sel_port0_tx_* and ethernet-phy@1 has no nvmem-cells.
The MFD driver treats the switch address as port 0's PHY:
drivers/mfd/airoha-an8855.c:an8855_phy_bus_register() {
...
phy_offset = addr - priv->switch_addr;
if (phy_offset >= AN8855_MAX_PHY_PORT)
return -EINVAL;
...
}
So when ethernet-phy@1 exists, ethernet-phy@2 can't be port 0. The PHY
driver in drivers/net/phy/air_an8855.c applies whatever tx_a..tx_d cells
the node references, with no cross-check.
Would a DT that follows the PHY binding example program port 0's TX
calibration into a different port? This example looks like the consistent
one. Should the PHY binding example be changed to match it?
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260928194511.41878-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH net-next v24 04/10] mfd: an8855: Add support for Airoha AN8855 Switch
2026-09-28 19:45 ` [PATCH net-next v24 04/10] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi
@ 2026-10-01 4:45 ` netdev-bot+sashiko
0 siblings, 0 replies; 17+ messages in thread
From: netdev-bot+sashiko @ 2026-10-01 4:45 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 7 potential
issue(s) to consider.
Critical: 0 · High: 0 · Medium: 4 · Low: 3
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [Medium] This patch adds the MFD_AIROHA_AN8855 symbol and registers an
'airoha,an8855-efuse' MFD cell.
- [Medium] The MFD binding (airoha,an8855.yaml) documents `reset-gpios`
on the AN8855 core node, and its example uses one.
- [Medium] The PHY binding example
(Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml)…
- [Medium] an8855_phy_bus_register() checks the DT PHY 'reg' only as an
offset from switch_addr (phy_offset = addr - switch_addr < 5), never…
- [Low] an8855_mdio_register() uses goto-based cleanup and scope-based
cleanup in the same function.
- [Low] an8855_core_probe() writes 0 to AN8855_RG_GPHY_AFE_PWD (line
534), which powers up the analog front end of all internal GPHYs.
- [Low] mfd: airoha-an8855: violates MFD naming conventions for private
structures
--
mfd: an8855: Add support for Airoha AN8855 Switch
This adds an MFD core driver for the Airoha AN8855 switch. It registers
efuse (NVMEM) and DSA switch child cells. It also creates an mdio-regmap
bus and a regmap for each internal PHY, so those PHYs can serve both as
PHYs and as the path for switch register access.
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index e4fd4572472f9..afbdcec0fce8f 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR
> using regmap_mmio accesses for ARM32 parts and SMC calls to
> EL3 for ARM64 parts.
>
> +config MFD_AIROHA_AN8855
> + tristate "Airoha AN8855 Switch Core"
> + select MFD_CORE
> + select REGMAP
> + select PHYLIB
> + select MDIO_REGMAP
> + depends on NETDEVICES && OF
> + help
> + Support for the Airoha AN8855 Switch Core. This is an SoC
> + that provides various peripherals, to count, i2c, an Ethrnet
> + Switch, a CPU timer, GPIO, eFUSE.
> +
> + Currently it provides a DSA switch and a NVMEM provider.
[Severity: Medium]
Now that this symbol exists, should NVMEM_AN8855_EFUSE in
drivers/nvmem/Kconfig get its dependency back?
Commit 4796eaafd6a1 ("nvmem: an8855: drop an unused Kconfig symbol")
removed "depends on MFD_AIROHA_AN8855 || COMPILE_TEST" only because this
symbol did not exist yet. The nvmem entry still has just:
config NVMEM_AN8855_EFUSE
...
depends on COMPILE_TEST
drivers/nvmem/Kconfig is not changed anywhere else in the series.
Without COMPILE_TEST, can any driver bind to the "airoha,an8855-efuse"
cell registered from an8855_cells? If not, the PHY calibration nvmem-cells
in the bindings can't be resolved. nvmem_cell_read_u32() in air_an8855.c
would then fail whenever a PHY node has nvmem-cells.
That seems to contradict the "NVMEM provider" described here and in the
commit message.
> diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c
> new file mode 100644
> index 0000000000000..cd5791ef436d9
> --- /dev/null
> +++ b/drivers/mfd/airoha-an8855.c
> @@ -0,0 +1,579 @@
[ ... ]
> +static int an8855_phy_bus_register(struct device *dev, struct an8855_core_priv *priv,
> + struct device_node *phy_np,
> + struct an8855_phy_bus *phy_bus_info)
> +{
[ ... ]
> + ret = of_property_read_u32(phy_np, "reg", &addr);
> + if (ret)
> + return ret;
> +
> + phy_offset = addr - priv->switch_addr;
> + if (phy_offset >= AN8855_MAX_PHY_PORT)
> + return -EINVAL;
[Severity: Medium]
Is the absolute addr ever checked against PHY_MAX_ADDR?
This only checks the offset from switch_addr. With the switch at MDIO
address 28-31, a DT "reg" of 32-35 gets through. an8855_core_probe() then
passes it to fwnode_mdiobus_register_phy(), which skips the
of_mdio_parse_addr() check that the normal OF path does.
With an explicit ethernet-phy-idXXXX.XXXX compatible, as in the binding
examples, can this index past the 32-entry arrays in struct mii_bus?
fwnode_mdiobus_phy_device_register()
mdio->irq[addr] = rc;
mdiobus_register_device()
if (mdiodev->bus->mdio_map[mdiodev->addr])
return -EBUSY;
...
mdiodev->bus->mdio_map[mdiodev->addr] = mdiodev;
phy_device_create() also reads bus->irq[addr], and the broken-turn-around
handling computes 1 << addr.
On 64-bit, irq[34] overlays the low word of bus->reset_gpiod. After an
interrupt write, the mdio_map[] check returns -EBUSY. mdiobus_unregister()
on the unwind path then calls gpiod_set_value_cansleep() on the corrupted
pointer.
On 32-bit, mdio_map[33] overlays phy_ignore_ta_mask. The PHY ends up in a
slot that mdiobus_unregister() never walks.
Such a DT would already violate mdio.yaml (reg max 31). Would an
"addr >= PHY_MAX_ADDR" check here still be worth adding?
[ ... ]
> + for_each_available_child_of_node_scoped(mdio_np, phy_np) {
> + if (i >= AN8855_MAX_PHY_PORT) {
> + ret = -EINVAL;
> + goto exit;
> + }
> +
> + ret = an8855_phy_bus_register(dev, priv, phy_np,
> + &phy_bus_infos[i]);
> + if (ret)
> + goto exit;
> +
> + i++;
> + }
> +
> +exit:
> + of_node_put(mdio_np);
[Severity: Low]
This isn't a bug, but an8855_mdio_register() mixes goto-based cleanup with
the scope-based __free(device_node) from
for_each_available_child_of_node_scoped(). include/linux/cleanup.h asks
that a routine use one style or the other, not both.
Nothing leaks today, because leaving the loop scope drops phy_np. Could
mdio_np be declared with __free(device_node), and the error paths return
directly after putting the fwnodes?
[ ... ]
> + /* Reset PHY page for switch address */
> + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
> + ret = an8855_mii_set_page(priv, priv->switch_addr,
> + AN8855_PHY_PAGE_STANDARD);
[Severity: Medium]
Should reset-gpios be handled before this first access?
The airoha,an8855.yaml binding documents reset-gpios on the core node, and
its example uses it. <linux/gpio/consumer.h> is included and AN8855_HWTRAP
is defined, but neither is used. an8855_core_probe() goes straight to MDIO
accesses, with no reset pulse, settle delay or HWTRAP ready poll.
The MDIO core won't handle it either. mdiobus_register_device() only sets
up the reset for PHY devices:
if (mdiodev->flags & MDIO_DEVICE_FLAG_PHY) {
err = mdio_device_register_reset(mdiodev);
For this plain mdio_device, reset_gpio stays NULL. The DSA driver later in
the series doesn't handle reset either.
On a board that leaves the line asserted, wouldn't the AN8855_CREV read
fail or return the wrong ID, so the whole device fails to probe? If the
line is left deasserted, the chip keeps whatever state the bootloader left.
[ ... ]
> + /* Release global PHY power down */
> + ret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0);
> + if (ret)
> + goto err_put_fwnodes;
> +
> + /* Register PHYs */
> + for (i = 0; i < num_phys; i++) {
> + ret = fwnode_mdiobus_register_phy(phy_bus_infos[i].bus,
> + phy_bus_infos[i].node,
> + phy_bus_infos[i].addr);
[Severity: Medium]
What happens here with a DT written from the PHY binding example? The
example in airoha,an8855-phy.yaml uses:
compatible = "ethernet-phy-idc0ff.0410",
"ethernet-phy-ieee802.3-c45";
The bus from devm_mdio_regmap_register() only has C22 accessors:
mii->read = mdio_regmap_read_c22;
mii->write = mdio_regmap_write_c22;
When the c45 compatible is present, fwnode_mdiobus_register_phy() probes
as C45 even if an explicit PHY ID is given:
is_c45 = fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45");
if (is_c45 || fwnode_get_phy_id(child, &phy_id))
phy = get_phy_device(bus, addr, is_c45);
get_phy_c45_ids() -> mdiobus_c45_read() then fails with -EOPNOTSUPP, and
get_phy_device() returns an error. The goto err_put_fwnodes fails the whole
probe, so the switch and efuse children are never created.
The MFD binding example uses "-c22", and air_an8855.c uses phy_*_mmd over
C22. Should the PHY binding example be changed to match? It is still
unchanged at the end of the series.
> + fwnode_handle_put(phy_bus_infos[i].node);
> + phy_bus_infos[i].node = NULL;
> +
> + if (ret)
> + goto err_put_fwnodes;
> + }
> +
> + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells,
> + ARRAY_SIZE(an8855_cells), NULL, 0,
> + NULL);
> +
> +err_put_fwnodes:
> + for (i = 0; i < num_phys; i++)
> + if (phy_bus_infos[i].node)
> + fwnode_handle_put(phy_bus_infos[i].node);
> +
> + return ret;
> +}
[Severity: Low]
Should the GPHYs be put back into power-down when probe fails?
AN8855_RG_GPHY_AFE_PWD is cleared before the PHYs are registered and before
devm_mfd_add_devices() runs. If either step fails, err_put_fwnodes only
drops the fwnode references. A devm_mfd_add_devices() error is returned
directly.
an8855_core_driver also has no .remove. mdio_probe() does nothing on
failure because reset_gpio is NULL here.
After a failed probe or an unbind, would the internal PHYs stay powered and
be able to bring links up with no driver owning them?
[ ... ]
> @@ -0,0 +1,579 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Core driver for Airoha AN8855 Switch
> + *
> + * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/fwnode_mdio.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/mfd/core.h>
> +#include <linux/mdio.h>
> +#include <linux/mdio/mdio-regmap.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/phy.h>
> +#include <linux/regmap.h>
> +
> +/* Register for HW trap status */
> +#define AN8855_HWTRAP 0x1000009c
> +
> +/*
> + * Register of the Switch ID
> + * (called Project ID in Documentation)
> + */
> +#define AN8855_CREV 0x10005000
> +#define AN8855_ID 0x8855 /* Switch ID */
> +
> +/* Register for GPHY Power Down
> + * Used to Toggle the Gigabit PHY power and enable them.
> + */
> +#define AN8855_RG_GPHY_AFE_PWD 0x1028c840
> +
> +/* MII Registers */
> +#define AN8855_PHY_SELECT_PAGE 0x1f
> +#define AN8855_PHY_PAGE GENMASK(2, 0)
> +#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
> +#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
> +#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4)
> +
> +/* MII Registers Page 4 */
> +#define AN8855_PBUS_MODE 0x10
> +#define AN8855_PBUS_MODE_ADDR_FIXED 0x0
> +#define AN8855_PBUS_MODE_ADDR_INCR BIT(15)
> +#define AN8855_PBUS_WR_ADDR_HIGH 0x11
> +#define AN8855_PBUS_WR_ADDR_LOW 0x12
> +#define AN8855_PBUS_WR_DATA_HIGH 0x13
> +#define AN8855_PBUS_WR_DATA_LOW 0x14
> +#define AN8855_PBUS_RD_ADDR_HIGH 0x15
> +#define AN8855_PBUS_RD_ADDR_LOW 0x16
> +#define AN8855_PBUS_RD_DATA_HIGH 0x17
> +#define AN8855_PBUS_RD_DATA_LOW 0x18
> +
> +#define AN8855_MAX_PHY_PORT 5
> +
> +struct an8855_core_priv {
> + struct mii_bus *bus;
> + struct mii_bus *phy_bus;
> + unsigned int switch_addr;
> + u16 current_page;
> +};
> +
> +struct an8855_phy_priv {
> + u8 addr;
> + struct an8855_core_priv *core;
> +};
> +
> +struct an8855_phy_bus {
> + struct mii_bus *bus;
> + struct fwnode_handle *node;
> + u8 addr;
> +};
> +
> +static const struct mfd_cell an8855_cells[] = {
> + MFD_CELL_OF("an8855-efuse", NULL, NULL, 0, 0,
> + "airoha,an8855-efuse"),
> + MFD_CELL_OF("an8855-switch", NULL, NULL, 0, 0,
> + "airoha,an8855-switch"),
> +};
> +
> +static int an8855_mii_set_page(struct an8855_core_priv *priv, u8 addr,
> + u8 page) __must_hold(&priv->bus->mdio_lock)
> +{
> + struct mii_bus *bus = priv->bus;
> + int ret;
> +
> + ret = __mdiobus_write(bus, addr, AN8855_PHY_SELECT_PAGE, page);
> + if (ret) {
> + dev_err_ratelimited(&bus->dev, "failed to set mii page\n");
> + return ret;
> + }
> +
> + /* Cache current page if next MII read/write is for Switch page */
> + priv->current_page = page;
> + return 0;
> +}
> +
> +static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg,
> + u32 *val) __must_hold(&bus->mdio_lock)
> +{
> + int lo, hi, ret;
> +
> + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
> + AN8855_PBUS_MODE_ADDR_FIXED);
> + if (ret)
> + goto err;
> +
> + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH,
> + upper_16_bits(reg));
> + if (ret)
> + goto err;
> +
> + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW,
> + lower_16_bits(reg));
> + if (ret)
> + goto err;
> +
> + hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH);
> + if (hi < 0) {
> + ret = hi;
> + goto err;
> + }
> +
> + lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW);
> + if (lo < 0) {
> + ret = lo;
> + goto err;
> + }
> +
> + *val = ((u32)hi << 16) | lo;
> +
> + return 0;
> +err:
> + dev_err_ratelimited(&bus->dev, "failed to read register\n");
> + return ret;
> +}
> +
> +/*
> + * Protect concurrent access to phy page if switch address also
> + * expose a PHY.
> + */
> +static void an8855_regmap_lock(struct an8855_core_priv *priv)
> +{
> + if (priv->phy_bus)
> + mutex_lock(&priv->phy_bus->mdio_lock);
> + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
> +}
> +
> +static void an8855_regmap_unlock(struct an8855_core_priv *priv)
> +{
> + mutex_unlock(&priv->bus->mdio_lock);
> + if (priv->phy_bus)
> + mutex_unlock(&priv->phy_bus->mdio_lock);
> +}
> +
> +static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
> +{
> + struct an8855_core_priv *priv = ctx;
> + struct mii_bus *bus = priv->bus;
> + u16 addr = priv->switch_addr;
> + int ret;
> +
> + an8855_regmap_lock(priv);
> + ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
> + if (ret < 0)
> + goto exit;
> +
> + ret = an8855_mii_read32(bus, addr, reg, val);
> +
> +exit:
> + an8855_regmap_unlock(priv);
> +
> + return ret < 0 ? ret : 0;
> +}
> +
> +static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg,
> + u32 val) __must_hold(&bus->mdio_lock)
> +{
> + int ret;
> +
> + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
> + AN8855_PBUS_MODE_ADDR_FIXED);
> + if (ret)
> + goto err;
> +
> + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH,
> + upper_16_bits(reg));
> + if (ret)
> + goto err;
> + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW,
> + lower_16_bits(reg));
> + if (ret)
> + goto err;
> +
> + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH,
> + upper_16_bits(val));
> + if (ret)
> + goto err;
> +
> + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW,
> + lower_16_bits(val));
> + if (ret)
> + goto err;
> +
> + return 0;
> +err:
> + dev_err_ratelimited(&bus->dev,
> + "failed to write an8855 register\n");
> + return ret;
> +}
> +
> +static int an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val)
> +{
> + struct an8855_core_priv *priv = ctx;
> + struct mii_bus *bus = priv->bus;
> + u16 addr = priv->switch_addr;
> + int ret;
> +
> + an8855_regmap_lock(priv);
> + ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
> + if (ret)
> + goto exit;
> +
> + ret = an8855_mii_write32(bus, addr, reg, val);
> +
> +exit:
> + an8855_regmap_unlock(priv);
> +
> + return ret < 0 ? ret : 0;
> +}
> +
> +static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask,
> + uint32_t write_val)
> +{
> + struct an8855_core_priv *priv = ctx;
> + struct mii_bus *bus = priv->bus;
> + u16 addr = priv->switch_addr;
> + u32 val;
> + int ret;
> +
> + an8855_regmap_lock(priv);
> + ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
> + if (ret)
> + goto exit;
> +
> + ret = an8855_mii_read32(bus, addr, reg, &val);
> + if (ret < 0)
> + goto exit;
> +
> + val &= ~mask;
> + val |= write_val & mask;
> + ret = an8855_mii_write32(bus, addr, reg, val);
> +
> +exit:
> + an8855_regmap_unlock(priv);
> +
> + return ret < 0 ? ret : 0;
> +}
> +
> +static const struct regmap_range an8855_readable_ranges[] = {
> + regmap_reg_range(0x10000000, 0x10000fff), /* SCU */
> + regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */
> + regmap_reg_range(0x10002000, 0x10002fff), /* MCU */
> + regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */
> + regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */
> + regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */
> + regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */
> + regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */
> + regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */
> + regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */
> + regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */
> + regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */
> + regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */
> + regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */
> + regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */
> + regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */
> + regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */
> + regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */
> + regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */
> + regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */
> + regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */
> + regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */
> + regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */
> + regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */
> + regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */
> + regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */
> + regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */
> +};
> +
> +static const struct regmap_access_table an8855_readable_table = {
> + .yes_ranges = an8855_readable_ranges,
> + .n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges),
> +};
> +
> +static const struct regmap_config an8855_regmap_config = {
> + .name = "switch",
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = 0xbfffffff,
> + .reg_read = an8855_regmap_read,
> + .reg_write = an8855_regmap_write,
> + .reg_update_bits = an8855_regmap_update_bits,
> + .disable_locking = true,
> + .rd_table = &an8855_readable_table,
> +};
> +
> +static int an8855_regmap_phy_reset_page(struct an8855_core_priv *priv,
> + int phy) __must_hold(&priv->bus->mdio_lock)
> +{
> + /* Check PHY page only for addr shared with switch */
> + if (phy != priv->switch_addr)
> + return 0;
> +
> + /* Don't restore page if it's not set to Switch page */
> + if (priv->current_page != AN8855_PHY_PAGE_EXTENDED_4)
> + return 0;
> +
> + /*
> + * Restore page to 0, PHY might change page right after but that
> + * will be ignored as it won't be a switch page.
> + */
> + return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);
> +}
> +
> +static int an8855_regmap_phy_read(void *ctx, uint32_t reg, uint32_t *val)
> +{
> + struct an8855_phy_priv *priv = ctx;
> + struct an8855_core_priv *core_priv;
> + u32 addr = priv->addr;
> + struct mii_bus *bus;
> + int ret;
> +
> + core_priv = priv->core;
> + bus = core_priv->bus;
> +
> + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
> + ret = an8855_regmap_phy_reset_page(core_priv, addr);
> + if (ret)
> + goto exit;
> +
> + ret = __mdiobus_read(bus, addr, reg);
> + if (ret >= 0)
> + *val = ret;
> +
> +exit:
> + mutex_unlock(&bus->mdio_lock);
> +
> + return ret < 0 ? ret : 0;
> +}
> +
> +static int an8855_regmap_phy_write(void *ctx, uint32_t reg, uint32_t val)
> +{
> + struct an8855_phy_priv *priv = ctx;
> + struct an8855_core_priv *core_priv;
> + u32 addr = priv->addr;
> + struct mii_bus *bus;
> + int ret;
> +
> + core_priv = priv->core;
> + bus = core_priv->bus;
> +
> + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
> + ret = an8855_regmap_phy_reset_page(core_priv, addr);
> + if (ret)
> + goto exit;
> +
> + ret = __mdiobus_write(bus, addr, reg, val);
> +
> +exit:
> + mutex_unlock(&bus->mdio_lock);
> +
> + return ret;
> +}
> +
> +static const struct regmap_config an8855_phy_regmap_config = {
> + .reg_bits = 16,
> + .val_bits = 16,
> + .reg_read = an8855_regmap_phy_read,
> + .reg_write = an8855_regmap_phy_write,
> + .disable_locking = true,
> + .max_register = 0x1f,
> +};
> +
> +static int an8855_read_switch_id(struct device *dev, struct regmap *regmap)
> +{
> + u32 id;
> + int ret;
> +
> + ret = regmap_read(regmap, AN8855_CREV, &id);
> + if (ret)
> + return ret;
> +
> + if (id != AN8855_ID) {
> + dev_err(dev, "Detected Switch ID %x but %x was expected\n",
> + id, AN8855_ID);
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> +static int an8855_phy_bus_register(struct device *dev, struct an8855_core_priv *priv,
> + struct device_node *phy_np,
> + struct an8855_phy_bus *phy_bus_info)
> +{
> + struct mdio_regmap_config mrc = { };
> + struct an8855_phy_priv *phy_priv;
> + struct regmap *regmap;
> + u32 addr, phy_offset;
> + struct mii_bus *bus;
> + int ret;
> +
> + ret = of_property_read_u32(phy_np, "reg", &addr);
> + if (ret)
> + return ret;
> +
> + phy_offset = addr - priv->switch_addr;
> + if (phy_offset >= AN8855_MAX_PHY_PORT)
> + return -EINVAL;
> +
> + phy_priv = devm_kzalloc(dev, sizeof(*phy_priv), GFP_KERNEL);
> + if (!phy_priv)
> + return -ENOMEM;
> +
> + phy_priv->addr = addr;
> + phy_priv->core = priv;
> +
> + regmap = devm_regmap_init(dev, NULL, phy_priv, &an8855_phy_regmap_config);
> + if (IS_ERR(regmap))
> + return dev_err_probe(dev, PTR_ERR(regmap),
> + "phy%d regmap initialization failed\n",
> + addr);
> +
> + mrc.regmap = regmap;
> + mrc.parent = dev;
> + mrc.valid_addr = addr;
> + snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-phy%u", dev_name(dev), addr);
> +
> + bus = devm_mdio_regmap_register(dev, &mrc);
> + if (IS_ERR(bus))
> + return PTR_ERR(bus);
> +
> + if (addr == priv->switch_addr)
> + priv->phy_bus = bus;
> +
> + phy_bus_info->bus = bus;
> + phy_bus_info->addr = addr;
> + phy_bus_info->node = fwnode_handle_get(of_fwnode_handle(phy_np));
> +
> + return 0;
> +}
> +
> +static int an8855_mdio_register(struct device *dev, struct an8855_core_priv *priv,
> + struct an8855_phy_bus *phy_bus_infos)
> +{
> + struct device_node *mdio_np;
> + int ret = 0;
> + int i = 0;
> +
> + mdio_np = of_get_child_by_name(dev->of_node, "mdio");
> + if (!mdio_np)
> + return -ENODEV;
> +
> + for_each_available_child_of_node_scoped(mdio_np, phy_np) {
> + if (i >= AN8855_MAX_PHY_PORT) {
> + ret = -EINVAL;
> + goto exit;
> + }
> +
> + ret = an8855_phy_bus_register(dev, priv, phy_np,
> + &phy_bus_infos[i]);
> + if (ret)
> + goto exit;
> +
> + i++;
> + }
> +
> +exit:
> + of_node_put(mdio_np);
> + if (ret) {
> + while (i--)
> + fwnode_handle_put(phy_bus_infos[i].node);
> +
> + return ret;
> + }
> +
> + return i;
> +}
> +
> +static int an8855_core_probe(struct mdio_device *mdiodev)
> +{
> + struct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] = { };
> + struct device *dev = &mdiodev->dev;
> + struct an8855_core_priv *priv;
> + struct regmap *regmap;
> + int num_phys;
> + int i, ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->bus = mdiodev->bus;
> + priv->switch_addr = mdiodev->addr;
> + /* No DMA for mdiobus, mute warning for DMA mask not set */
> + dev->dma_mask = &dev->coherent_dma_mask;
> +
> + /* Register virtual MDIO for each PHY */
> + num_phys = an8855_mdio_register(dev, priv, phy_bus_infos);
> + if (num_phys < 0)
> + return num_phys;
> +
> + regmap = devm_regmap_init(dev, NULL, priv, &an8855_regmap_config);
> + if (IS_ERR(regmap)) {
> + ret = PTR_ERR(regmap);
> + dev_err_probe(dev, ret, "regmap initialization failed\n");
> + goto err_put_fwnodes;
> + }
> +
> + /* Reset PHY page for switch address */
> + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
> + ret = an8855_mii_set_page(priv, priv->switch_addr,
> + AN8855_PHY_PAGE_STANDARD);
> + mutex_unlock(&priv->bus->mdio_lock);
> + if (ret)
> + goto err_put_fwnodes;
> +
> + ret = an8855_read_switch_id(dev, regmap);
> + if (ret)
> + goto err_put_fwnodes;
> +
> + /* Release global PHY power down */
> + ret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0);
> + if (ret)
> + goto err_put_fwnodes;
> +
> + /* Register PHYs */
> + for (i = 0; i < num_phys; i++) {
> + ret = fwnode_mdiobus_register_phy(phy_bus_infos[i].bus,
> + phy_bus_infos[i].node,
> + phy_bus_infos[i].addr);
> + fwnode_handle_put(phy_bus_infos[i].node);
> + phy_bus_infos[i].node = NULL;
> +
> + if (ret)
> + goto err_put_fwnodes;
> + }
> +
> + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells,
> + ARRAY_SIZE(an8855_cells), NULL, 0,
> + NULL);
> +
> +err_put_fwnodes:
> + for (i = 0; i < num_phys; i++)
> + if (phy_bus_infos[i].node)
> + fwnode_handle_put(phy_bus_infos[i].node);
> +
> + return ret;
> +}
> +
> +static const struct of_device_id an8855_core_of_match[] = {
> + { .compatible = "airoha,an8855" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, an8855_core_of_match);
> +
> +static struct mdio_driver an8855_core_driver = {
> + .probe = an8855_core_probe,
> + .mdiodrv.driver = {
> + .name = "an8855",
> + .of_match_table = an8855_core_of_match,
> + },
> +};
> +mdio_module_driver(an8855_core_driver);
> +
> +MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
> +MODULE_DESCRIPTION("Driver for Airoha AN8855");
> +MODULE_LICENSE("GPL");
[Severity: Low]
This isn't a functional problem, but the MFD convention is to name the
private data structure after the device and to call the instance
ddata, rather than using generic names like priv or info.
Here the core state is struct an8855_core_priv, the per-PHY context is
struct an8855_phy_priv, and an8855_core_probe(), the switch regmap
callbacks and an8855_phy_bus_register() all name the instance priv.
In an8855_regmap_phy_read() and an8855_regmap_phy_write(), priv is
the PHY context while core_priv is the core state, which makes it easy
to mix up which structure a given priv refers to.
Could struct an8855_core_priv be renamed after the device, e.g. struct
an8855 with a ddata instance, and the PHY context be given a matching
device-based name?
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260928194511.41878-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH net-next v24 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
2026-09-28 19:45 ` [PATCH net-next v24 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Christian Marangi
@ 2026-10-01 4:45 ` netdev-bot+sashiko
0 siblings, 0 replies; 17+ messages in thread
From: netdev-bot+sashiko @ 2026-10-01 4:45 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 4 potential
issue(s) to consider.
Critical: 0 · High: 0 · Medium: 3 · Low: 1
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [Medium] an8855_probe() (drivers/net/phy/air_an8855.c) reads the four
eFUSE NVMEM cells in .probe and returns any error as a probe failure.
- [Medium] AIR_AN8855_PHY has 'depends on NVMEM || !NVMEM'
(drivers/net/phy/Kconfig:101), so CONFIG_NVMEM=n is an explicitly…
- [Medium] The ETHTOOL_PHY_DOWNSHIFT tunable does not follow the retry-
count ABI.
- [Low] The PHY binding added in the series (commit "dt-bindings: net:
Document support for AN8855 Switch Internal PHY",…
--
net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
This adds a phylib driver for the internal gigabit PHYs of the Airoha
AN8855 switch. At probe time it reads per-pair R50 calibration values
from eFUSE NVMEM cells. config_init then applies them, along with
noise-reduction tuning and HW downshift enable, and the downshift tunable
is exposed through ethtool.
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index d3835597e3795..eca2ce135c86b 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -96,6 +96,12 @@ config AIR_AN8801_PHY
> help
> Currently supports the Airoha AN8801R PHY.
>
> +config AIR_AN8855_PHY
> + tristate "Airoha AN8855 Internal Gigabit PHY"
> + depends on NVMEM || !NVMEM
[Severity: Medium]
This dependency allows a CONFIG_NVMEM=n build. In that build
nvmem_cell_read_u32() is the inline stub:
include/linux/nvmem-consumer.h:
static inline int nvmem_cell_read_u32(struct device *dev,
const char *cell_id, u32 *val)
{
return -EOPNOTSUPP;
}
an8855_probe() still sets needs_calibration from
of_property_present(dev->of_node, "nvmem-cells"). It then returns the
-EOPNOTSUPP from an8855_get_r50ohm_val() as a probe failure.
nvmem-cells is optional in airoha,an8855-phy.yaml, and the MFD binding
example puts nvmem-cells on every PHY. On an NVMEM=n kernel, would a
DT that follows the binding leave every port bound to genphy instead of
this driver?
That would also drop the noise-reduction writes and the downshift setup
in an8855_config_init(), and neither of those depends on NVMEM.
Could probe treat -EOPNOTSUPP and -ENOENT as "no calibration" and
continue? dp83867_of_init_io_impedance() does this:
if (ret != -ENOENT && ret != -EOPNOTSUPP)
return phydev_err_probe(phydev, ret, ...);
> + help
> + Currently supports the internal Airoha AN8855 Switch PHY.
[ ... ]
> diff --git a/drivers/net/phy/air_an8855.c b/drivers/net/phy/air_an8855.c
> new file mode 100644
> index 0000000000000..bc22256fd5f95
> --- /dev/null
> +++ b/drivers/net/phy/air_an8855.c
[ ... ]
> +static int an8855_probe(struct phy_device *phydev)
> +{
> + struct device *dev = &phydev->mdio.dev;
> + struct air_an8855_priv *priv;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->needs_calibration = of_property_present(dev->of_node,
> + "nvmem-cells");
> +
> + if (priv->needs_calibration) {
> + int ret;
> +
> + ret = an8855_get_r50ohm_val(dev, "tx_a", &priv->calibration_data[0]);
> + if (ret)
> + return ret;
[Severity: Medium]
Can this succeed on the first probe? an8855_core_probe() in
drivers/mfd/airoha-an8855.c registers the PHYs before it creates the
eFUSE provider cell:
drivers/mfd/airoha-an8855.c:an8855_core_probe() {
...
/* Register PHYs */
for (i = 0; i < num_phys; i++) {
ret = fwnode_mdiobus_register_phy(phy_bus_infos[i].bus,
phy_bus_infos[i].node,
phy_bus_infos[i].addr);
...
return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells,
ARRAY_SIZE(an8855_cells), NULL, 0,
NULL);
}
So nvmem_cell_read_u32() here would return -EPROBE_DEFER on the first
probe of every PHY node that has nvmem-cells.
The DSA switch cell is added in the same devm_mfd_add_devices() call,
and fw_devlink does not follow phy-handle. If the switch attaches the
PHY while this driver is still deferred, phy_attach_direct() takes its
fallback:
if (!d->driver) {
if (phydev->is_c45)
d->driver = &genphy_c45_driver.mdiodrv.driver;
else
d->driver = &genphy_driver.mdiodrv.driver;
Would genphy then stay bound? If so, the R50 calibration, the
noise-reduction writes and the downshift setup would all be skipped
with no error.
There is also a Kconfig problem. NVMEM_AN8855_EFUSE in
drivers/nvmem/Kconfig currently has:
config NVMEM_AN8855_EFUSE
tristate "Airoha AN8855 eFuse support"
depends on COMPILE_TEST
On a non-COMPILE_TEST kernel with CONFIG_NVMEM=y the provider can never
exist. Would a DT that follows the MFD binding example then defer here
forever and always end up on genphy?
Should a missing provider fall back to running uncalibrated? Or should
AIR_AN8855_PHY be tied to the eFUSE provider in Kconfig?
[ ... ]
> +static int an8855_get_downshift(struct phy_device *phydev, u8 *data)
> +{
> + int val;
> +
> + val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);
> + if (val < 0)
> + return val;
> +
> + *data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :
> + DOWNSHIFT_DEV_DISABLE;
> +
> + return 0;
> +}
> +
> +static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)
> +{
> + u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;
> +
> + return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1,
> + AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT,
> + ds);
> +}
[Severity: Medium]
Do these follow the downshift retry-count ABI?
an8855_set_downshift() accepts any count from 1 to 254 and reduces it
to the single AN8855_PHY_EN_DOWN_SHIFT bit. It returns success even
though the hardware keeps its own fixed retry threshold.
ethtool_phy_tunable_valid() only checks length and type, so nothing
else rejects the value.
On the get side, an8855_get_downshift() reports
DOWNSHIFT_DEV_DEFAULT_COUNT (0xff) whenever the bit is set. That value
is a set-side sentinel, so ethtool would show "Downshift count: 255".
A set of 3 followed by a get would not read back 3.
Other drivers map the sentinel to a concrete count and reject counts
they cannot program. For example, bcm54140_set_downshift() does:
if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT)
return -EINVAL;
...
if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT)
cnt = BCM54140_DEFAULT_DOWNSHIFT;
microchip.c, mscc_main.c, qcom-phy-lib.c and marvell10g.c work the
same way.
Could this driver report the count the hardware actually uses, and
return -EINVAL for counts it cannot honor?
A smaller point: an8855_config_init() runs on every phy_init_hw() call
(attach and resume) and does:
/* Enable HW auto downshift */
ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
So a user's "downshift off" setting is re-enabled after resume. mtk-ge.c
and marvell10g.c do the same, so this part may be acceptable.
[ ... ]
> +static struct phy_driver an8855_driver[] = {
> +{
> + PHY_ID_MATCH_EXACT(AN8855_PHY_ID),
> + .name = "Airoha AN8855 internal PHY",
> + /* PHY_GBIT_FEATURES */
> + .flags = PHY_IS_INTERNAL,
[ ... ]
> + .read_page = an8855_read_page,
> + .write_page = an8855_write_page,
> +}, };
[Severity: Low]
This one is in another patch in the series, but it affects how this
driver gets probed. The examples in the PHY binding
(Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml) use:
compatible = "ethernet-phy-idc0ff.0410",
"ethernet-phy-ieee802.3-c45";
mfd/airoha,an8855.yaml uses "ethernet-phy-ieee802.3-c22" for the same
PHYs. The driver and the bus are both Clause 22 only, since
devm_mdio_regmap_register() sets only mii->read and mii->write.
If a DT copies the PHY binding example, fwnode_mdiobus_register_phy()
sees the c45 compatible:
is_c45 = fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45");
if (is_c45 || fwnode_get_phy_id(child, &phy_id))
phy = get_phy_device(bus, addr, is_c45);
Wouldn't get_phy_c45_ids() then fail with -EIO on this C22-only bus?
That would make an8855_core_probe() fail for the whole MFD (switch,
PHYs and eFUSE).
Should the example use "ethernet-phy-ieee802.3-c22" instead?
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260928194511.41878-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH net-next v24 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG
2026-09-28 19:45 ` [PATCH net-next v24 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG Christian Marangi
@ 2026-10-01 4:45 ` netdev-bot+sashiko
0 siblings, 0 replies; 17+ messages in thread
From: netdev-bot+sashiko @ 2026-10-01 4:45 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 2 potential
issue(s) to consider.
Critical: 0 · High: 0 · Medium: 1 · Low: 1
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [Medium] This patch adds a new tag protocol, DSA_TAG_PROTO_AIROHA
("airoha").
- [Low] After this patch, tag_mtk.ko can register both the "mtk" and
"airoha" tag drivers through…
--
net: dsa: tag_mtk: add Airoha variant usage of this TAG
This commit adds a new DSA_TAG_PROTO_AIROHA tag protocol ("airoha") that
reuses the existing MTK tag xmit/rcv handlers. It adds a comment noting
that AN8855 lacks the SA_DIS and Leaky VLAN tag bits. It also reworks
Kconfig and the Makefile so tag_mtk.o is built through a common
NET_DSA_TAG_MTK_COMMON symbol and registers either or both taggers.
> diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
> index c7dc7731675ec..f8087d768da6d 100644
> --- a/net/dsa/tag_mtk.c
> +++ b/net/dsa/tag_mtk.c
[ ... ]
> @@ -107,8 +112,33 @@ static const struct dsa_device_ops mtk_netdev_ops = {
> .needed_headroom = MTK_HDR_LEN,
> };
>
> -MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
> -MODULE_LICENSE("GPL");
> +DSA_TAG_DRIVER(mtk_netdev_ops);
> MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);
> +#endif
>
> -module_dsa_tag_driver(mtk_netdev_ops);
> +#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
> +static const struct dsa_device_ops airoha_netdev_ops = {
> + .name = AIROHA_NAME,
> + .proto = DSA_TAG_PROTO_AIROHA,
> + .xmit = mtk_tag_xmit,
> + .rcv = mtk_tag_rcv,
> + .needed_headroom = MTK_HDR_LEN,
> +};
[Severity: Medium]
The wire format here is the same as DSA_TAG_PROTO_MTK. However, the
conduit drivers that handle the MTK special tag in hardware check the
protocol ID, not the format. Will they still handle a conduit that uses
the "airoha" tagger correctly?
Later in the series, an8855_get_tag_protocol() returns
DSA_TAG_PROTO_AIROHA. No later patch updates these checks, which still
only match DSA_TAG_PROTO_MTK:
drivers/net/ethernet/mediatek/mtk_ppe_offload.c:mtk_flow_get_dsa_port() {
...
if (dp->cpu_dp->tag_ops->proto != DSA_TAG_PROTO_MTK)
return -ENODEV;
...
}
drivers/net/ethernet/mediatek/mtk_ppe.c:__mtk_ppe_check_skb() {
...
if (!netdev_uses_dsa(skb->dev) ||
skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)
goto out;
...
}
With an AN8855 behind a mtk_eth_soc conduit, it looks like PPE/flowtable
offload to the switch user ports would be silently unavailable.
On netsys v1, mtk_uses_dsa() also compares only against
DSA_TAG_PROTO_MTK:
drivers/net/ethernet/mediatek/mtk_eth_soc.c:mtk_uses_dsa() {
return netdev_uses_dsa(dev) &&
dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK;
}
So mtk_open() skips the dsa_meta allocation and takes the else branch:
} else {
...
val &= ~MTK_CDMP_STAG_EN;
mtk_w32(eth, val, MTK_CDMP_IG_CTRL);
mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
}
Meanwhile, mtk_gdm_config() still sets MTK_GDMA_SPECIAL_TAG and
mtk_tx_set_dma_desc_v2() still sets TX_DMA_SPTAG_V3 for any DSA conduit.
Does this leave the MAC only partly configured for the special tag?
On Airoha SoCs, airoha_get_dsa_tag() has the same kind of check:
drivers/net/ethernet/airoha/airoha_eth.c:airoha_get_dsa_tag() {
...
if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)
return 0;
...
default:
/* PPE module requires untagged DSA packets to work properly,
* so move DSA tag to DMA descriptor.
*/
memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN);
__skb_pull(skb, MTK_HDR_LEN);
break;
...
}
With the new protocol, the in-band tag stays in the frame and 0 is
written to QDMA_ETH_TXMSG_SP_TAG_MASK. airoha_dev_xmit() still requests
TCO/UCO/ICO checksum offload and TSO for that frame.
On RX, airoha_dev_open() sets GDM_STAG_EN_MASK for any DSA conduit, so
RX and TX handling of the tag would not match. Whether this corrupts
checksums or makes the hardware insert a second tag depends on hardware
behaviour, and the code alone can't show which.
The commit message says the change is about giving external tools like
libpcap a dedicated name. Should these conduit checks also accept
DSA_TAG_PROTO_AIROHA? One option is a helper that means "uses the MTK
special tag format".
> +
> +DSA_TAG_DRIVER(airoha_netdev_ops);
> +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_AIROHA, AIROHA_NAME);
> +#endif
> +
> +static struct dsa_tag_driver *dsa_tag_driver_array[] = {
> +#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)
> + &DSA_TAG_DRIVER_NAME(mtk_netdev_ops),
> +#endif
> +#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
> + &DSA_TAG_DRIVER_NAME(airoha_netdev_ops),
> +#endif
> +};
> +
> +module_dsa_tag_drivers(dsa_tag_driver_array);
> +
> +MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
[Severity: Low]
This isn't a bug, but should the module description be updated here?
The module can now register the "airoha" tagger too. With only
CONFIG_NET_DSA_TAG_AIROHA enabled, it registers only the Airoha tagger,
but modinfo still reports "DSA tag driver for Mediatek switches".
> +MODULE_LICENSE("GPL");
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260928194511.41878-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH net-next v24 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver
2026-09-28 19:45 ` [PATCH net-next v24 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Christian Marangi
@ 2026-10-01 4:45 ` netdev-bot+sashiko
0 siblings, 0 replies; 17+ messages in thread
From: netdev-bot+sashiko @ 2026-10-01 4:45 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 12 potential
issue(s) to consider.
Critical: 0 · High: 2 · Medium: 7 · Low: 3
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [High] In the AN8855 driver, the shared VLAN read-modify-write path
reads the VLAN write-data register (AN8855_VAWD0) back, not the read-…
- [High] an8855_port_enable() sets ports[port].enable and turns on PMCR
TX/RX, but it never writes the cached forwarding matrix…
- [Medium] mt7530_lib_port_change_mtu() writes DIV_ROUND_UP(length, 1024)
into MT7530_GMACCR_MAX_RX_JUMBO.
- [Medium] an8855_set_mac_eee() rejects any tx_lpi_timer > 0xFFF (4095
us).
- [Medium] The new an8855_mib table exposes, as private ethtool -S
strings, counters that already have standard uAPI homes, and the…
- [Medium] an8855_setup() clears the AN8855_UNIPMF (IP unknown-multicast
flood) bit for every user port, and nothing sets it again.
- [Medium] an8855_pcs_config() updates AN8855_PLL_CTRL_2 with
AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, a field an8855.h defines in…
- [Medium] SGMII without in-band negotiation is always forced to 1000
Mb/s in the PCS.
- [Medium] an8855_port_fdb_dump() declares 'u32 rsp;' without
initialising it and passes it to mt7530_lib_fdb_cmd().
- [Low] NET_DSA_AN8855 can be enabled with COMPILE_TEST and
CONFIG_REGMAP=n.
- [Low] an8855_pcs_config() changes several mode-specific SerDes/PCS bits
in one direction only.
- [Low] an8855_rmon_ranges gives the top RMON histogram bucket as { 1519,
AN8855_MAX_MTU }.
--
net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver
This patch adds a DSA driver for the switch inside the Airoha AN8855. It
reuses the shared mt7530-lib helpers through a per-chip regmap_field
table, and it extends the lib with several AN8855-specific fields. It
also adds a PCS for the SGMII/2500base-X CPU port and EEE support.
> diff --git a/drivers/net/dsa/mediatek/Kconfig b/drivers/net/dsa/mediatek/Kconfig
> index 7b48300dca0c5..2799e78a86517 100644
> --- a/drivers/net/dsa/mediatek/Kconfig
> +++ b/drivers/net/dsa/mediatek/Kconfig
> @@ -1,4 +1,14 @@
> # SPDX-License-Identifier: GPL-2.0-only
> +config NET_DSA_AN8855
> + tristate "Airoha AN8855 Ethernet switch support"
> + depends on MFD_AIROHA_AN8855 || COMPILE_TEST
> + depends on NET_DSA
> + select NET_DSA_MT7530_LIB
> + select NET_DSA_TAG_AIROHA
[Severity: Low]
Can this fail to build with COMPILE_TEST=y, MFD_AIROHA_AN8855=n and
CONFIG_REGMAP=n?
REGMAP is only guaranteed through the select REGMAP in
MFD_AIROHA_AN8855. Neither NET_DSA_MT7530_LIB nor NET_DSA selects it.
In include/linux/regmap.h, struct reg_field and devm_regmap_field_alloc()
only exist under CONFIG_REGMAP, and there are no stubs for them.
struct mt7530_reg_field and an8855_setup_lib_priv() use both.
Is a select REGMAP needed on NET_DSA_AN8855 or NET_DSA_MT7530_LIB?
> diff --git a/drivers/net/dsa/mediatek/an8855.c b/drivers/net/dsa/mediatek/an8855.c
> new file mode 100644
> index 0000000000000..b4b02b7cb6eb8
> --- /dev/null
> +++ b/drivers/net/dsa/mediatek/an8855.c
> @@ -0,0 +1,1741 @@
[ ... ]
> + { MT7530_VAWD_IVL_MAC, REG_FIELD(AN8855_VAWD0, 5, 5) },
> + { MT7530_VAWD_EG_CON, REG_FIELD(AN8855_VAWD0, 11, 11) },
> + { MT7530_VAWD_VTAG_EN, REG_FIELD(AN8855_VAWD0, 10, 10) },
> + { MT7530_VAWD_PORT_MEM, REG_FIELD(AN8855_VAWD0, 26, 31) },
> + { MT7530_VAWD_FID, REG_FIELD(AN8855_VAWD0, 1, 4) },
> + { MT7530_VAWD_VLAN_VALID, REG_FIELD(AN8855_VAWD0, 0, 0) },
> + { __MT7530_VAWD1, REG_FIELD(AN8855_VAWD0, 0, 31) },
> +
> + { MT7530_VAWD_ETAG, REG_FIELD(AN8855_VAWD0, 12, 23) },
> + { __MT7530_VAWD2, REG_FIELD(AN8855_VAWD1, 0, 31) },
[Severity: High]
On AN8855, do the VLAN read-modify-write paths in mt7530-lib.c read
back the correct register?
After the VTCR read command, mt7530_hw_vlan_update() reads the entry
through the VAWD fields:
mt7530_hw_vlan_update() {
...
mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
regmap_field_read(priv->fields[MT7530_VAWD_PORT_MEM], &val);
entry->old_members = val;
...
}
mt7530_hw_vlan_del() also checks:
regmap_field_read(priv->fields[MT7530_VAWD_VLAN_VALID], &val);
if (!val) {
In this table all of those fields map to AN8855_VAWD0, which is the
write-data register. an8855.h defines a read-data register, but nothing
uses it:
/* Same register field of VAWD0 */
#define AN8855_VARD0 0x10200618
If the hardware puts the read result in VARD0, the fetched entry is
whatever was last written to VAWD0. For example, an8855_setup() ends
with mt7530_lib_setup_vlan0(), which leaves PORT_MEM set to all members
and VALID=1. The first bridge VLAN add would then read old_members as
all ports.
Could this make ports members of VIDs they were never added to, or carry
ETAG bits from one VID to another?
Could it also let mt7530_hw_vlan_del() see a stale VALID=0, after which
WR_VID writes stale data over a live VLAN?
> +static const struct mt7530_mib_desc an8855_mib[] = {
> + MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),
> + MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"),
> + MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"),
[ ... ]
> + MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"),
> + MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"),
> + MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"),
[Severity: Medium]
Should some of these counters go through the standard interfaces rather
than ethtool -S?
RxCrcErr matches the eth-mac FrameCheckSequenceErrors counter and
rtnl_link_stats64.rx_crc_errors. TxCollision matches collisions, and
RxDrop/TxDrop match rx_dropped/tx_dropped.
mt7530_lib_get_eth_mac_stats() never fills FrameCheckSequenceErrors.
an8855_switch_ops also has no .get_stats64, while mt7530.c implements
mt7530_get_stats64() from the same MIB.
[ ... ]
> +static int an8855_port_fdb_dump(struct dsa_switch *ds, int port,
> + dsa_fdb_dump_cb_t *cb, void *data)
> +{
> + struct an8855_priv *priv = ds->priv;
> + int banks, count = 0;
> + u32 rsp;
> + int ret;
> + int i;
[ ... ]
> + ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START,
> + AN8855_FDB_MAT_MAC_PORT, &rsp);
> + if (ret < 0)
> + goto exit;
> +
> + do {
> + /* From response get the number of banks to read, exit if 0 */
> + banks = FIELD_GET(AN8855_ATC_HIT, rsp);
[Severity: Medium]
Can rsp be used uninitialized here?
mt7530_lib_fdb_cmd() ignores the result of its final read and returns 0
anyway:
if (rsp)
regmap_field_read(priv->fields[__MT7530_ATC], rsp);
return 0;
regmap_field_read() leaves *val untouched when it fails. If that read
fails after FDB_START, FIELD_GET() runs on an uninitialized stack value.
After FDB_NEXT it would run on a stale value.
Should rsp be initialized, or should mt7530_lib_fdb_cmd() return the read
error?
[ ... ]
> +static int an8855_port_max_mtu(struct dsa_switch *ds, int port)
> +{
> + return AN8855_MAX_MTU;
> +}
[Severity: Medium]
Does mt7530_lib_port_change_mtu() program a valid jumbo value on AN8855?
It writes the MT7530 linear encoding:
regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_JUMBO],
DIV_ROUND_UP(length, 1024));
an8855.h documents a non-linear encoding for this field:
#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9)
#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa)
#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb)
#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc)
At AN8855_MAX_MTU, length is 15338 + 14 + 4 + 4 = 15360, so 0xf gets
written, and that value is not defined.
More generally, frame lengths from 12289 to 15360 give 0xd-0xf. Lengths
from 9217 to 12288 give 0xa-0xc, which the hardware would read as
12K/15K/16K.
[ ... ]
> +static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = {
[ ... ]
> + { 1024, 1518 },
> + { 1519, AN8855_MAX_MTU },
> + {}
> +};
[Severity: Low]
Should the top bucket's upper bound be a frame length?
The other buckets are frame lengths in octets. AN8855_MAX_MTU (15338) is
an L3 MTU, while the PKT_SZ_1519_TO_MAX counter counts frames up to
15360 bytes.
[ ... ]
> +static int an8855_port_enable(struct dsa_switch *ds, int port,
> + struct phy_device *phy)
> +{
> + struct an8855_priv *priv = ds->priv;
> + int ret;
> +
> + mutex_lock(&priv->reg_mutex);
> + priv->ports[port].enable = true;
> + ret = regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
> + AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
> + mutex_unlock(&priv->reg_mutex);
> +
> + return ret;
> +}
[Severity: High]
Should this also write the cached port matrix to hardware?
mt7530_update_port_member() skips the hardware write for disabled ports:
if (priv->ports[port].enable)
regmap_fields_write(priv->fields[MT7530_PCR_MATRIX],
port, port_bitmap);
mt7530_port_enable() in mt7530.c then applies it when the port comes up:
regmap_update_bits(priv->regmap, MT7530_PCR_P(port), PCR_MATRIX_MASK,
PCR_MATRIX(priv->ports[port].pm));
an8855_setup() calls an8855_port_disable() for every user port, so every
port starts with enable=false.
If a port joins a bridge, or is marked isolated, while it is down, does
that matrix ever reach AN8855_PORTMATRIX_P(port)?
If not, bridged ports would not forward to each other in hardware, and an
isolated port would still reach its peers.
[ ... ]
> +static int an8855_set_mac_eee(struct dsa_switch *ds, int port,
> + struct ethtool_keee *e)
> +{
> + if (e->tx_lpi_timer > 0xFFF)
> + return -EINVAL;
> +
> + return 0;
> +}
[Severity: Medium]
Is the 0xFFF limit from MT7530 right for AN8855?
an8855_phylink_get_caps() reports the default timer from the 18-bit
AN8855_LPI_TXIDLE_THD_MASK field, in 2us units:
config->lpi_timer_default = FIELD_GET(AN8855_LPI_TXIDLE_THD_MASK, reg) *
AN8855_TX_LPI_UNIT;
That comes to about 60000us, and phylink reports it via get_eee.
ethtool set-eee does a get-modify-set. dsa_user_set_eee() therefore
passes the unchanged 60000us timer to set_mac_eee(), and the request is
aborted with -EINVAL.
Wouldn't that make "ethtool --set-eee lanX eee off" fail unless tx-timer
is also lowered to 4095 or less?
an8855_phylink_mac_enable_tx_lpi() accepts timers up to the full 18-bit
field and clamps them.
[ ... ]
> + /* Disable Unknown Multicast Forward on user ports */
> + ret = regmap_clear_bits(priv->regmap, AN8855_UNMF, BIT(dp->index));
> + if (ret)
> + return ret;
> +
> + ret = regmap_clear_bits(priv->regmap, AN8855_UNIPMF, BIT(dp->index));
> + if (ret)
> + return ret;
[Severity: Medium]
What sets a user port's AN8855_UNIPMF bit again after this?
an8855_port_pre_bridge_flags() accepts BR_MCAST_FLOOD, but
mt7530_lib_port_bridge_flags() only updates the UNMF mask:
if (flags.mask & BR_MCAST_FLOOD)
regmap_field_update_bits(priv->fields[MT7530_UNM_FFP],
With this, is unknown IP multicast still not flooded between bridged user
ports when mcast_flood is on, which is the bridge default?
[ ... ]
> + /* PLL - SDM */
> + ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
> + AN8855_RG_DA_QP_PLL_SDM_HREN_INTF,
> + FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0));
> + if (ret)
> + return ret;
[Severity: Medium]
Should this register be AN8855_PLL_CTRL_4?
an8855.h defines the field under PLL_CTRL_4:
#define AN8855_PLL_CTRL_4 0x1022e410
#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)
In PLL_CTRL_2, bits 4:2 hold AN8855_RG_DA_QP_PLL_BPA_INTF, which the
"PLL - LPF" step just set to 0x5.
Clearing bits 4:3 here changes BPA to 0x1, and SDM_HREN in PLL_CTRL_4 is
never written.
[ ... ]
> + } else {
> + ret = regmap_update_bits(priv->regmap, AN8855_RG_AN_SGMII_MODE_FORCE,
> + AN8855_RG_FORCE_CUR_SGMII_MODE |
> + AN8855_RG_FORCE_CUR_SGMII_SEL,
> + AN8855_RG_FORCE_CUR_SGMII_SEL);
> + if (ret)
> + return ret;
[Severity: Low]
Several mode-specific bits in an8855_pcs_config() only ever change in
one direction.
These are only set: FORCE_TXC_SEL, FORCE_SPD_MODE_P0,
FORCE_CUR_SGMII_SEL, P0_MII_MODE, P0_RA_AN_EN and FORCE_AN_DONE.
These are only cleared: SGMII_MODE/SGMII_AN_EN, P0_DIS_MII_MODE and
P0_MII_RA_*.
For example, FORCE_SPD_MODE_P0 is set for forced SGMII but never cleared
for in-band SGMII.
Could moving between in-band SGMII, forced SGMII and 2500base-X, or
starting from a PCS the bootloader configured, leave a mix of register
state from two modes?
[ ... ]
> + /* Force Speed with fixed-link or 2500base-x as doesn't support aneg */
> + if (interface == PHY_INTERFACE_MODE_2500BASEX ||
> + neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
> + if (interface == PHY_INTERFACE_MODE_2500BASEX)
> + val = AN8855_RG_LINK_MODE_P0_SPEED_2500;
> + else
> + val = AN8855_RG_LINK_MODE_P0_SPEED_1000;
[Severity: Medium]
Does SGMII without in-band negotiation work at 10/100?
an8855_phylink_get_caps() advertises MAC_10 | MAC_100 along with SGMII
on port 5, but this code always forces the PCS to 1000.
an8855_phylink_mac_link_up() only updates PMCR, and an8855_pcs_ops has
no .pcs_link_up to program the resolved speed into the PCS.
With a 10/100 fixed-link, or an out-of-band PHY that resolves to 10/100,
would the PCS stay at 1000 while the MAC runs at the lower speed?
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260928194511.41878-1-ansuelsmth%40gmail.com
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2026-09-28 19:44 [PATCH net-next v24 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
2026-09-28 19:45 ` [PATCH net-next v24 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 04/10] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
2026-09-28 19:45 ` [PATCH net-next v24 07/10] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch Christian Marangi
2026-09-28 19:45 ` [PATCH net-next v24 08/10] net: dsa: move mediatek DSA driver in dedicated directory Christian Marangi
2026-09-28 19:45 ` [PATCH net-next v24 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Christian Marangi
2026-10-01 4:45 ` netdev-bot+sashiko
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