Re: [PATCH 02/24] ARM: l2c: Serialize device reads with cache maintenance when requested

[Navid Ghahremani <ghahramani.navid@gmail.com>]

Hi Arnd,

Thank you very much for the thoughtful advice and guidance.

I completely agree with the strategy of decoupling the problem. I have
dropped patches 01, 02, and 03 from the upstream submission, keeping the
outer-cache serialization workaround downstream in OpenWrt so that my
local test units remain stable while I get the clean platform code
upstreamed.

The v2 series now focuses entirely on the clean platform support:
1. Unified ARM/ZTE ZX SOC SUPPORT entry with Stefan Dösinger and myself
   as co-maintainers.
2. Split CRM DT schemas (topcrm vs lspcrpm) with fixed clock lists and
   simple-mfd reboot child.
3. Logical enum IDs for resets in include/dt-bindings/reset/.
4. Isolation of PCIe SerDes/PLL into a Generic PHY driver (#phy-cells = <0>)
   under drivers/phy/zte/, removing all raw syscon poking from the DWC
   PCIe host driver.
5. Integration of Stefan's tuned spi-zx.c driver with CCF dynamic clock
   scaling.
6. Header hygiene in platform drivers, avoiding <linux/mod_devicetable.h>.

Once the platform series is in good shape, I will explore using
lib/logic_iomem.c to see if I can register a transparent trapped MMIO
region for PCI reads as a cleaner long-term architectural solution for
the silicon crossbar flaw.

I will send out the formal v2 platform series shortly.

Best regards,
Navid