From: Navid Ghahremani <ghahramani.navid@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: arnd@arndb.de, stefandoesinger@gmail.com, krzk@kernel.org,
Navid Ghahremani <ghahramani.navid@gmail.com>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org
Subject: [PATCH v2 08/24] gpio: Add ZTE ZX279128S GPIO driver
Date: Wed, 14 Oct 2026 08:20:48 +0100 [thread overview]
Message-ID: <20261014072109.1759502-9-ghahramani.navid@gmail.com> (raw)
In-Reply-To: <20261014072109.1759502-1-ghahramani.navid@gmail.com>
Expose the six banks using the generic GPIO implementation and enable
the register clock before accessing the bank.
Signed-off-by: Navid Ghahremani <ghahramani.navid@gmail.com>
---
drivers/gpio/Kconfig | 12 ++++++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-zx279128s.c | 79 +++++++++++++++++++++++++++++++++++
3 files changed, 92 insertions(+)
create mode 100644 drivers/gpio/gpio-zx279128s.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index a48586bb8e..3ae51a3c10 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -902,6 +902,18 @@ config GPIO_ZEVIO
help
Say yes here to support the GPIO controller in LSI ZEVIO SoCs.
+config GPIO_ZX279128S
+ tristate "ZTE zx279128s GPIO support"
+ depends on ARCH_ZTE || COMPILE_TEST
+ select GPIO_GENERIC
+ help
+ Say yes here to support the GPIO controller of the ZTE zx279128s
+ SoC. It has several banks of 16 lines each, which boards such as
+ the ZTE ZXHN H3600 use for LEDs, buttons and reset lines.
+
+ To compile this driver as a module, choose M here: the module
+ will be called gpio-zx279128s.
+
config GPIO_ZYNQ
tristate "Xilinx Zynq GPIO support"
depends on ARCH_ZYNQ || ARCH_ZYNQMP || COMPILE_TEST
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index dc9e6d643b..a57ed7ec71 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -223,5 +223,6 @@ obj-$(CONFIG_GPIO_XLP) += gpio-xlp.o
obj-$(CONFIG_GPIO_XRA1403) += gpio-xra1403.o
obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o
obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
+obj-$(CONFIG_GPIO_ZX279128S) += gpio-zx279128s.o
obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
obj-$(CONFIG_GPIO_ZYNQMP_MODEPIN) += gpio-zynqmp-modepin.o
diff --git a/drivers/gpio/gpio-zx279128s.c b/drivers/gpio/gpio-zx279128s.c
new file mode 100644
index 0000000000..71eb6b5d82
--- /dev/null
+++ b/drivers/gpio/gpio-zx279128s.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ZTE zx279128s GPIO controller
+ *
+ * Copyright (C) 2026 Navid Ghahremani <ghahramani.navid@gmail.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/gpio/generic.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+/*
+ * Each bank has 16 lines, one bit per line in each register. The registers
+ * at 0x04-0x10 and 0x28-0x34 control the interrupts, which are not supported
+ * yet.
+ */
+#define ZX279128S_GPIO_DIR 0x00 /* 1: output */
+#define ZX279128S_GPIO_DATA 0x14 /* line level */
+#define ZX279128S_GPIO_SET 0x18 /* write 1: drive high */
+#define ZX279128S_GPIO_CLEAR 0x1c /* write 1: drive low */
+
+static int zx279128s_gpio_probe(struct platform_device *pdev)
+{
+ struct gpio_generic_chip_config config = { };
+ struct device *dev = &pdev->dev;
+ struct gpio_generic_chip *chip;
+ void __iomem *base;
+ struct clk *clk;
+ int ret;
+
+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "failed to get the clock\n");
+
+ config.dev = dev;
+ config.sz = 4;
+ config.dat = base + ZX279128S_GPIO_DATA;
+ config.set = base + ZX279128S_GPIO_SET;
+ config.clr = base + ZX279128S_GPIO_CLEAR;
+ config.dirout = base + ZX279128S_GPIO_DIR;
+
+ ret = gpio_generic_chip_init(chip, &config);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to set up the GPIO chip\n");
+
+ chip->gc.ngpio = 16;
+
+ return devm_gpiochip_add_data(dev, &chip->gc, NULL);
+}
+
+static const struct of_device_id zx279128s_gpio_of_match[] = {
+ { .compatible = "zte,zx279128s-gpio" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, zx279128s_gpio_of_match);
+
+static struct platform_driver zx279128s_gpio_driver = {
+ .probe = zx279128s_gpio_probe,
+ .driver = {
+ .name = "zx279128s-gpio",
+ .of_match_table = zx279128s_gpio_of_match,
+ },
+};
+module_platform_driver(zx279128s_gpio_driver);
+
+MODULE_AUTHOR("Navid Ghahremani <ghahramani.navid@gmail.com>");
+MODULE_DESCRIPTION("ZTE zx279128s GPIO controller driver");
+MODULE_LICENSE("GPL");
--
2.55.0
next prev parent reply other threads:[~2026-10-14 7:43 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-14 7:20 [PATCH v2 00/24] ARM: zte: Add support for Sanechips ZX279128S and ZTE ZXHN H3600 Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 01/24] MAINTAINERS: Consolidate ARM/ZTE ZX SOC SUPPORT with Stefan Doesinger Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 02/24] dt-bindings: arm: Add ZTE ZX279128S platform descriptions Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 03/24] ARM: zte: Add ZX279128S platform and CPU hotplug support Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 04/24] dt-bindings: clock: Add ZTE ZX279128S CRM clock bindings Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 05/24] dt-bindings: reset: Add ZTE ZX279128S reset controller bindings Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 06/24] clk: zte: Add ZX279128S CRM clock and reset driver Navid Ghahremani
2026-10-14 13:21 ` Philipp Zabel
2026-10-14 19:39 ` Stefan Dösinger
2026-10-14 7:20 ` [PATCH v2 07/24] dt-bindings: gpio: Add ZTE ZX279128S GPIO controller Navid Ghahremani
2026-10-14 7:20 ` Navid Ghahremani [this message]
2026-10-14 7:20 ` [PATCH v2 09/24] dt-bindings: pinctrl: pinctrl-single: Add ZTE ZX279128S pin mux Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 10/24] dt-bindings: phy: Add ZTE ZX279128S PCIe PHY binding Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 11/24] phy: zte: Add ZTE ZX279128S PCIe PHY driver Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 12/24] dt-bindings: PCI: Add ZTE ZX279128S host controller Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 13/24] PCI: dwc: Add ZTE ZX279128S host controller driver Navid Ghahremani
2026-10-14 13:19 ` Bjorn Helgaas
2026-10-14 7:20 ` [PATCH v2 14/24] dt-bindings: net: Add ZTE ZX279128S MDIO controller Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 15/24] net: mdio: " Navid Ghahremani
2026-10-14 12:13 ` Andrew Lunn
2026-10-14 7:20 ` [PATCH v2 16/24] net: phy: Add Sanechips ZX5201 PHY support Navid Ghahremani
2026-10-14 12:37 ` Andrew Lunn
2026-10-14 7:20 ` [PATCH v2 17/24] dt-bindings: net: Add ZTE ZX279128S Ethernet switch Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 18/24] net: ethernet: zte: Add ZX279128S Ethernet switch driver Navid Ghahremani
2026-10-14 7:20 ` [PATCH v2 19/24] dt-bindings: spi: Add ZTE ZX family SPI flash controller binding Navid Ghahremani
2026-10-14 7:21 ` [PATCH v2 20/24] spi: zx: Add ZTE ZX family SPI flash controller driver Navid Ghahremani
2026-10-14 19:28 ` Stefan Dösinger
2026-10-14 7:21 ` [PATCH v2 21/24] dt-bindings: usb: Add ZTE ZX279128S DWC3 controller Navid Ghahremani
2026-10-14 7:21 ` [PATCH v2 22/24] usb: dwc3: generic-plat: Add ZTE ZX279128S Navid Ghahremani
2026-10-14 7:21 ` [PATCH v2 23/24] ARM: dts: zte: Add ZX279128S SoC description Navid Ghahremani
2026-10-14 7:21 ` [PATCH v2 24/24] ARM: dts: zte: Add ZTE ZXHN H3600 board Navid Ghahremani
2026-10-14 12:52 ` Andrew Lunn
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261014072109.1759502-9-ghahramani.navid@gmail.com \
--to=ghahramani.navid@gmail.com \
--cc=arnd@arndb.de \
--cc=brgl@kernel.org \
--cc=krzk@kernel.org \
--cc=linusw@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=stefandoesinger@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox