[PATCH v4 0/2] Add device tree for NVIDIA VR-NVL BMC

[PATCH v4 0/2] Add device tree for NVIDIA VR-NVL BMC

[Jacky Huang]

This series adds the DT binding compatible and the device tree for
the NVIDIA VR-NVL BMC, an Aspeed AST2600-based BMC for the Vera
Rubin NVL compute platform.

Changes in v4:
- dts: address dt-check-style findings for property and child node
  ordering, required blank lines, and line length.
- dts: retain conventional multi-line block comments, which account
  for the remaining 8 mixed-indent findings.
- dts: retain 22 meaningful unused labels for source readability and
  future references. They can be removed if preferred.

Changes in v3:
- dts: reword the &mac0 comment per Andrew Lunn's feedback.

Changes in v2:
- dts: correct the compatible of the PDB I/O expander at 0x75 from
  nxp,pca9555 to nxp,pca9539 to match the actual part.
- Pick up Acked-by from Krzysztof Kozlowski on the binding.
- Pick up Reviewed-by from Andrew Lunn on the &mac0 and &mdio0 nodes.

v3: https://lore.kernel.org/all/20260710054849.3178747-1-jackyhuang@nvidia.com/
v2: https://lore.kernel.org/all/20260706101526.2556226-1-jackyhuang@nvidia.com/
v1: https://lore.kernel.org/all/20260702165524.2168091-1-jackyhuang@nvidia.com/

Jacky Huang (2):
  dt-bindings: arm: aspeed: Add NVIDIA VR-NVL BMC
  ARM: dts: aspeed: Add NVIDIA VR-NVL BMC

 .../bindings/arm/aspeed/aspeed.yaml           |   1 +
 arch/arm/boot/dts/aspeed/Makefile             |   1 +
 .../aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts   | 923 ++++++++++++++++++
 3 files changed, 925 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts

-- 
2.43.0

[PATCH v4 1/2] dt-bindings: arm: aspeed: Add NVIDIA VR-NVL BMC

[Jacky Huang]

Add NVIDIA's VR-NVL BMC board compatible.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jacky Huang <jackyhuang@nvidia.com>
---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index dd7996960de3..ce893553cfc3 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -114,6 +114,7 @@ properties:
               - jabil,rbp-bmc
               - nvidia,gb200nvl-bmc
               - nvidia,msx4-bmc
+              - nvidia,vr-nvl-bmc
               - qcom,dc-scm-v1-bmc
               - quanta,s6q-bmc
               - ufispace,ncplite-bmc
-- 
2.43.0

[PATCH v4 2/2] ARM: dts: aspeed: Add NVIDIA VR-NVL BMC

[Jacky Huang]

Add the device tree for the Aspeed AST2600 BMC for NVIDIA's Vera
Rubin NVL compute platform.

MAC0 uses phy-mode = "rgmii-id" because the on-board PHY supplies
both RGMII internal delays. The matching U-Boot device tree does not
enable SoC-side MAC clock delays, leaving the MAC internal delay at
zero so the PHY-provided delay is not doubled by the MAC controller.

The corresponding U-Boot change has been submitted to openbmc/u-boot:
Link: https://lore.kernel.org/all/20260629105202.1417679-1-jackyhuang@nvidia.com/

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jacky Huang <jackyhuang@nvidia.com>
---
v4: address dt-check-style findings for property and child node ordering,
    required blank lines, and line length. Retain 8 conventional multi-line
    block comments with mixed-indent and 22 meaningful unused labels for
    source readability and future references. They can be removed if
    preferred.

 arch/arm/boot/dts/aspeed/Makefile             |   1 +
 .../aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts   | 923 ++++++++++++++++++
 2 files changed, 924 insertions(+)
 create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts

diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
index 6b68671f9379..07e10083a8bd 100644
--- a/arch/arm/boot/dts/aspeed/Makefile
+++ b/arch/arm/boot/dts/aspeed/Makefile
@@ -65,6 +65,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-microsoft-olympus.dtb \
 	aspeed-bmc-nvidia-gb200nvl-bmc.dtb \
 	aspeed-bmc-nvidia-msx4-bmc.dtb \
+	aspeed-bmc-nvidia-vr-nvl-bmc.dtb \
 	aspeed-bmc-opp-lanyang.dtb \
 	aspeed-bmc-opp-mowgli.dtb \
 	aspeed-bmc-opp-nicole.dtb \
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts
new file mode 100644
index 000000000000..1c04fd3e627c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts
@@ -0,0 +1,923 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2026 NVIDIA Corporation
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	compatible = "nvidia,vr-nvl-bmc", "aspeed,ast2600";
+	model = "AST2600 VR NVL BMC";
+
+	aliases {
+		i2c16 = &i2c_usbhub;
+		i2c17 = &i2c_tpm;
+		i2c18 = &i2c_dp;
+		serial2 = &uart3;
+		serial4 = &uart5;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+	};
+
+	memory@80000000 {
+		reg = <0x80000000 0x80000000>;
+		device_type = "memory";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			gpios = <&exp4 10 GPIO_ACTIVE_LOW>;
+			label = "uid_led";
+		};
+
+		led-1 {
+			gpios = <&exp4 12 GPIO_ACTIVE_LOW>;
+			label = "fault_led";
+		};
+
+		led-2 {
+			gpios = <&exp4 8 GPIO_ACTIVE_LOW>;
+			label = "power_led";
+		};
+	};
+
+	standby_power_regulator: regulator-standby-power {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "standby_power";
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		vga_memory: framebuffer@9f000000 {
+			reg = <0x9f000000 0x01000000>;	/* 16 MiB */
+			no-map;
+		};
+
+		ramoops@a0000000 {
+			compatible = "ramoops";
+			reg = <0xa0000000 0x100000>;	/* 1 MiB */
+			max-reason = <2>;		/* KMSG_DUMP_OOPS */
+			record-size = <0x10000>;	/* 64 KiB */
+		};
+
+		gfx_memory: framebuffer {
+			compatible = "shared-dma-pool";
+			alignment = <0x01000000>;
+			reusable;
+			size = <0x01000000>;
+		};
+
+		video_engine_memory: jpegbuffer {
+			compatible = "shared-dma-pool";
+			alignment = <0x01000000>;
+			reusable;
+			size = <0x02000000>;		/* 32 MiB */
+		};
+	};
+};
+
+&ehci1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	status = "okay";
+
+	hub@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		hub@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			hub@4 {
+				reg = <4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* port 1: BlueField-4 SMA mgmt */
+				device@1 {
+					reg = <1>;
+					#address-cells = <2>;
+					#size-cells = <0>;
+
+					interface@1 {
+						reg = <1 1>;
+					};
+				};
+
+				cp2112g: device@2 {
+					reg = <2>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					gpio-line-names =
+						"BF4_USB_MCU_RECOVERY_L",
+						"BF4_USB_MCU_RST_L",
+						"BF4_USB_FORCE_FNP_L",
+						"BF4_GLOBAL_WP",
+						"BF4_FORCE_POR_L",
+						"BF4_BMC_EROT_RST_L",
+						"BF4_BMC_EROT_RECOVERY_L",
+						"BF4_THERM_SHUTDOWN";
+					#interrupt-cells = <2>;
+					interrupt-controller;
+				};
+			};
+		};
+
+		hub@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			hub@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				device@1 {
+					reg = <1>;
+					#address-cells = <2>;
+					#size-cells = <0>;
+
+					cp2112a: interface@1 {
+						reg = <1 1>;
+						#gpio-cells = <2>;
+						gpio-controller;
+						#interrupt-cells = <2>;
+						interrupt-controller;
+					};
+				};
+
+				hub@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					device@1 {
+						reg = <1>;
+						#address-cells = <2>;
+						#size-cells = <0>;
+
+						iob1_sma: interface@1 {
+							reg = <1 1>;
+							#gpio-cells = <2>;
+							gpio-controller;
+							#interrupt-cells = <2>;
+							interrupt-controller;
+						};
+					};
+
+					cp2112c: device@2 {
+						reg = <2>;
+						#gpio-cells = <2>;
+						gpio-controller;
+						gpio-line-names =
+							"IOB1_MCP_P0_2-B",
+							"IOB1_MCU_RST_L-O",
+							"IOB1_MCU_RECOVERY_L-O",
+							"IOB1_GLOBAL_WP-O",
+							"IOB1_GLOBAL_ADDR_L_R-O",
+							"IOB1_GLOBAL_ADDR_U_D-O",
+							"IOB1_PWR_EN-O",
+							"IOB1_MCU_READY_STATUS-I";
+						#interrupt-cells = <2>;
+						interrupt-controller;
+					};
+				};
+
+				hub@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					device@1 {
+						reg = <1>;
+						#address-cells = <2>;
+						#size-cells = <0>;
+
+						iob0_sma: interface@1 {
+							reg = <1 1>;
+							#gpio-cells = <2>;
+							gpio-controller;
+							#interrupt-cells = <2>;
+							interrupt-controller;
+						};
+					};
+
+					cp2112d: device@2 {
+						reg = <2>;
+						#gpio-cells = <2>;
+						gpio-controller;
+						gpio-line-names =
+							"IOB0_MCP_P0_2-B",
+							"IOB0_MCU_RST_L-O",
+							"IOB0_MCU_RECOVERY_L-O",
+							"IOB0_GLOBAL_WP-O",
+							"IOB0_GLOBAL_ADDR_L_R-O",
+							"IOB0_GLOBAL_ADDR_U_D-O",
+							"IOB0_PWR_EN-O",
+							"IOB0_MCU_READY_STATUS-I";
+						#interrupt-cells = <2>;
+						interrupt-controller;
+					};
+				};
+			};
+
+			hub@2 {
+				reg = <2>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				device@1 {
+					reg = <1>;
+					#address-cells = <2>;
+					#size-cells = <0>;
+
+					cp2112b: interface@1 {
+						reg = <1 1>;
+						#gpio-cells = <2>;
+						gpio-controller;
+						#interrupt-cells = <2>;
+						interrupt-controller;
+					};
+				};
+
+				hub@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					device@1 {
+						reg = <1>;
+						#address-cells = <2>;
+						#size-cells = <0>;
+
+						iob2_sma: interface@1 {
+							reg = <1 1>;
+							#gpio-cells = <2>;
+							gpio-controller;
+							#interrupt-cells = <2>;
+							interrupt-controller;
+						};
+					};
+
+					cp2112e: device@2 {
+						reg = <2>;
+						#gpio-cells = <2>;
+						gpio-controller;
+						gpio-line-names =
+							"IOB2_MCP_P0_2-B",
+							"IOB2_MCU_RST_L-O",
+							"IOB2_MCU_RECOVERY_L-O",
+							"IOB2_GLOBAL_WP-O",
+							"IOB2_GLOBAL_ADDR_L_R-O",
+							"IOB2_GLOBAL_ADDR_U_D-O",
+							"IOB2_PWR_EN-O",
+							"IOB2_MCU_READY_STATUS-I";
+						#interrupt-cells = <2>;
+						interrupt-controller;
+					};
+				};
+
+				hub@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					device@1 {
+						reg = <1>;
+						#address-cells = <2>;
+						#size-cells = <0>;
+
+						iob3_sma: interface@1 {
+							reg = <1 1>;
+							#gpio-cells = <2>;
+							gpio-controller;
+							#interrupt-cells = <2>;
+							interrupt-controller;
+						};
+					};
+
+					cp2112f: device@2 {
+						reg = <2>;
+						#gpio-cells = <2>;
+						gpio-controller;
+						gpio-line-names =
+							"IOB3_MCP_P0_2-B",
+							"IOB3_MCU_RST_L-O",
+							"IOB3_MCU_RECOVERY_L-O",
+							"IOB3_GLOBAL_WP-O",
+							"IOB3_GLOBAL_ADDR_L_R-O",
+							"IOB3_GLOBAL_ADDR_U_D-O",
+							"IOB3_PWR_EN-O",
+							"IOB3_MCU_READY_STATUS-I";
+						#interrupt-cells = <2>;
+						interrupt-controller;
+					};
+				};
+			};
+		};
+	};
+};
+
+&fmc {
+	status = "okay";
+
+	flash@0 {
+		label = "bmc";
+
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x0 0xe0000>;		/* 896 KiB */
+				label = "u-boot";
+			};
+
+			partition@100000 {
+				reg = <0x100000 0x900000>;	/* 9 MiB */
+				label = "kernel";
+			};
+
+			partition@a00000 {
+				/*
+				 * extends to end of 64 MiB - 4 KiB; last
+				 * 4 KiB reserved for EROT image
+				 */
+				reg = <0xa00000 0x35ff000>;
+				label = "rofs";
+			};
+		};
+	};
+};
+
+&gpio0 {
+	gpio-line-names =
+		/* A0-A7 */ "", "", "", "", "", "", "", "",
+		/* B0-B7 */ "", "", "", "", "", "", "", "",
+		/* C0-C7 */ "", "BF4_USB_RST_L-O", "", "", "", "", "", "",
+		/* D0-D7 */ "", "", "", "", "", "FPGA_PEX_RST_L", "", "",
+		/* E0-E7 */ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I",
+			    "", "", "", "", "", "MUX_SGPIO_SEL-O",
+		/* F0-F7 */ "", "", "", "", "", "", "", "",
+		/* G0-G7 */ "", "", "", "", "", "", "", "",
+		/* H0-H7 */ "", "", "", "", "", "", "", "",
+		/* I0-I7 */ "", "", "", "", "", "QSPI2_RST_L-O",
+			    "GLOBAL_WP_BMC-I", "BMC_DDR4_TEN-O",
+		/* J0-J7 */ "", "", "", "", "", "", "", "",
+		/* K0-K7 */ "", "", "", "", "", "", "", "",
+		/* L0-L7 */ "", "", "", "", "", "", "", "",
+		/* M0-M7 */ "USB_HUB_RST_N-O", "BMC_FRU_WP-O",
+			    "", "HMC_STBY_POWER_EN-O", "STBY_POWER_PG-I",
+			    "PCIE_EP_RST_L-O", "", "",
+		/* N0-N7 */ "", "", "", "", "", "", "", "",
+		/* O0-O7 */ "", "", "", "", "", "", "", "",
+		/* P0-P7 */ "", "", "", "", "", "", "", "",
+		/* Q0-Q7 */ "", "", "", "", "", "", "", "",
+		/* R0-R7 */ "", "SP0_AP_INTR_N-I", "", "", "", "", "", "",
+		/* S0-S7 */ "", "", "", "", "", "", "", "",
+		/* T0-T7 */ "", "", "", "", "", "", "", "",
+		/* U0-U7 */ "", "", "", "", "", "", "", "",
+		/* V0-V7 */ "", "", "", "", "",
+			    "PCB_TEMP_ALERT-I", "", "",
+		/* W0-W7 */ "", "", "", "", "", "", "", "CPU_RST_L-I",
+		/* X0-X7 */ "", "", "", "", "", "", "", "",
+		/* Y0-Y7 */ "", "", "", "EMMC_RST-O", "", "", "", "",
+		/* Z0-Z7 */ "HMC_EROT_SPI_INT_L-I",
+			    "", "", "", "", "", "", "";
+};
+
+&gpio1 {
+	gpio-line-names =
+		/* A0-A7 */ "", "", "", "", "", "", "", "",
+		/* B0-B7 */ "", "", "", "", "AP_EROT_REQ-O",
+			    "EROT_AP_GNT-I", "IO_EXPANDER_INT_L-I", "",
+		/* C0-C7 */ "", "", "", "", "", "", "", "",
+		/* D0-D7 */ "", "", "", "", "", "", "",
+			    "I2C_SSIF_ALERT_L-I",
+		/* E0-E7 */ "", "", "", "", "", "", "", "";
+};
+
+/* SSIF (CPU0 host IPMI) */
+&i2c0 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+/* BMC <-> HMC management (FRU proxy) */
+&i2c1 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	exp0: gpio@20 {
+		compatible = "nxp,pca9555";
+		reg = <0x20>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"B0_M0_SHDN_FORCE_L-O",
+			"B0_M0_STBY_POWER_PG-I",
+			"B0_M0_THERM_OVERT_L-I",
+			"B0_M0_THERM_WARN_L-I",
+			"B0_M0_GLOBAL_WP-O",
+			"B0_M0_USB_HUB0_RST_L-O",
+			"B0_M0_PRE_SYS_RST_L-O",
+			"B0_M0_LEAK_DETECT_ALERT_L-I",
+			"B0_M0_RUN_POWER_EN-O",
+			"B0_M0_RUN_POWER_PG-I",
+			"B0_M0_CPU_CHIPTHROT_L-O",
+			"B0_M0_SHDN_REQ_L-O",
+			"B0_M0_CPU_SHDN_OK_L-I",
+			"B0_M0_CPLD_READY-I",
+			"B0_M0_PWR_BRAKE_L-O",
+			"B0_M0_PWR_BRAKE_STATUS_L-I";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+		vcc-supply = <&standby_power_regulator>;
+	};
+
+	exp1: gpio@21 {
+		compatible = "nxp,pca9555";
+		reg = <0x21>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"B0_M0_I2C_BUS_MUX_RESET_L-O",
+			"B0_M0_HPM_MCU_OK-I",
+			"B0_M0_CPU_L0_RST_IND_L-O",
+			"B0_M0_C0_SOCAMM_DAC_SEL0-O",
+			"B0_M0_C1_SOCAMM_DAC_SEL1-O",
+			"B0_M0_C0_SOCAMM_I2C_SEL_R-O",
+			"B0_M0_C1_SOCAMM_I2C_SEL_R-O",
+			"B0_M0_EEPROM_POWER_DISABLE-O",
+			"B0_M0_L0L1_RST_L-I",
+			"B0_M0_L2_RST_L-I",
+			"B0_M0_BRD_ID_0-I",
+			"B0_M0_BRD_ID_1-I",
+			"B0_M0_BMC_LEAK_TEST_L-O",
+			"B0_M0_MCU_BMC_ALERT_L-I",
+			"B0_M0_CPU_BOOT_COMPLETE_3V3-I",
+			"B0_M0_BMC_TO_GPU_MCU_I2C_EN-O";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+		vcc-supply = <&standby_power_regulator>;
+	};
+};
+
+/* HMC virtual EEPROM / sensor proxy */
+&i2c3 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+/* MCIO expansion connector (HPM board 0) */
+&i2c4 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+&i2c5 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	exp4: gpio@20 {
+		compatible = "nxp,pca9555";
+		reg = <0x20>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"HMC_RST_R_L-O",
+			"HMC_RECOVERY_R-O",
+			"HMC_SPI_MUX_R_SEL-O",
+			"GLOBAL_WP-O",
+			"HMC_READY-I",
+			"HMC_PRSNT_R-I",
+			"BMC_SELF_PWR_CYCLE-O",
+			"EEDO_LED2-O",
+			"PWR_LED_L-O",
+			"PWR_BTN_L-I",
+			"UID_LED_L-O",
+			"UID_BTN_L-I",
+			"FAULT_LED_L-O",
+			"USB2_HUB_RST_L-O",
+			"IOX_GPIO_P16_TP",
+			"WARN_LED_L-O";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	exp5: gpio@21 {
+		compatible = "nxp,pca9555";
+		reg = <0x21>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"BMC_HMC_MUX_SEL-O",
+			"BMC_TPM_MUX_SEL-O",
+			"BMC_USB2_MUX_SEL-O",
+			"HMC_PGOOD_3V3-I",
+			"BF3_AOC_NCSI_PRSNT_L-I",
+			"HDR_SPI_PRSNT_L-I",
+			"SW_NRESET_R_L-O",
+			"MUX_I2C_ESPI_SEL-O",
+			"I2C_BUS_MUX_RESET_L-O",
+			"USB_MUX_EN-O",
+			"PDB_TRAY_RST-O",
+			"USB_PWR_EN-O",
+			"RTC_CLR_L-O",
+			"I2C_RTC_ALERT_L-I",
+			"X86_TPM_RST_SEL_L-O",
+			"BMC_MUX_PI3DP_SEL-O";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&i2c6 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	exp19: gpio@20 {
+		compatible = "ti,tca6408";
+		reg = <0x20>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"", "",
+			"HMC_EROT_FATAL_ERROR_L-I", "",
+			"", "HMC_EROT_RECOVERY_L-O",
+			"HMC_EROT_RESET_L-O", "";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9546";
+		reg = <0x70>;
+		#address-cells = <1>;
+		i2c-mux-idle-disconnect;
+		#size-cells = <0>;
+
+		/* USB hub sideband */
+		i2c_usbhub: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		/* optional TPM mux (unused; primary TPM is SPI) */
+		i2c_tpm: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		/* DisplayPort/USB-C crossbar */
+		i2c_dp: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c7 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	exp2: gpio@20 {
+		compatible = "nxp,pca9555";
+		reg = <0x20>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"B1_M0_SHDN_FORCE_L-O",
+			"B1_M0_STBY_POWER_PG-I",
+			"B1_M0_THERM_OVERT_L-I",
+			"B1_M0_THERM_WARN_L-I",
+			"B1_M0_GLOBAL_WP-O",
+			"B1_M0_USB_HUB0_RST_L-O",
+			"B1_M0_PRE_SYS_RST_L-O",
+			"B1_M0_LEAK_DETECT_ALERT_L-I",
+			"B1_M0_RUN_POWER_EN-O",
+			"B1_M0_RUN_POWER_PG-I",
+			"B1_M0_CPU_CHIPTHROT_L-O",
+			"B1_M0_SHDN_REQ_L-O",
+			"B1_M0_CPU_SHDN_OK_L-I",
+			"B1_M0_CPLD_READY-I",
+			"B1_M0_PWR_BRAKE_L-O",
+			"B1_M0_PWR_BRAKE_STATUS_L-I";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+		vcc-supply = <&standby_power_regulator>;
+	};
+
+	exp3: gpio@21 {
+		compatible = "nxp,pca9555";
+		reg = <0x21>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"B1_M0_I2C_BUS_MUX_RESET_L-O",
+			"B1_M0_HPM_MCU_OK-I",
+			"B1_M0_CPU_L0_RST_IND_L-O",
+			"B1_M0_C0_SOCAMM_DAC_SEL0-O",
+			"B1_M0_C1_SOCAMM_DAC_SEL1-O",
+			"B1_M0_C0_SOCAMM_I2C_SEL_R-O",
+			"B1_M0_C1_SOCAMM_I2C_SEL_R-O",
+			"B1_M0_EEPROM_POWER_DISABLE-O",
+			"B1_M0_L0L1_RST_L-I",
+			"B1_M0_L2_RST_L-I",
+			"B1_M0_BRD_ID_0-I",
+			"B1_M0_BRD_ID_1-I",
+			"B1_M0_BMC_LEAK_TEST_L-O",
+			"B1_M0_MCU_BMC_ALERT_L-I",
+			"B1_M0_CPU_BOOT_COMPLETE_3V3-I",
+			"B1_M0_BMC_TO_GPU_MCU_I2C_EN-O";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+		vcc-supply = <&standby_power_regulator>;
+	};
+};
+
+/* SSIF (CPU1 host IPMI) */
+&i2c8 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+&i2c9 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	exp6: gpio@20 {
+		compatible = "nxp,pca9555";
+		reg = <0x20>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"PDB_STRAP-I",
+			"STBY_POWER_EN-O",
+			"STBY_PWR_OK-I",
+			"", "",
+			"MAIN_PWR_EN-O",
+			"MAIN_PWR_OK-I",
+			"PDB_GLB_WP-O",
+			"PDB_PWR_BRK_L-I",
+			"FAN_PRSNT-I",
+			"", "",
+			"HSC4_S5_OR_S0_N-O",
+			"", "", "";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <8>;
+	};
+
+	exp7: gpio@75 {
+		compatible = "nxp,pca9539";
+		reg = <0x75>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"SNN_PDB_RUN_IO0_A_R_PG-I",
+			"RST_STBY_R_L-O",
+			"SNN_PDB_RUN_IO0_B_R_EN-O",
+			"PSU1_PRSNT_R_N-O",
+			"PSU2_PRSNT_R_N-O",
+			"PSU3_PRSNT_R_N-O",
+			"PSU4_PRSNT_R_N-O",
+			"PDB_12V_PG_R-I",
+			"PDB_12V_2_PG_R-I",
+			"PDB_12V_2_EN_R-O",
+			"PDB_12V_EN_N_R-O",
+			"",
+			"HSC_PG_VIN_PG_R-I",
+			"PDB_PSU_SMB_ALERT_L_R-O",
+			"SNN_JSB2_17_R-I",
+			"TRAY_RST_L_R-I";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&i2c10 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <8>;
+	};
+};
+
+/* Realtek Ethernet switch config EEPROM */
+&i2c11 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+/* BMC EROT */
+&i2c12 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+&i2c13 {
+	clock-frequency = <400000>;
+	mctp-controller;
+	multi-master;
+
+	status = "okay";
+
+	mctp-controller@18 {
+		compatible = "mctp-i2c-controller";
+		reg = <(0x18 | I2C_OWN_SLAVE_ADDRESS)>;
+	};
+
+	exp18: gpio@38 {
+		compatible = "nxp,pca9554";
+		reg = <0x38>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names =
+			"SSD0_PRSNT_L-I",
+			"E1S_PWR_EN-O",
+			"SSD0_PWRDIS-O",
+			"I2C_PDB_ALERT_L-I",
+			"BMC_SSD0_RST_L-O",
+			"GLOBAL_WP_E1S-O",
+			"12V_SSD0_PGD-I",
+			"SSD0_LED-O";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+/* MCIO expansion connector (HPM board 1) */
+&i2c14 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+/* USB-C PD controller */
+&i2c15 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+&mac0 {
+	phy-handle = <&ethphy0>;
+	/*
+	 * The on-board PHY uses both the RX and TX RGMII internal
+	 * delays. Declare "rgmii-id" so the MAC does not add
+	 * additional delay. The same setting is applied in the
+	 * matching u-boot DTS to keep early-boot networking working.
+	 */
+	phy-mode = "rgmii-id";
+	pinctrl-0 = <&pinctrl_rgmii1_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&mdio0 {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&spi2 {
+	pinctrl-0 = <&pinctrl_spi2_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash@0 {
+		label = "config";
+
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x0 0x40000>;	/* 256 KiB */
+				label = "u-boot-env";
+			};
+
+			partition@40000 {
+				reg = <0x40000 0x1000000>;	/* 16 MiB */
+				label = "rwfs";
+			};
+
+			partition@1040000 {
+				reg = <0x1040000 0x2800000>;	/* 40 MiB */
+				label = "log";
+			};
+		};
+	};
+};
+
+/* BMC <-> host CPU UART */
+&uart1 {
+	status = "okay";
+};
+
+/* Serial-over-LAN */
+&uart3 {
+	status = "okay";
+};
+
+/* BMC debug console */
+&uart5 {
+	status = "okay";
+};
+
+&uart_routing {
+	status = "okay";
+};
+
+&vhub {
+	status = "okay";
+};
+
+&video {
+	memory-region = <&video_engine_memory>;
+
+	status = "okay";
+};
-- 
2.43.0

Re: [PATCH v4 2/2] ARM: dts: aspeed: Add NVIDIA VR-NVL BMC

[Rob Herring]

On Tue, Jul 28, 2026 at 05:55:10PM +0900, Jacky Huang wrote:
> Add the device tree for the Aspeed AST2600 BMC for NVIDIA's Vera
> Rubin NVL compute platform.
> 
> MAC0 uses phy-mode = "rgmii-id" because the on-board PHY supplies
> both RGMII internal delays. The matching U-Boot device tree does not
> enable SoC-side MAC clock delays, leaving the MAC internal delay at
> zero so the PHY-provided delay is not doubled by the MAC controller.
> 
> The corresponding U-Boot change has been submitted to openbmc/u-boot:
> Link: https://lore.kernel.org/all/20260629105202.1417679-1-jackyhuang@nvidia.com/
> 
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> Signed-off-by: Jacky Huang <jackyhuang@nvidia.com>
> ---
> v4: address dt-check-style findings for property and child node ordering,
>     required blank lines, and line length. Retain 8 conventional multi-line
>     block comments with mixed-indent and 22 meaningful unused labels for
>     source readability and future references. They can be removed if
>     preferred.
> 
>  arch/arm/boot/dts/aspeed/Makefile             |   1 +
>  .../aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts   | 923 ++++++++++++++++++
>  2 files changed, 924 insertions(+)
>  create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts
> 
> diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
> index 6b68671f9379..07e10083a8bd 100644
> --- a/arch/arm/boot/dts/aspeed/Makefile
> +++ b/arch/arm/boot/dts/aspeed/Makefile
> @@ -65,6 +65,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
>  	aspeed-bmc-microsoft-olympus.dtb \
>  	aspeed-bmc-nvidia-gb200nvl-bmc.dtb \
>  	aspeed-bmc-nvidia-msx4-bmc.dtb \
> +	aspeed-bmc-nvidia-vr-nvl-bmc.dtb \
>  	aspeed-bmc-opp-lanyang.dtb \
>  	aspeed-bmc-opp-mowgli.dtb \
>  	aspeed-bmc-opp-nicole.dtb \
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts
> new file mode 100644
> index 000000000000..1c04fd3e627c
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-vr-nvl-bmc.dts
> @@ -0,0 +1,923 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2026 NVIDIA Corporation


> +&ehci1 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	status = "okay";
> +
> +	hub@1 {
> +		reg = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		hub@1 {
> +			reg = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			hub@4 {
> +				reg = <4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				/* port 1: BlueField-4 SMA mgmt */
> +				device@1 {
> +					reg = <1>;
> +					#address-cells = <2>;
> +					#size-cells = <0>;
> +
> +					interface@1 {
> +						reg = <1 1>;
> +					};
> +				};
> +
> +				cp2112g: device@2 {

This and other devices should have a compatible string and associated 
schema. The hub probably should too.

> +					reg = <2>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +					gpio-line-names =
> +						"BF4_USB_MCU_RECOVERY_L",
> +						"BF4_USB_MCU_RST_L",
> +						"BF4_USB_FORCE_FNP_L",
> +						"BF4_GLOBAL_WP",
> +						"BF4_FORCE_POR_L",
> +						"BF4_BMC_EROT_RST_L",
> +						"BF4_BMC_EROT_RECOVERY_L",
> +						"BF4_THERM_SHUTDOWN";
> +					#interrupt-cells = <2>;
> +					interrupt-controller;
> +				};
> +			};
> +		};
> +

> +&fmc {
> +	status = "okay";
> +
> +	flash@0 {

Needs a compatible.

> +		label = "bmc";
> +
> +		status = "okay";

okay is the default, so not needed.

> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				reg = <0x0 0xe0000>;		/* 896 KiB */
> +				label = "u-boot";
> +			};
> +
> +			partition@100000 {
> +				reg = <0x100000 0x900000>;	/* 9 MiB */
> +				label = "kernel";
> +			};
> +
> +			partition@a00000 {
> +				/*
> +				 * extends to end of 64 MiB - 4 KiB; last
> +				 * 4 KiB reserved for EROT image
> +				 */
> +				reg = <0xa00000 0x35ff000>;
> +				label = "rofs";
> +			};
> +		};
> +	};
> +};


> +&spi2 {
> +	pinctrl-0 = <&pinctrl_spi2_default>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +
> +	flash@0 {
> +		label = "config";

Needs a compatible.

> +
> +		status = "okay";

Drop

> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				reg = <0x0 0x40000>;	/* 256 KiB */
> +				label = "u-boot-env";
> +			};
> +
> +			partition@40000 {
> +				reg = <0x40000 0x1000000>;	/* 16 MiB */
> +				label = "rwfs";
> +			};
> +
> +			partition@1040000 {
> +				reg = <0x1040000 0x2800000>;	/* 40 MiB */
> +				label = "log";
> +			};
> +		};
> +	};
> +};

Re: [PATCH v4 2/2] ARM: dts: aspeed: Add NVIDIA VR-NVL BMC

[Jacky Huang]

Hi Rob,

Thank you very much for the review.

On Tue, Jul 28, 2026 at 09:39:52AM -0500, Rob Herring wrote:
> > +				cp2112g: device@2 {
>
> This and other devices should have a compatible string and associated
> schema. The hub probably should too.

Will fix in v5.

> > +	flash@0 {
>
> Needs a compatible.

The flash@0 node augments the corresponding node defined in
aspeed-g6.dtsi, which already carries compatible = "jedec,spi-nor",
so the compatible is inherited. The same applies to the flash@0
under &spi2.

> > +		status = "okay";
>
> okay is the default, so not needed.

The flash@0 node in aspeed-g6.dtsi is status = "disabled", so the
board file needs status = "okay" to enable it.

Jacky

Re: [PATCH v4 2/2] ARM: dts: aspeed: Add NVIDIA VR-NVL BMC

[Krzysztof Kozlowski]

On 29/07/2026 08:06, Jacky Huang wrote:
> Hi Rob,
> 
> Thank you very much for the review.
> 
> On Tue, Jul 28, 2026 at 09:39:52AM -0500, Rob Herring wrote:
>>> +				cp2112g: device@2 {
>>
>> This and other devices should have a compatible string and associated
>> schema. The hub probably should too.
> 
> Will fix in v5.
> 
>>> +	flash@0 {
>>
>> Needs a compatible.
> 
> The flash@0 node augments the corresponding node defined in
> aspeed-g6.dtsi, which already carries compatible = "jedec,spi-nor",
> so the compatible is inherited. The same applies to the flash@0
> under &spi2.
> 
>>> +		status = "okay";
>>
>> okay is the default, so not needed.
> 
> The flash@0 node in aspeed-g6.dtsi is status = "disabled", so the
> board file needs status = "okay" to enable it.
> 

Why are you extending existing nodes that way instead of phandle/label?
You write confusing code, so that's why you have such comments.

Best regards,
Krzysztof

Re: [PATCH v4 2/2] ARM: dts: aspeed: Add NVIDIA VR-NVL BMC

[Jacky Huang]

Hi Krzysztof,

On Wed, Jul 29, 2026 at 08:16:52AM +0200, Krzysztof Kozlowski wrote:
> Why are you extending existing nodes that way instead of phandle/label?
> You write confusing code, so that's why you have such comments.

Thank you for pointing this out. I agree that the current form is unclear.

For v5, I plan to add source labels to the existing flash nodes in
aspeed-g6.dtsi:

    fmc: spi@1e620000 {
            fmc_flash0: flash@0 {
                    ...
            };
    };

    spi2: spi@1e631000 {
            spi2_flash0: flash@0 {
                    ...
            };
    };

The board DTS will then reference them directly:

    &fmc_flash0 {
            ...
    };

    &spi2_flash0 {
            ...
    };

This should make the references to the existing nodes explicit.

Best,
Jacky

Re: [PATCH v4 2/2] ARM: dts: aspeed: Add NVIDIA VR-NVL BMC

[Rob Herring]

On Wed, Jul 29, 2026 at 1:06 AM Jacky Huang <jackyhuang@nvidia.com> wrote:
>
> Hi Rob,
>
> Thank you very much for the review.
>
> On Tue, Jul 28, 2026 at 09:39:52AM -0500, Rob Herring wrote:
> > > +                           cp2112g: device@2 {
> >
> > This and other devices should have a compatible string and associated
> > schema. The hub probably should too.
>
> Will fix in v5.
>
> > > +   flash@0 {
> >
> > Needs a compatible.
>
> The flash@0 node augments the corresponding node defined in
> aspeed-g6.dtsi, which already carries compatible = "jedec,spi-nor",
> so the compatible is inherited. The same applies to the flash@0
> under &spi2.

Is the flash part of the SoC package? A board level component
shouldn't be in the SoC .dtsi file. If there's some components that
all/most boards happen to use, then those should be a common board
.dtsi file.

Rob

Re: [PATCH v4 2/2] ARM: dts: aspeed: Add NVIDIA VR-NVL BMC

[Jacky Huang]

Hi Rob,

On Wed, Jul 29, 2026 at 08:17:40AM -0500, Rob Herring wrote:
> Is the flash part of the SoC package? A board level component
> shouldn't be in the SoC .dtsi file. If there's some components that
> all/most boards happen to use, then those should be a common board
> .dtsi file.

No, it is not part of the AST2600 SoC package. It is a discrete SPI NOR
on the BMC module.

I agree a common board .dtsi would be the better structure. The nodes
are already in aspeed-g6.dtsi today and more than 28 AST2600 board files
extend them. I can help prepare that cleanup if it is wanted.

Thanks,
Jacky

Re: [PATCH v4 2/2] ARM: dts: aspeed: Add NVIDIA VR-NVL BMC

[Jacky Huang]

Hi Rob,

> A board level component shouldn't be in the SoC .dtsi file.

I submitted a separate cleanup series to address this. The series
updates the AST2600 board files and vendor common DTSI files to
declare the flash devices they use, then removes the shared flash
nodes from aspeed-g6.dtsi:

https://lore.kernel.org/all/20260813102233.3088939-1-jackyhuang@nvidia.com/

I plan to base v5 of the VR-NVL DTS series on this cleanup.

Thanks,
Jacky