From: Ada Couprie Diaz <ada.coupriediaz@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Mark Rutland <mark.rutland@arm.com>,
Marc Zyngier <maz@kernel.org>, Barry Song <baohua@kernel.org>,
Vladimir Murzin <vladimir.murzin@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Lucas Wei <lucaswei@google.com>, Mark Brown <broonie@kernel.org>,
Andre Przywara <andre.przywara@arm.com>,
Tejun Heo <tj@kernel.org>, Oliver Upton <oupton@kernel.org>,
Will Deacon <will@kernel.org>,
Sascha Bischoff <Sascha.Bischoff@arm.com>
Subject: [PATCH 1/4] arm64: sysreg: generate TPIDR, SP and DAIF encodings
Date: Fri, 16 Oct 2026 17:46:45 +0100 [thread overview]
Message-ID: <20261016164648.251258-2-ada.coupriediaz@arm.com> (raw)
In-Reply-To: <20261016164648.251258-1-ada.coupriediaz@arm.com>
Introduce missing SYS_DAIF and SYS_SP_EL0 encodings in preparation
for a future commit.
While we are here, replace SYS_SP_EL{1,2} manual encodings with
automatically generated ones.
As the future commit will make use of SYS_TPIDR_EL{1,2} encodings,
replace their and related registers manual encodings with
automatically generated ones as well.
Clean up manual `SYS_CONTEXTIDR_EL2` definition, as it was already
generated.
Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
---
arch/arm64/include/asm/sysreg.h | 8 -------
arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7aa08d59d4944..7948b8c74cf49 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -418,10 +418,6 @@
#define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
#define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
-#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
-#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
-#define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
-
#define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
/* Definitions for system register interface to AMU for ARMv8.4 onwards */
@@ -520,7 +516,6 @@
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
-#define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
#define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
#define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
#define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
@@ -580,8 +575,6 @@
#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
-#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
-#define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
#define __AMEV_op2(m) (m & 0x7)
@@ -623,7 +616,6 @@
#define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
#define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
-#define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
/* AT instructions */
#define AT_Op0 1
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index e2d37ee221b84..7349744f14211 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2958,6 +2958,10 @@ Res0 4:1
Field 0 PCRSEL
EndSysreg
+Sysreg SP_EL0 3 0 4 1 0
+Field 63:0 SP
+EndSysreg
+
Sysreg ALLINT 3 0 4 3 0
Res0 63:14
Field 13 ALLINT
@@ -3811,6 +3815,15 @@ Sysreg GCSPR_EL0 3 3 2 5 1
Fields GCSPR_ELx
EndSysreg
+Sysreg DAIF 3 3 4 2 1
+Res0 63:10
+Field 9 D
+Field 8 A
+Field 7 I
+Field 6 F
+Res0 5:0
+EndSysreg
+
Sysreg SVCR 3 3 4 2 2
Res0 63:2
Field 1 ZA
@@ -3885,6 +3898,22 @@ UnsignedEnum 2:0 F8S1
EndEnum
EndSysreg
+Sysreg TPIDR_EL0 3 3 13 0 2
+Field 63:0 ThreadID
+EndSysreg
+
+Sysreg TPIDRRO_EL0 3 3 13 0 3
+Field 63:0 ThreadID
+EndSysreg
+
+Sysreg TPIDR2_EL0 3 3 13 0 5
+Field 63:0 ThreadID
+EndSysreg
+
+Sysreg SP_EL1 3 4 4 1 0
+Field 63:0 SP
+EndSysreg
+
Sysreg SCTLR_EL2 3 4 1 0 0
Field 63 TIDCP
Field 62 SPINTMASK
@@ -5425,6 +5454,10 @@ Sysreg CONTEXTIDR_EL2 3 4 13 0 1
Fields CONTEXTIDR_ELx
EndSysreg
+Sysreg TPIDR_EL2 3 4 13 0 2
+Field 63:0 ThreadID
+EndSysreg
+
Sysreg CNTPOFF_EL2 3 4 14 0 6
Field 63:0 PhysicalOffset
EndSysreg
@@ -5465,6 +5498,10 @@ Sysreg CONTEXTIDR_EL12 3 5 13 0 1
Mapping CONTEXTIDR_EL1
EndSysreg
+Sysreg SP_EL2 3 6 4 1 0
+Field 63:0 SP
+EndSysreg
+
SysregFields TTBRx_EL1
Field 63:48 ASID
Field 47:1 BADDR
--
2.43.0
next prev parent reply other threads:[~2026-10-16 16:47 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 16:46 [PATCH 0/4] arm64: insn: fix sysreg encodings, simplify dependent code Ada Couprie Diaz
2026-10-16 16:46 ` Ada Couprie Diaz [this message]
2026-10-20 9:16 ` [PATCH 1/4] arm64: sysreg: generate TPIDR, SP and DAIF encodings Vladimir Murzin
2026-10-16 16:46 ` [PATCH 2/4] arm64: insn: fix system register inconsistencies Ada Couprie Diaz
2026-10-20 9:47 ` Vladimir Murzin
2026-10-16 16:46 ` [PATCH 3/4] arm64: insn: operate on MSR/MRS sysreg field via defines Ada Couprie Diaz
2026-10-20 10:12 ` Vladimir Murzin
2026-10-16 16:46 ` [PATCH 4/4] arm64: insn: clean-up sysregs handling Ada Couprie Diaz
2026-10-20 10:45 ` Vladimir Murzin
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