From: Ada Couprie Diaz <ada.coupriediaz@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Mark Rutland <mark.rutland@arm.com>,
Marc Zyngier <maz@kernel.org>, Barry Song <baohua@kernel.org>,
Vladimir Murzin <vladimir.murzin@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Lucas Wei <lucaswei@google.com>, Mark Brown <broonie@kernel.org>,
Andre Przywara <andre.przywara@arm.com>,
Tejun Heo <tj@kernel.org>, Oliver Upton <oupton@kernel.org>,
Will Deacon <will@kernel.org>,
Sascha Bischoff <Sascha.Bischoff@arm.com>
Subject: [PATCH 3/4] arm64: insn: operate on MSR/MRS sysreg field via defines
Date: Fri, 16 Oct 2026 17:46:47 +0100 [thread overview]
Message-ID: <20261016164648.251258-4-ada.coupriediaz@arm.com> (raw)
In-Reply-To: <20261016164648.251258-1-ada.coupriediaz@arm.com>
Replace the few instances of hard-coded system register offset and masks
used to operate on MSR/MRS instructions with defines.
This will allow re-use in future commits while making the connection
between those values more explicit.
While we are here, mark `aarch64_insn_extract_system_reg()` `noinstr`
so it can be safe to use in alternative pacthing callbacks.
Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
---
arch/arm64/include/asm/insn.h | 3 +++
arch/arm64/lib/insn.c | 8 ++++----
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 2e45f6e80d15f..e020f9d8b83c2 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -113,6 +113,9 @@ enum aarch64_insn_register {
AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */
};
+#define AARCH64_INSN_SYSREG_OFFSET 5
+#define AARCH64_INSN_SYSREG_MASK GENMASK(20, AARCH64_INSN_SYSREG_OFFSET)
+
enum aarch64_insn_special_register {
AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200,
AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201,
diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
index 94ee1aae2f5b7..2edc5a9c0a9c8 100644
--- a/arch/arm64/lib/insn.c
+++ b/arch/arm64/lib/insn.c
@@ -1362,9 +1362,9 @@ u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
/*
* Extract the Op/CR data from a msr/mrs instruction.
*/
-u32 aarch64_insn_extract_system_reg(u32 insn)
+noinstr u32 aarch64_insn_extract_system_reg(u32 insn)
{
- return (insn & 0x1FFFE0) >> 5;
+ return (insn & AARCH64_INSN_SYSREG_MASK) >> AARCH64_INSN_SYSREG_OFFSET;
}
bool aarch32_insn_is_wide(u32 insn)
@@ -1566,8 +1566,8 @@ u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
{
u32 insn = aarch64_insn_get_mrs_value();
- insn &= ~GENMASK(20, 5);
- insn |= sysreg << 5;
+ insn &= ~AARCH64_INSN_SYSREG_MASK;
+ insn |= sysreg << AARCH64_INSN_SYSREG_OFFSET;
return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT,
insn, result);
}
--
2.43.0
next prev parent reply other threads:[~2026-10-16 16:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 16:46 [PATCH 0/4] arm64: insn: fix sysreg encodings, simplify dependent code Ada Couprie Diaz
2026-10-16 16:46 ` [PATCH 1/4] arm64: sysreg: generate TPIDR, SP and DAIF encodings Ada Couprie Diaz
2026-10-16 16:46 ` [PATCH 2/4] arm64: insn: fix system register inconsistencies Ada Couprie Diaz
2026-10-16 16:46 ` Ada Couprie Diaz [this message]
2026-10-16 16:46 ` [PATCH 4/4] arm64: insn: clean-up sysregs handling Ada Couprie Diaz
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