[PATCH 0/7] arm64: renesas: r8a78000: Enable GPIO support

[PATCH 0/7] arm64: renesas: r8a78000: Enable GPIO support

[Geert Uytterhoeven]

	Hi all,

This patch series enables GPIO support for the Renesas R-Car X5H SoC, as
found on the Renesas Ironhide development board.  On this board, clocks,
power-domains, and resets must be accessed only through SCMI firmware.

The series is a bit special, in that most patches are not meant to be
applied upstream yet:
  1. The first patch, targeting the GPIO tree, restores the abily to use
     the R-Car GPIO driver on a system that does not have pin control
     support yet (pin control is not yet supported by SCMI on Ironhide),
  2. The second patch, targeting a shared DT bindings branch, adds GPIO
     clock definitions,
  3. The third patch, targeting renesas-devel, adds GPIO device nodes to
     the R-Car X5H .dtsi file,
  4. The remaining patches are marked RFC or DNI; the latter depend on
     code or DTS that is not yet upstream.  More detail can be found in
     the individual patches.

This has been tested on Ironhide using GP05_15..GP05_20 (exposed on the
PWM connector), with and without SCMI.

Thanks for your comments!

Geert Uytterhoeven (6):
  gpio: rcar: Convert to gpiochip_generic_{request,free}()
  dt-bindings: clock: renesas,r8a78000-cpg: Add GPIO clocks
  [DNI] clk: renesas: r8a78000: Add GPIO clocks
  [RFC] pmdomain: renesas: r8a78000: Add default GPIO support
  [DNI] pmdomain: renesas: r8a78000: Add SCMI GPIO support
  [DNI] arm64: dts: renesas: r8a78000: Add gpio-ranges

Marek Vasut (1):
  arm64: dts: renesas: r8a78000: Add GPIO controller nodes

 arch/arm64/boot/dts/renesas/r8a78000.dtsi     | 166 ++++++++++++++++++
 drivers/clk/renesas/r8a78000-cpg.c            |  12 ++
 drivers/gpio/gpio-rcar.c                      |   5 +-
 drivers/pmdomain/renesas/r8a78000-mdlc.c      |  50 ++++++
 .../dt-bindings/clock/renesas,r8a78000-cpg.h  |  16 ++
 5 files changed, 246 insertions(+), 3 deletions(-)

-- 
2.43.0

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 1/7] gpio: rcar: Convert to gpiochip_generic_{request,free}()

[Geert Uytterhoeven]

When a gpio device node has no gpio-ranges property,
pinctrl_gpio_request() returns -EPROBE_DEFER and its GPIOs are unusable.

Restore the ability to use GPIOs before pin control support is added by
using the gpiolib helpers instead, which cater for this use case.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/gpio/gpio-rcar.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 54dc47d45de7e861..1192e1f1c6db8433 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -15,7 +15,6 @@
 #include <linux/irq.h>
 #include <linux/module.h>
 #include <linux/of.h>
-#include <linux/pinctrl/consumer.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/spinlock.h>
@@ -309,7 +308,7 @@ static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
 		return error;
 	}
 
-	error = pinctrl_gpio_request(chip, offset);
+	error = gpiochip_generic_request(chip, offset);
 	if (error)
 		pm_runtime_put(p->dev);
 
@@ -320,7 +319,7 @@ static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
 {
 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
 
-	pinctrl_gpio_free(chip, offset);
+	gpiochip_generic_free(chip, offset);
 
 	/*
 	 * Set the GPIO as an input to ensure that the next GPIO request won't
-- 
2.43.0

Re: [PATCH 1/7] gpio: rcar: Convert to gpiochip_generic_{request,free}()

[Linus Walleij]

On Fri, Oct 23, 2026 at 7:52 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:

> When a gpio device node has no gpio-ranges property,
> pinctrl_gpio_request() returns -EPROBE_DEFER and its GPIOs are unusable.
>
> Restore the ability to use GPIOs before pin control support is added by
> using the gpiolib helpers instead, which cater for this use case.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij

[PATCH 2/7] dt-bindings: clock: renesas,r8a78000-cpg: Add GPIO clocks

[Geert Uytterhoeven]

Add definitions for the clocks used by the GPIO modules on R-Car X5H:
  - R8A78000_CPG_SCPBUSD16_SCP_MAIN,
  - R8A78000_CPG_S0D24_PERE_MAIN,
  - R8A78000_CPG_SGD32_PERW_BUS,
  - R8A78000_CPG_S0D24_HSCN_OTHER.
Include a few more clocks from the same groups for ordering consistency.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 include/dt-bindings/clock/renesas,r8a78000-cpg.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
index 14b3885f2d9933a3..cd7192ccecd4e22c 100644
--- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
+++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
@@ -12,5 +12,21 @@
 #define R8A78000_CPG_SGASYNCD16_PERW_BUS	2
 #define R8A78000_CPG_MSO_SCP_MAIN		3
 #define R8A78000_CPG_MSOCK_PERW_BUS		4
+#define R8A78000_CPG_SCPBUSD1_SCP_MAIN		5
+#define R8A78000_CPG_SCPBUSD2_SCP_MAIN		6
+#define R8A78000_CPG_SCPBUSD4_SCP_MAIN		7
+#define R8A78000_CPG_SCPBUSD6_SCP_MAIN		8
+#define R8A78000_CPG_SCPBUSD8_SCP_MAIN		9
+#define R8A78000_CPG_SCPBUSD16_SCP_MAIN		10
+#define R8A78000_CPG_SCPBUSD32_SCP_MAIN		11
+#define R8A78000_CPG_S0D1_PERE_MAIN		12
+#define R8A78000_CPG_S0D2_PERE_MAIN		13
+#define R8A78000_CPG_S0D3_PERE_MAIN		14
+#define R8A78000_CPG_S0D4_PERE_MAIN		15
+#define R8A78000_CPG_S0D8_PERE_MAIN		16
+#define R8A78000_CPG_S0D24_PERE_MAIN		17
+#define R8A78000_CPG_SGD8_PERW_BUS		18
+#define R8A78000_CPG_SGD32_PERW_BUS		19
+#define R8A78000_CPG_S0D24_HSCN_OTHER		20
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */
-- 
2.43.0

Re: [PATCH 2/7] dt-bindings: clock: renesas,r8a78000-cpg: Add GPIO clocks

[Krzysztof Kozlowski]

On Fri, Oct 23, 2026 at 07:50:40PM +0200, Geert Uytterhoeven wrote:
> Add definitions for the clocks used by the GPIO modules on R-Car X5H:
>   - R8A78000_CPG_SCPBUSD16_SCP_MAIN,
>   - R8A78000_CPG_S0D24_PERE_MAIN,
>   - R8A78000_CPG_SGD32_PERW_BUS,
>   - R8A78000_CPG_S0D24_HSCN_OTHER.
> Include a few more clocks from the same groups for ordering consistency.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  include/dt-bindings/clock/renesas,r8a78000-cpg.h | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 3/7] arm64: dts: renesas: r8a78000: Add GPIO controller nodes

[Geert Uytterhoeven]

From: Marek Vasut <marek.vasut+renesas@mailbox.org>

Add device nodes for the General-Purpose Input/Output Ports (GPIO) on
the Renesas R-Car X5H (R8A78000) SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Co-developed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes compared to Marek's original:
  - Use hardware clocks/power-domains/resets instead of direct SCMI
    references,
  - Drop gpio-ranges properties for now, as upstream lacks Pin Function
    Controller (PFC) support.
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 155 ++++++++++++++++++++++
 1 file changed, 155 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 66eec0907b34fa58..36a4fa1e032ee703 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1263,6 +1263,161 @@ pfc: pinctrl@c1080000 {
 			bootph-all;
 		};
 
+		gpio0: gpio@c1080110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc1080110 0 0xc0>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SCPBUSD16_SCP_MAIN>;
+			power-domains = <&mdlc_aon R8A78000_MDLC_PD_AON 0x20>;
+			resets = <&mdlc_aon 0x20>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio1: gpio@c1080910 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc1080910 0 0xc0>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SCPBUSD16_SCP_MAIN>;
+			power-domains = <&mdlc_aon R8A78000_MDLC_PD_AON 0x20>;
+			resets = <&mdlc_aon 0x20>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio2: gpio@c1081110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc1081110 0 0xc0>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SCPBUSD16_SCP_MAIN>;
+			power-domains = <&mdlc_aon R8A78000_MDLC_PD_AON 0x20>;
+			resets = <&mdlc_aon 0x20>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio3: gpio@c0800110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0800110 0 0xc0>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_S0D24_PERE_MAIN>;
+			power-domains = <&mdlc_pere R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_pere 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio4: gpio@c0800910 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0800910 0 0xc0>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_S0D24_PERE_MAIN>;
+			power-domains = <&mdlc_pere R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_pere 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio5: gpio@c0400110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0400110 0 0xc0>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD32_PERW_BUS>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_perw 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio6: gpio@c0400910 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0400910 0 0xc0>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD32_PERW_BUS>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_perw 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio7: gpio@c0401110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0401110 0 0xc0>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD32_PERW_BUS>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_perw 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio8: gpio@c0401910 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc0401910 0 0xc0>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD32_PERW_BUS>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x30>;
+			resets = <&mdlc_perw 0x30>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-reserved-ranges = <16 10>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio9: gpio@c9b00110 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc9b00110 0 0xc0>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_S0D24_HSCN_OTHER>;
+			power-domains = <&mdlc_hscn R8A78000_MDLC_PD_APL 0x50>;
+			resets = <&mdlc_hscn 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		gpio10: gpio@c9b00910 {
+			compatible = "renesas,gpio-r8a78000",
+				     "renesas,rcar-gen5-gpio";
+			reg = <0 0xc9b00910 0 0xc0>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_S0D24_HSCN_OTHER>;
+			power-domains = <&mdlc_hscn R8A78000_MDLC_PD_APL 0x50>;
+			resets = <&mdlc_hscn 0x50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
 		cpg: clock-controller@c1320000 {
 			compatible = "renesas,r8a78000-cpg";
 			reg = <0 0xc1320000 0 0x10000>;
-- 
2.43.0

Re: [PATCH 3/7] arm64: dts: renesas: r8a78000: Add GPIO controller nodes

[Marek Vasut]

On 10/23/26 7:50 PM, Geert Uytterhoeven wrote:
> From: Marek Vasut <marek.vasut+renesas@mailbox.org>
> 
> Add device nodes for the General-Purpose Input/Output Ports (GPIO) on
> the Renesas R-Car X5H (R8A78000) SoC.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> Co-developed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Changes compared to Marek's original:
>    - Use hardware clocks/power-domains/resets instead of direct SCMI
>      references,
>    - Drop gpio-ranges properties for now, as upstream lacks Pin Function
>      Controller (PFC) support.

Is that ^ OK ? If so, good, TIL.

The rest is

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Thank you !

Re: [PATCH 3/7] arm64: dts: renesas: r8a78000: Add GPIO controller nodes

[Geert Uytterhoeven]

Hi Marek,

On Sat, 24 Oct 2026 at 07:35, Marek Vasut <marek.vasut@mailbox.org> wrote:
> On 10/23/26 7:50 PM, Geert Uytterhoeven wrote:
> > From: Marek Vasut <marek.vasut+renesas@mailbox.org>
> >
> > Add device nodes for the General-Purpose Input/Output Ports (GPIO) on
> > the Renesas R-Car X5H (R8A78000) SoC.
> >
> > Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> > Co-developed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > Changes compared to Marek's original:
> >    - Use hardware clocks/power-domains/resets instead of direct SCMI
> >      references,
> >    - Drop gpio-ranges properties for now, as upstream lacks Pin Function
> >      Controller (PFC) support.
>
> Is that ^ OK ? If so, good, TIL.

Yes, it works without PFC, as long as the pins are kept at their reset
state or configured for GPIO before Linux boots, which is the case
for the pins on the PWM connector.

> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Thanks!

BTW, looks like I used a wrong base for submitting, as the context does
include the pfc node, which is not present in upstream ;-)

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/7] arm64: dts: renesas: r8a78000: Add GPIO controller nodes

[Linus Walleij]

On Fri, Oct 23, 2026 at 7:53 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:

> From: Marek Vasut <marek.vasut+renesas@mailbox.org>
>
> Add device nodes for the General-Purpose Input/Output Ports (GPIO) on
> the Renesas R-Car X5H (R8A78000) SoC.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> Co-developed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

LGTM!
Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij

[PATCH/DNI 4/7] clk: renesas: r8a78000: Add GPIO clocks

[Geert Uytterhoeven]

Add support for the clocks used by the GPIO modules on R-Car X5H.
This includes SCMI remapping tables and fixed-clock fallbacks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on "[PATCH v4 2/8] clk: renesas: r8a78000: Add SCMI
remapping support"
https://lore.kernel.org/c38d744c09dffff550a9b882051c211b572b8daf.1792163045.git.geert+renesas@glider.be/
---
 drivers/clk/renesas/r8a78000-cpg.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c
index 758cfe78ae58e0fb..1d66082f6f44b5ba 100644
--- a/drivers/clk/renesas/r8a78000-cpg.c
+++ b/drivers/clk/renesas/r8a78000-cpg.c
@@ -35,12 +35,16 @@ struct cpg_data {
 };
 
 enum fixed_clk {
+	FIXED_CLK_33M,
+	FIXED_CLK_37M5,
 	FIXED_CLK_66M,
 	FIXED_CLK_133M,
 	FIXED_CLK_266M,
 };
 
 static const unsigned long fixed_clk_rates[] = {
+	[FIXED_CLK_33M] = 33333000,
+	[FIXED_CLK_37M5] = 37500000,
 	[FIXED_CLK_66M] = 66666000,
 	[FIXED_CLK_133M] = 133330000,
 	[FIXED_CLK_266M] = 266660000,
@@ -291,6 +295,10 @@ static const struct clk_map_in r8a78000_cpg_default[] = {
 	{ R8A78000_CPG_SGASYNCD4_PERW_BUS,	FIXED_CLK(266M) },
 	{ R8A78000_CPG_SGASYNCD8_PERW_BUS,	FIXED_CLK(133M) },
 	{ R8A78000_CPG_SGASYNCD16_PERW_BUS,	FIXED_CLK(66M) },
+	{ R8A78000_CPG_SCPBUSD16_SCP_MAIN,	FIXED_CLK(37M5) },
+	{ R8A78000_CPG_S0D24_PERE_MAIN,		FIXED_CLK(33M) },
+	{ R8A78000_CPG_SGD32_PERW_BUS,		FIXED_CLK(33M) },
+	{ R8A78000_CPG_S0D24_HSCN_OTHER,	FIXED_CLK(33M) },
 	{ -1 }
 };
 
@@ -300,6 +308,10 @@ static const struct clk_map_in r8a78000_cpg_fw[] = {
 	{ R8A78000_CPG_SGASYNCD16_PERW_BUS,	1663 },
 	{ R8A78000_CPG_MSO_SCP_MAIN,		1459 },
 	{ R8A78000_CPG_MSOCK_PERW_BUS,		1667 },
+	{ R8A78000_CPG_SCPBUSD16_SCP_MAIN,	1454 },
+	{ R8A78000_CPG_S0D24_PERE_MAIN,		1690 },
+	{ R8A78000_CPG_SGD32_PERW_BUS,		1660 },
+	{ R8A78000_CPG_S0D24_HSCN_OTHER,	1499 },
 	{ -1 }
 };
 
-- 
2.43.0

[PATCH/RFC 5/7] pmdomain: renesas: r8a78000: Add default GPIO support

[Geert Uytterhoeven]

All GPIO modules seem to be accessible without SCMI, and at least
GP05_15..GP05_20 are known to work.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Do we want this? So far there are no users of GPIO, and future users
might need SCMI for other reasons anyway.
---
 drivers/pmdomain/renesas/r8a78000-mdlc.c | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
index af36d8229030f6c0..10089d938f71b27e 100644
--- a/drivers/pmdomain/renesas/r8a78000-mdlc.c
+++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
@@ -606,13 +606,38 @@ static int r8a78000_mdlc_probe(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct mod_map_in r8a78000_mdlc_aon_mod_default[] = {
+	{ 0x20, 0, -1 },	/* GPIODM0 */
+	{ -1 }
+};
+
+static const struct mod_map_in r8a78000_mdlc_hscn_mod_default[] = {
+	{ 0x50, 0, -1 },	/* PFC_HSCN_GPIODM0 */
+	{ -1 }
+};
+
+static const struct mod_map_in r8a78000_mdlc_pere_mod_default[] = {
+	{ 0x30, 0, -1 },	/* PFC_PERE_GPIODM0 */
+	{ -1 }
+};
+
 static const struct mod_map_in r8a78000_mdlc_perw_mod_default[] = {
+	{ 0x30, 0, -1 },	/* PFC_PERW_GPIODM0 */
 	{ 0x54, 0, -1 },	/* HSCIF0 */
 	{ -1 }
 };
 
 static const struct mdlc_info r8a78000_mdlc_default[] = {
 	{
+		.base = 0xc1338000 /* mdlc_aon */,
+		.mod_map = r8a78000_mdlc_aon_mod_default,
+	}, {
+		.base = 0xc9c90000 /* mdlc_hscn */,
+		.mod_map = r8a78000_mdlc_hscn_mod_default,
+	}, {
+		.base = 0xc08f0000 /* mdlc_pere */,
+		.mod_map = r8a78000_mdlc_pere_mod_default,
+	}, {
 		.base = 0xc05d0000 /* mdlc_perw */,
 		.mod_map = r8a78000_mdlc_perw_mod_default,
 	},
-- 
2.43.0

[PATCH/DNI 6/7] pmdomain: renesas: r8a78000: Add SCMI GPIO support

[Geert Uytterhoeven]

Add support for the GPIO modules on R-Car X5H when using SCMI.
These are handled by the AON, HSCN, PERE, and PERW Module Controller
blocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on "[PATCH v4 7/8] pmdomain: renesas: r8a78000: Add SCMI
remapping support"
https://lore.kernel.org/2895c8f3cbe718dc597ad25e16c2461f0d681ab6.1792163045.git.geert+renesas@glider.be/
---
 drivers/pmdomain/renesas/r8a78000-mdlc.c | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
index 10089d938f71b27e..838566ed821e29e0 100644
--- a/drivers/pmdomain/renesas/r8a78000-mdlc.c
+++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
@@ -644,7 +644,23 @@ static const struct mdlc_info r8a78000_mdlc_default[] = {
 	{ /* sentinel */ }
 };
 
+static const struct mod_map_in r8a78000_mdlc_aon_mod_fw[] = {
+	{ 0x20, 811, -1 },	/* GPIODM0 */
+	{ -1 }
+};
+
+static const struct mod_map_in r8a78000_mdlc_hscn_mod_fw[] = {
+	{ 0x50, 332, -1 },	/* PFC_HSCN_GPIODM0 */
+	{ -1 }
+};
+
+static const struct mod_map_in r8a78000_mdlc_pere_mod_fw[] = {
+	{ 0x30, 193, -1 },	/* PFC_PERE_GPIODM0 */
+	{ -1 }
+};
+
 static const struct mod_map_in r8a78000_mdlc_perw_mod_fw[] = {
+	{ 0x30, 201, -1 },	/* PFC_PERW_GPIODM0 */
 	{ 0x40, 205, -1 },	/* SCIF0 */
 	{ 0x41, 206, -1 },	/* SCIF1 */
 	{ 0x42, 207, -1 },	/* SCIF3 */
@@ -678,6 +694,15 @@ static const struct mod_map_in r8a78000_mdlc_scp_mod_fw[] = {
 
 static const struct mdlc_info r8a78000_mdlc_fw[] = {
 	{
+		.base = 0xc1338000 /* mdlc_aon */,
+		.mod_map = r8a78000_mdlc_aon_mod_fw,
+	}, {
+		.base = 0xc9c90000 /* mdlc_hscn */,
+		.mod_map = r8a78000_mdlc_hscn_mod_fw,
+	}, {
+		.base = 0xc08f0000 /* mdlc_pere */,
+		.mod_map = r8a78000_mdlc_pere_mod_fw,
+	}, {
 		.base = 0xc05d0000 /* mdlc_perw */,
 		.mod_map = r8a78000_mdlc_perw_mod_fw,
 	}, {
-- 
2.43.0

[PATCH/DNI 7/7] arm64: dts: renesas: r8a78000: Add gpio-ranges

[Geert Uytterhoeven]

Link all GPIO controllers to the Pin Function Controller using
"gpio-ranges" properties.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on out-of-tree pin control support.
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 36a4fa1e032ee703..946dce6ab38b619d 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1273,6 +1273,7 @@ gpio0: gpio@c1080110 {
 			resets = <&mdlc_aon 0x20>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 0 28>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 		};
@@ -1287,6 +1288,7 @@ gpio1: gpio@c1080910 {
 			resets = <&mdlc_aon 0x20>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 32 22>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 		};
@@ -1301,6 +1303,7 @@ gpio2: gpio@c1081110 {
 			resets = <&mdlc_aon 0x20>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 64 29>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 		};
@@ -1315,6 +1318,7 @@ gpio3: gpio@c0800110 {
 			resets = <&mdlc_pere 0x30>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 96 17>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 		};
@@ -1329,6 +1333,7 @@ gpio4: gpio@c0800910 {
 			resets = <&mdlc_pere 0x30>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 128 16>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 		};
@@ -1343,6 +1348,7 @@ gpio5: gpio@c0400110 {
 			resets = <&mdlc_perw 0x30>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 160 23>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 		};
@@ -1357,6 +1363,7 @@ gpio6: gpio@c0400910 {
 			resets = <&mdlc_perw 0x30>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 192 31>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 		};
@@ -1371,6 +1378,7 @@ gpio7: gpio@c0401110 {
 			resets = <&mdlc_perw 0x30>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 224 31>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 		};
@@ -1385,6 +1393,7 @@ gpio8: gpio@c0401910 {
 			resets = <&mdlc_perw 0x30>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 256 32>;
 			gpio-reserved-ranges = <16 10>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
@@ -1400,6 +1409,7 @@ gpio9: gpio@c9b00110 {
 			resets = <&mdlc_hscn 0x50>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 288 17>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 		};
@@ -1414,6 +1424,7 @@ gpio10: gpio@c9b00910 {
 			resets = <&mdlc_hscn 0x50>;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pfc 0 320 14>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
 		};
-- 
2.43.0

Re: [PATCH/DNI 7/7] arm64: dts: renesas: r8a78000: Add gpio-ranges

[Linus Walleij]

On Fri, Oct 23, 2026 at 7:55 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:

> Link all GPIO controllers to the Pin Function Controller using
> "gpio-ranges" properties.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij