[PATCH v3 0/3] ARM: bcm: Enable CFE SMP on BCMBCA

[PATCH v3 0/3] ARM: bcm: Enable CFE SMP on BCMBCA

[Linus Walleij]

When booted through CFE and mainline U-Boot, the XG6846B has no PSCI
provider. CFE powers up CPU1 and leaves it waiting in a holding pen.

Add a BCMBCA CFE SMP method selected by enable-method = "brcm,bca-smp".
It uses a GPIO mailbox and a wakeup IPI, with PSCI retaining priority.
On the XG6846B, preserve the holding pen and disable the board's inherited
PSCI setup.
Tested on the XG6846B with both CPUs coming online.

These patches were authored with the assistance of an LLM.

Signed-off-by: Linus Walleij <linusw@kernel.org>
---
Changes in v3:
- Use BCMBCA naming for the CFE SMP implementation.
- Add the brcm,bca-smp binding and select CFE SMP through the CPU
  enable-method, retaining PSCI priority.
- Squash the holding-pen reservation fix into the CFE bring-up DTS patch.
- Boot tested successfully on the XG6846B.
- Link to v2: https://patch.msgid.link/20261017-genexis-xg6846-smp-v7-3-rc1-v2-0-bf6b4b374b6e@kernel.org

Changes in v2:
- Read the CFE mailbox address from CPU1's cpu-release-addr property,
  as suggested by William Zhang.
- Link to v1: https://patch.msgid.link/20261012-genexis-xg6846-smp-v7-3-rc1-v1-0-a51d4afde4a7@kernel.org

---
Linus Walleij (3):
      dt-bindings: arm: cpus: Add brcm,bca-smp enable method
      ARM: bcm: Add CFE SMP support for BCMBCA
      ARM: dts: broadcom: Use CFE CPU bring-up on the XG6846B

 Documentation/devicetree/bindings/arm/cpus.yaml    | 36 ++++++++++++++
 .../boot/dts/broadcom/bcm6846-genexis-xg6846b.dts  | 16 ++++++-
 arch/arm/mach-bcm/Makefile                         |  2 +-
 arch/arm/mach-bcm/board_bcmbca.c                   | 56 ++++++++++++++++++++++
 4 files changed, 108 insertions(+), 2 deletions(-)
---
base-commit: 6356fd3dd29d8b5620507a0ce037c644e052b5dd
change-id: 20261011-genexis-xg6846-smp-v7-3-rc1-b470f0e20475

Best regards,
--  
Linus Walleij <linusw@kernel.org>

[PATCH v3 1/3] dt-bindings: arm: cpus: Add brcm,bca-smp enable method

[Linus Walleij]

BCMBCA systems booted through CFE can release a secondary CPU by
writing its ARM-state entry address to a 32-bit MMIO mailbox and
sending a wakeup interrupt.

Document brcm,bca-smp and its single-cell cpu-release-addr property.
The boot CPU does not need a mailbox; secondary CPUs do. Add a
Cortex-A7 example showing both CPU nodes.

Suggested-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 Documentation/devicetree/bindings/arm/cpus.yaml | 36 +++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 5be89c584026..6771b85f757b 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -255,6 +255,7 @@ properties:
           - amlogic,meson8b-smp
           - arm,realview-smp
           - aspeed,ast2600-smp
+          - brcm,bca-smp
           - brcm,bcm11351-cpu-method
           - brcm,bcm23550
           - brcm,bcm2836-smp
@@ -471,6 +472,20 @@ allOf:
     then:
       required:
         - secondary-boot-reg
+  - if:
+      properties:
+        enable-method:
+          const: brcm,bca-smp
+      required:
+        - enable-method
+    then:
+      properties:
+        cpu-release-addr:
+          $ref: /schemas/types.yaml#/definitions/uint32
+          description:
+            Physical address of the 32-bit MMIO mailbox read by CFE after
+            a wakeup interrupt. Required on secondary CPUs. The kernel
+            writes the ARM-state entry address before sending the interrupt.
   - if:
       properties:
         enable-method:
@@ -712,4 +727,25 @@ examples:
         cpu-release-addr = <0 0x20000000>;
       };
     };
+  - |
+    // Example 5 (Broadcom BCMBCA with CFE):
+    cpus {
+      #size-cells = <0>;
+      #address-cells = <1>;
+
+      cpu@0 {
+        device_type = "cpu";
+        compatible = "arm,cortex-a7";
+        reg = <0>;
+        enable-method = "brcm,bca-smp";
+      };
+
+      cpu@1 {
+        device_type = "cpu";
+        compatible = "arm,cortex-a7";
+        reg = <1>;
+        enable-method = "brcm,bca-smp";
+        cpu-release-addr = <0xff800568>;
+      };
+    };
 ...

-- 
2.56.0

[PATCH v3 2/3] ARM: bcm: Add CFE SMP support for BCMBCA

[Linus Walleij]

The XG6846B CFE bootloader powers up CPU1 and leaves it in a holding pen
waiting for an interrupt. After waking, the stub reads the GPIO
GeneralPurpose register at 0xff800568 and branches to the stored address
in ARM state. The vendor kernel uses this mailbox and a wakeup IPI.

Implement the brcm,bca-smp CPU enable-method for BCMBCA systems
booted through CFE.
Read the mailbox address from the secondary CPU's cpu-release-addr
property. Map it as device memory, write secondary_startup_arm and
complete the write before sending the wakeup IPI. CPU1 is already
running, so no power or reset sequence is needed. Using the ARM entry
also supports kernels built in Thumb-2 mode. Clear any Thumb function
pointer tag before programming this ARM entry address.

Register the operations with CPU_METHOD_OF_DECLARE() so the CPU
nodes select CFE bring-up explicitly. Build the BCMBCA machine
description independently of DEBUG_BCMBCA, keeping the debug UART
mapping conditional. The generic ARM startup code retains PSCI priority.

Suggested-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 arch/arm/mach-bcm/Makefile       |  2 +-
 arch/arm/mach-bcm/board_bcmbca.c | 56 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 6baedf4c6304..fcc4e0174adc 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -58,6 +58,6 @@ endif
 
 # BCMBCA
 ifeq ($(CONFIG_ARCH_BCMBCA),y)
-obj-$(CONFIG_DEBUG_BCMBCA)	+= board_bcmbca.o
+obj-y				+= board_bcmbca.o
 obj-$(CONFIG_SMP)		+= bcm63xx_smp.o bcm63xx_pmb.o
 endif
diff --git a/arch/arm/mach-bcm/board_bcmbca.c b/arch/arm/mach-bcm/board_bcmbca.c
index b510d959870a..248b8bd77645 100644
--- a/arch/arm/mach-bcm/board_bcmbca.c
+++ b/arch/arm/mach-bcm/board_bcmbca.c
@@ -1,9 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0-only
 // Copyright (C) 2024 Linus Walleij <linus.walleij@linaro.org>
 
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/smp.h>
+
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/smp_plat.h>
 
+#ifdef CONFIG_DEBUG_BCMBCA
 /* This is needed for LL-debug/earlyprintk/debug-macro.S */
 static struct map_desc bcmbca_io_desc[] __initdata = {
 	{
@@ -13,12 +19,62 @@ static struct map_desc bcmbca_io_desc[] __initdata = {
 		.type = MT_DEVICE,
 	},
 };
+#endif
 
 static void __init bcmbca_map_io(void)
 {
+#ifdef CONFIG_DEBUG_BCMBCA
 	iotable_init(bcmbca_io_desc, ARRAY_SIZE(bcmbca_io_desc));
+#endif
 }
 
+#ifdef CONFIG_SMP
+static int bcmbca_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	struct device_node *np;
+	void __iomem *mailbox;
+	u32 release_addr;
+	int ret;
+
+	/* CFE has already powered up CPU1 and left it waiting in WFI. */
+	if (cpu_logical_map(cpu) != 1)
+		return -EINVAL;
+
+	np = of_get_cpu_node(cpu, NULL);
+	if (!np)
+		return -ENODEV;
+
+	ret = of_property_read_u32(np, "cpu-release-addr", &release_addr);
+	of_node_put(np);
+	if (ret) {
+		pr_err("CPU%u: missing or invalid cpu-release-addr property\n", cpu);
+		return ret;
+	}
+
+	mailbox = ioremap(release_addr, sizeof(u32));
+	if (!mailbox)
+		return -ENOMEM;
+
+	/*
+	 * The CFE stub reads GPIO GeneralPurpose after an interrupt and
+	 * branches to it in ARM state. Clear any Thumb function pointer
+	 * tag and complete the MMIO write before sending the wakeup IPI.
+	 */
+	writel(__pa_symbol(secondary_startup_arm) & ~1, mailbox);
+	dsb(sy);
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+	iounmap(mailbox);
+
+	return 0;
+}
+
+static const struct smp_operations bcmbca_smp_ops __initconst = {
+	.smp_boot_secondary = bcmbca_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(bcmbca_smp, "brcm,bca-smp", &bcmbca_smp_ops);
+#endif
+
 static const char * const bcmbca_dt_compat[] = {
 	/* TODO: Add other BCMBCA SoCs here to get debug UART support */
 	"brcm,bcm6846",

-- 
2.56.0

[PATCH v3 3/3] ARM: dts: broadcom: Use CFE CPU bring-up on the XG6846B

[Linus Walleij]

The XG6846B boots through CFE, which parks CPU1 in a holding pen and does
not provide PSCI. Starting Linux from CFE does not install a PSCI
implementation either. The working PSCI interface in newer GenXOS
firmware belongs to a different boot stack.

Disable the inherited PSCI node on this board so Linux does not issue
SMCs to an interface that is absent. Set the CPUs' enable-method to
brcm,bca-smp to select the BCMBCA CFE SMP operations. Describe the CFE
mailbox in CPU1's cpu-release-addr property. Keep both CPU nodes enabled
and leave the SoC's PSCI defaults available to other boards.

Also remove no-map from the secondary-boot reservation. Its overlap
with ARM's initial page tables otherwise causes the reservation to be
rejected, leaving CFE's holding pen unprotected.

Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts b/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts
index a3616fb7b3a8..45d4df523110 100644
--- a/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts
+++ b/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts
@@ -34,7 +34,7 @@ reserved-memory {
 		ranges;
 
 		secondary-boot@0 {
-			no-map;
+			/* Includes the kernel's initial page tables. */
 			reg = <0x00000000 0x00008000>;
 		};
 		pmc3-firmware@8000 {
@@ -56,6 +56,20 @@ button-restart {
 	};
 };
 
+/* CFE parks CPU1 in its holding pen and does not provide PSCI. */
+&{/psci} {
+	status = "disabled";
+};
+
+&CA7_0 {
+	enable-method = "brcm,bca-smp";
+};
+
+&CA7_1 {
+	enable-method = "brcm,bca-smp";
+	cpu-release-addr = <0xff800568>;
+};
+
 &gpio0 {
 	status = "okay";
 };

-- 
2.56.0

Re: [PATCH v3 1/3] dt-bindings: arm: cpus: Add brcm,bca-smp enable method

[Rob Herring]

On Wed, Oct 21, 2026 at 05:09:52PM +0200, Linus Walleij wrote:
> BCMBCA systems booted through CFE can release a secondary CPU by
> writing its ARM-state entry address to a 32-bit MMIO mailbox and
> sending a wakeup interrupt.
> 
> Document brcm,bca-smp and its single-cell cpu-release-addr property.
> The boot CPU does not need a mailbox; secondary CPUs do. Add a
> Cortex-A7 example showing both CPU nodes.
> 
> Suggested-by: William Zhang <william.zhang@broadcom.com>
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  Documentation/devicetree/bindings/arm/cpus.yaml | 36 +++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index 5be89c584026..6771b85f757b 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -255,6 +255,7 @@ properties:
>            - amlogic,meson8b-smp
>            - arm,realview-smp
>            - aspeed,ast2600-smp
> +          - brcm,bca-smp
>            - brcm,bcm11351-cpu-method
>            - brcm,bcm23550
>            - brcm,bcm2836-smp
> @@ -471,6 +472,20 @@ allOf:
>      then:
>        required:
>          - secondary-boot-reg
> +  - if:
> +      properties:
> +        enable-method:
> +          const: brcm,bca-smp
> +      required:
> +        - enable-method
> +    then:
> +      properties:
> +        cpu-release-addr:
> +          $ref: /schemas/types.yaml#/definitions/uint32
> +          description:
> +            Physical address of the 32-bit MMIO mailbox read by CFE after
> +            a wakeup interrupt. Required on secondary CPUs. The kernel
> +            writes the ARM-state entry address before sending the interrupt.

required:
  - cpu-release-addr

??? But cpu0 doesn't have an address. Is there really no address or you 
just omitted because you don't really need it. Should still be there in 
the latter case IMO.

Alternatively, add the enable-method value to the existing section that 
does this. Also, there might be other cases that are a 32-bit address 
and need this same constraint.

>    - if:
>        properties:
>          enable-method:
> @@ -712,4 +727,25 @@ examples:
>          cpu-release-addr = <0 0x20000000>;
>        };
>      };
> +  - |
> +    // Example 5 (Broadcom BCMBCA with CFE):
> +    cpus {
> +      #size-cells = <0>;
> +      #address-cells = <1>;
> +
> +      cpu@0 {
> +        device_type = "cpu";
> +        compatible = "arm,cortex-a7";
> +        reg = <0>;
> +        enable-method = "brcm,bca-smp";
> +      };
> +
> +      cpu@1 {
> +        device_type = "cpu";
> +        compatible = "arm,cortex-a7";
> +        reg = <1>;
> +        enable-method = "brcm,bca-smp";
> +        cpu-release-addr = <0xff800568>;
> +      };
> +    };
>  ...
> 
> -- 
> 2.56.0
> 

Re: [PATCH v3 2/3] ARM: bcm: Add CFE SMP support for BCMBCA

[William Zhang]

[-- Attachment #1: Type: text/plain, Size: 4734 bytes --]

On Wed, Oct 21, 2026 at 8:10 AM Linus Walleij <linusw@kernel.org> wrote:
>
> The XG6846B CFE bootloader powers up CPU1 and leaves it in a holding pen
> waiting for an interrupt. After waking, the stub reads the GPIO
> GeneralPurpose register at 0xff800568 and branches to the stored address
> in ARM state. The vendor kernel uses this mailbox and a wakeup IPI.
>
> Implement the brcm,bca-smp CPU enable-method for BCMBCA systems
> booted through CFE.
> Read the mailbox address from the secondary CPU's cpu-release-addr
> property. Map it as device memory, write secondary_startup_arm and
> complete the write before sending the wakeup IPI. CPU1 is already
> running, so no power or reset sequence is needed. Using the ARM entry
> also supports kernels built in Thumb-2 mode. Clear any Thumb function
> pointer tag before programming this ARM entry address.
>
> Register the operations with CPU_METHOD_OF_DECLARE() so the CPU
> nodes select CFE bring-up explicitly. Build the BCMBCA machine
> description independently of DEBUG_BCMBCA, keeping the debug UART
> mapping conditional. The generic ARM startup code retains PSCI priority.
>
> Suggested-by: William Zhang <william.zhang@broadcom.com>
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  arch/arm/mach-bcm/Makefile       |  2 +-
>  arch/arm/mach-bcm/board_bcmbca.c | 56 ++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 57 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> index 6baedf4c6304..fcc4e0174adc 100644
> --- a/arch/arm/mach-bcm/Makefile
> +++ b/arch/arm/mach-bcm/Makefile
> @@ -58,6 +58,6 @@ endif
>
>  # BCMBCA
>  ifeq ($(CONFIG_ARCH_BCMBCA),y)
> -obj-$(CONFIG_DEBUG_BCMBCA)     += board_bcmbca.o
> +obj-y                          += board_bcmbca.o
>  obj-$(CONFIG_SMP)              += bcm63xx_smp.o bcm63xx_pmb.o
>  endif
> diff --git a/arch/arm/mach-bcm/board_bcmbca.c b/arch/arm/mach-bcm/board_bcmbca.c
> index b510d959870a..248b8bd77645 100644
> --- a/arch/arm/mach-bcm/board_bcmbca.c
> +++ b/arch/arm/mach-bcm/board_bcmbca.c
> @@ -1,9 +1,15 @@
>  // SPDX-License-Identifier: GPL-2.0-only
>  // Copyright (C) 2024 Linus Walleij <linus.walleij@linaro.org>
>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/smp.h>
> +
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> +#include <asm/smp_plat.h>
>
> +#ifdef CONFIG_DEBUG_BCMBCA
>  /* This is needed for LL-debug/earlyprintk/debug-macro.S */
>  static struct map_desc bcmbca_io_desc[] __initdata = {
>         {
> @@ -13,12 +19,62 @@ static struct map_desc bcmbca_io_desc[] __initdata = {
>                 .type = MT_DEVICE,
>         },
>  };
> +#endif
>
>  static void __init bcmbca_map_io(void)
>  {
> +#ifdef CONFIG_DEBUG_BCMBCA
>         iotable_init(bcmbca_io_desc, ARRAY_SIZE(bcmbca_io_desc));
> +#endif
>  }
>
> +#ifdef CONFIG_SMP
> +static int bcmbca_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> +       struct device_node *np;
> +       void __iomem *mailbox;
> +       u32 release_addr;
> +       int ret;
> +
> +       /* CFE has already powered up CPU1 and left it waiting in WFI. */
> +       if (cpu_logical_map(cpu) != 1)
> +               return -EINVAL;
> +
> +       np = of_get_cpu_node(cpu, NULL);
> +       if (!np)
> +               return -ENODEV;
> +
> +       ret = of_property_read_u32(np, "cpu-release-addr", &release_addr);
> +       of_node_put(np);
> +       if (ret) {
> +               pr_err("CPU%u: missing or invalid cpu-release-addr property\n", cpu);
> +               return ret;
> +       }
> +
> +       mailbox = ioremap(release_addr, sizeof(u32));
> +       if (!mailbox)
> +               return -ENOMEM;
> +
> +       /*
> +        * The CFE stub reads GPIO GeneralPurpose after an interrupt and
> +        * branches to it in ARM state. Clear any Thumb function pointer
> +        * tag and complete the MMIO write before sending the wakeup IPI.
> +        */
> +       writel(__pa_symbol(secondary_startup_arm) & ~1, mailbox);
> +       dsb(sy);
> +       arch_send_wakeup_ipi_mask(cpumask_of(cpu));
> +       iounmap(mailbox);
> +
> +       return 0;
> +}
> +
> +static const struct smp_operations bcmbca_smp_ops __initconst = {
> +       .smp_boot_secondary = bcmbca_boot_secondary,
> +};
> +
> +CPU_METHOD_OF_DECLARE(bcmbca_smp, "brcm,bca-smp", &bcmbca_smp_ops);
> +#endif
> +
>  static const char * const bcmbca_dt_compat[] = {
>         /* TODO: Add other BCMBCA SoCs here to get debug UART support */
>         "brcm,bcm6846",
>
> --
> 2.56.0
>

Reviewed-by: William Zhang <william.zhang@broadcom.com>

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Re: [PATCH v3 3/3] ARM: dts: broadcom: Use CFE CPU bring-up on the XG6846B

[William Zhang]

[-- Attachment #1: Type: text/plain, Size: 2238 bytes --]

On Wed, Oct 21, 2026 at 8:10 AM Linus Walleij <linusw@kernel.org> wrote:
>
> The XG6846B boots through CFE, which parks CPU1 in a holding pen and does
> not provide PSCI. Starting Linux from CFE does not install a PSCI
> implementation either. The working PSCI interface in newer GenXOS
> firmware belongs to a different boot stack.
>
> Disable the inherited PSCI node on this board so Linux does not issue
> SMCs to an interface that is absent. Set the CPUs' enable-method to
> brcm,bca-smp to select the BCMBCA CFE SMP operations. Describe the CFE
> mailbox in CPU1's cpu-release-addr property. Keep both CPU nodes enabled
> and leave the SoC's PSCI defaults available to other boards.
>
> Also remove no-map from the secondary-boot reservation. Its overlap
> with ARM's initial page tables otherwise causes the reservation to be
> rejected, leaving CFE's holding pen unprotected.
>
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts b/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts
> index a3616fb7b3a8..45d4df523110 100644
> --- a/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts
> +++ b/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts
> @@ -34,7 +34,7 @@ reserved-memory {
>                 ranges;
>
>                 secondary-boot@0 {
> -                       no-map;
> +                       /* Includes the kernel's initial page tables. */
>                         reg = <0x00000000 0x00008000>;
>                 };
>                 pmc3-firmware@8000 {
> @@ -56,6 +56,20 @@ button-restart {
>         };
>  };
>
> +/* CFE parks CPU1 in its holding pen and does not provide PSCI. */
> +&{/psci} {
> +       status = "disabled";
> +};
> +
> +&CA7_0 {
> +       enable-method = "brcm,bca-smp";
> +};
> +
> +&CA7_1 {
> +       enable-method = "brcm,bca-smp";
> +       cpu-release-addr = <0xff800568>;
> +};
> +
>  &gpio0 {
>         status = "okay";
>  };
>
> --
> 2.56.0
>

Reviewed-by: William Zhang <william.zhang@broadcom.com>

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Re: [PATCH v3 1/3] dt-bindings: arm: cpus: Add brcm,bca-smp enable method

[William Zhang]

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On Thu, Oct 22, 2026 at 7:15 AM Rob Herring <robh@kernel.org> wrote:
>
> On Wed, Oct 21, 2026 at 05:09:52PM +0200, Linus Walleij wrote:
> > BCMBCA systems booted through CFE can release a secondary CPU by
> > writing its ARM-state entry address to a 32-bit MMIO mailbox and
> > sending a wakeup interrupt.
> >
> > Document brcm,bca-smp and its single-cell cpu-release-addr property.
> > The boot CPU does not need a mailbox; secondary CPUs do. Add a
> > Cortex-A7 example showing both CPU nodes.
> >
> > Suggested-by: William Zhang <william.zhang@broadcom.com>
> > Signed-off-by: Linus Walleij <linusw@kernel.org>
> > ---
> >  Documentation/devicetree/bindings/arm/cpus.yaml | 36 +++++++++++++++++++++++++
> >  1 file changed, 36 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> > index 5be89c584026..6771b85f757b 100644
> > --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> > @@ -255,6 +255,7 @@ properties:
> >            - amlogic,meson8b-smp
> >            - arm,realview-smp
> >            - aspeed,ast2600-smp
> > +          - brcm,bca-smp
> >            - brcm,bcm11351-cpu-method
> >            - brcm,bcm23550
> >            - brcm,bcm2836-smp
> > @@ -471,6 +472,20 @@ allOf:
> >      then:
> >        required:
> >          - secondary-boot-reg
> > +  - if:
> > +      properties:
> > +        enable-method:
> > +          const: brcm,bca-smp
> > +      required:
> > +        - enable-method
> > +    then:
> > +      properties:
> > +        cpu-release-addr:
> > +          $ref: /schemas/types.yaml#/definitions/uint32
> > +          description:
> > +            Physical address of the 32-bit MMIO mailbox read by CFE after
> > +            a wakeup interrupt. Required on secondary CPUs. The kernel
> > +            writes the ARM-state entry address before sending the interrupt.
>
> required:
>   - cpu-release-addr
>
> ??? But cpu0 doesn't have an address. Is there really no address or you
> just omitted because you don't really need it. Should still be there in
> the latter case IMO.
>
> Alternatively, add the enable-method value to the existing section that
> does this. Also, there might be other cases that are a 32-bit address
> and need this same constraint.
>
Cpu0 does not need release because it is the boot up CPU.  But there
is no harm to add it to be consistent.
All the BCA v7 chips only use 32 bit address for MMIO register.
Otheriwse,
Reviewed-by: William Zhang <william.zhang@broadcom.com>

> >    - if:
> >        properties:
> >          enable-method:
> > @@ -712,4 +727,25 @@ examples:
> >          cpu-release-addr = <0 0x20000000>;
> >        };
> >      };
> > +  - |
> > +    // Example 5 (Broadcom BCMBCA with CFE):
> > +    cpus {
> > +      #size-cells = <0>;
> > +      #address-cells = <1>;
> > +
> > +      cpu@0 {
> > +        device_type = "cpu";
> > +        compatible = "arm,cortex-a7";
> > +        reg = <0>;
> > +        enable-method = "brcm,bca-smp";
> > +      };
> > +
> > +      cpu@1 {
> > +        device_type = "cpu";
> > +        compatible = "arm,cortex-a7";
> > +        reg = <1>;
> > +        enable-method = "brcm,bca-smp";
> > +        cpu-release-addr = <0xff800568>;
> > +      };
> > +    };
> >  ...
> >
> > --
> > 2.56.0
> >

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Re: [PATCH v3 1/3] dt-bindings: arm: cpus: Add brcm,bca-smp enable method

[Rob Herring]

On Fri, Oct 23, 2026 at 09:20:06PM -0700, William Zhang wrote:
> On Thu, Oct 22, 2026 at 7:15 AM Rob Herring <robh@kernel.org> wrote:
> >
> > On Wed, Oct 21, 2026 at 05:09:52PM +0200, Linus Walleij wrote:
> > > BCMBCA systems booted through CFE can release a secondary CPU by
> > > writing its ARM-state entry address to a 32-bit MMIO mailbox and
> > > sending a wakeup interrupt.
> > >
> > > Document brcm,bca-smp and its single-cell cpu-release-addr property.
> > > The boot CPU does not need a mailbox; secondary CPUs do. Add a
> > > Cortex-A7 example showing both CPU nodes.
> > >
> > > Suggested-by: William Zhang <william.zhang@broadcom.com>
> > > Signed-off-by: Linus Walleij <linusw@kernel.org>
> > > ---
> > >  Documentation/devicetree/bindings/arm/cpus.yaml | 36 +++++++++++++++++++++++++
> > >  1 file changed, 36 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> > > index 5be89c584026..6771b85f757b 100644
> > > --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> > > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> > > @@ -255,6 +255,7 @@ properties:
> > >            - amlogic,meson8b-smp
> > >            - arm,realview-smp
> > >            - aspeed,ast2600-smp
> > > +          - brcm,bca-smp
> > >            - brcm,bcm11351-cpu-method
> > >            - brcm,bcm23550
> > >            - brcm,bcm2836-smp
> > > @@ -471,6 +472,20 @@ allOf:
> > >      then:
> > >        required:
> > >          - secondary-boot-reg
> > > +  - if:
> > > +      properties:
> > > +        enable-method:
> > > +          const: brcm,bca-smp
> > > +      required:
> > > +        - enable-method
> > > +    then:
> > > +      properties:
> > > +        cpu-release-addr:
> > > +          $ref: /schemas/types.yaml#/definitions/uint32
> > > +          description:
> > > +            Physical address of the 32-bit MMIO mailbox read by CFE after
> > > +            a wakeup interrupt. Required on secondary CPUs. The kernel
> > > +            writes the ARM-state entry address before sending the interrupt.
> >
> > required:
> >   - cpu-release-addr
> >
> > ??? But cpu0 doesn't have an address. Is there really no address or you
> > just omitted because you don't really need it. Should still be there in
> > the latter case IMO.
> >
> > Alternatively, add the enable-method value to the existing section that
> > does this. Also, there might be other cases that are a 32-bit address
> > and need this same constraint.
> >
> Cpu0 does not need release because it is the boot up CPU.

I get that. Is that convention or h/w restriction? I seem to recall the 
arm32 kernel might require cpu0 booting, but I think other arches do 
not. What if you support power gating or hot unplug of CPU0? Then you'd 
need the address.

>  But there
> is no harm to add it to be consistent.

If there is an release address for cpu0, then yes, you should have the 
property. If there is not and you just have to make up something to be 
consistent, then you should not have the property.

Rob