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From: Mario Behn <mario.behn@gmail.com>
To: Mark Brown <broonie@kernel.org>, Michal Simek <michal.simek@amd.com>
Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Mario Behn <mario.behn@gmail.com>
Subject: [PATCH v1 0/2] spi: zynq-qspi: use a flash larger than 16 MiB
Date: Thu,  5 Nov 2026 21:37:32 +0100	[thread overview]
Message-ID: <20261105203734.979168-1-mario.behn@gmail.com> (raw)

The Zynq-7000 QSPI controller sends at most 3 address bytes. spi-nor
needs 4-byte addresses for a flash larger than 16 MiB, so on a board
with a 32 MiB W25Q256 (the ADALM-PLUTO+ has one) the probe fails with
-EINVAL and no mtd device appears.

These two patches keep the flash in 3-byte mode and handle an operation
with a 4-byte address inside the controller driver, through the flash's
Extended Address Register (EAR): write enable, write EAR with
addr >> 24, the operation in its 3-byte form, then the EAR back to 0.
The EAR is 0 between operations, so a warm reset leaves the BootROM and
U-Boot in bank 0.

Patch 1 makes the flash readable (every other operation is refused).
Patch 2 adds program and erase, which need the write enable again after
the EAR write, a check of the bank register before the operation, and
waiting for the flash to be idle before the EAR is restored.

Tested on an ADALM-PLUTO+ (Zynq-7010, W25Q256, JEDEC id ef4019) with
v7.3 plus these patches:
 - the four partitions (mtd0 to mtd3, the last one 30 MiB and crossing
   the 16 MiB bank boundary) read back with the same md5 as on a vendor
   6.12 kernel that handles the 4-byte addresses in spi-nor;
 - the U-Boot environment in mtd1 is written with fw_setenv, survives a
   reboot and is read back;
 - one 64 KiB block in bank 1: erase, program a random pattern, read
   back (equal), restore;
 - 14 MiB (224 erase blocks) in bank 1: erase, program, read back
   (equal), restore; about 110 s each way;
 - a 26 MB firmware image written into the 30 MiB partition from the
   running system and verified byte for byte, after which the board
   boots from QSPI;
 - no driver error in the kernel log during any of it.

Not tested: other flash chips, boards with a flash on another chip
select, or the quad program path with a flash that is not a W25Q256.

Mario Behn (2):
  spi: zynq-qspi: read flash above 16 MiB via the extended address register
  spi: zynq-qspi: program and erase flash above 16 MiB via the EAR

 drivers/spi/spi-zynq-qspi.c | 1 file changed


             reply	other threads:[~2026-11-05 20:38 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-05 20:37 Mario Behn [this message]
2026-11-05 20:37 ` [PATCH v1 1/2] spi: zynq-qspi: read flash above 16 MiB via the extended address register Mario Behn
2026-11-05 20:37 ` [PATCH v1 2/2] spi: zynq-qspi: program and erase flash above 16 MiB via the EAR Mario Behn

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