* [PATCH v2 2/3] pci/designware: Add base driver for Designware PCIe
2015-04-15 9:48 [PATCH v2 0/3] pci/designware: Add architecture-independent driver for Designware PCIe Minghuan Lian
2015-04-15 9:48 ` [PATCH v2 1/3] arm/pci: Add support architecture-independent PCIe driver Minghuan Lian
@ 2015-04-15 9:48 ` Minghuan Lian
2015-04-15 10:36 ` Arnd Bergmann
2015-04-15 9:48 ` [PATCH v2 3/3] pci/layerscape: Add LS2085A PCIe support Minghuan Lian
2 siblings, 1 reply; 8+ messages in thread
From: Minghuan Lian @ 2015-04-15 9:48 UTC (permalink / raw)
To: linux-arm-kernel
The Synopsys Designware IP is shared with couples of platforms
under multiple architectures. The patch is to provide basic
architecture-independent Designware PCIe host driver including
ATU initialization and PCI OPS. Currently, which supports arm
and arm64 simultaneously.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v1-v2:
1. Get MSI chip according to dts property 'msi-parent'
2. Simplify platform_get_resource_byname() failure checking
drivers/pci/host/Kconfig | 3 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-designware-base.c | 293 ++++++++++++++++++++++++++++++++
drivers/pci/host/pcie-designware-base.h | 63 +++++++
4 files changed, 360 insertions(+)
create mode 100644 drivers/pci/host/pcie-designware-base.c
create mode 100644 drivers/pci/host/pcie-designware-base.h
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 1dfb567..2a697c0a 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -18,6 +18,9 @@ config PCI_MVEBU
config PCIE_DW
bool
+config PCIE_DW_BASE
+ bool
+
config PCI_EXYNOS
bool "Samsung Exynos PCIe controller"
depends on SOC_EXYNOS5440
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index f733b4e..da985e1 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_PCIE_DW_BASE) += pcie-designware-base.o
obj-$(CONFIG_PCIE_DW) += pcie-designware.o
obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
diff --git a/drivers/pci/host/pcie-designware-base.c b/drivers/pci/host/pcie-designware-base.c
new file mode 100644
index 0000000..10b4002
--- /dev/null
+++ b/drivers/pci/host/pcie-designware-base.c
@@ -0,0 +1,293 @@
+/*
+ * Synopsys Designware PCIe host controller base driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_regs.h>
+#include <linux/platform_device.h>
+
+#include "pcie-designware-base.h"
+
+void dw_pcie_dbi_write(struct dw_pcie_port *pp, u32 value, u32 offset)
+{
+ iowrite32(value, pp->dbi + offset);
+}
+
+u32 dw_pcie_dbi_read(struct dw_pcie_port *pp, u32 offset)
+{
+ return ioread32(pp->dbi + offset);
+}
+
+int dw_pcie_host_link_up(struct dw_pcie_port *pp)
+{
+ if (pp->dw_ops->link_up)
+ return pp->dw_ops->link_up(pp);
+ else
+ return 0;
+}
+
+void dw_pcie_atu_outbound_set(struct dw_pcie_port *pp, int idx, int type,
+ u64 cpu_addr, u64 pci_addr, u32 size)
+{
+ if (idx >= pp->atu_num)
+ return;
+
+ dw_pcie_dbi_write(pp, PCIE_ATU_REGION_OUTBOUND | idx,
+ PCIE_ATU_VIEWPORT);
+ dw_pcie_dbi_write(pp, lower_32_bits(cpu_addr),
+ PCIE_ATU_LOWER_BASE);
+ dw_pcie_dbi_write(pp, upper_32_bits(cpu_addr),
+ PCIE_ATU_UPPER_BASE);
+ dw_pcie_dbi_write(pp, lower_32_bits(cpu_addr + size - 1),
+ PCIE_ATU_LIMIT);
+ dw_pcie_dbi_write(pp, lower_32_bits(pci_addr),
+ PCIE_ATU_LOWER_TARGET);
+ dw_pcie_dbi_write(pp, upper_32_bits(pci_addr),
+ PCIE_ATU_UPPER_TARGET);
+ dw_pcie_dbi_write(pp, type, PCIE_ATU_CR1);
+ dw_pcie_dbi_write(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+}
+
+static void __iomem *
+dw_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int offset)
+{
+ struct dw_pcie_port *pp = bus->sysdata;
+ u32 type, busdev;
+
+ /* If there is no link, then there is no device */
+ if (!pci_is_root_bus(bus) && !dw_pcie_host_link_up(pp))
+ return NULL;
+
+ /* access only one slot on each root port */
+ if (pci_is_root_bus(bus) && devfn > 0)
+ return NULL;
+
+ if (pci_is_root_bus(bus))
+ return pp->dbi + offset;
+
+ busdev = PCIE_ATU_BUS(bus->number) |
+ PCIE_ATU_DEV(PCI_SLOT(devfn)) |
+ PCIE_ATU_FUNC(PCI_FUNC(devfn));
+
+ if (pci_is_root_bus(bus->parent))
+ type = PCIE_ATU_TYPE_CFG0;
+ else
+ type = PCIE_ATU_TYPE_CFG1;
+
+ dw_pcie_atu_outbound_set(pp,
+ PCIE_ATU_REGION_INDEX0,
+ type,
+ pp->cfg_addr,
+ busdev,
+ pp->cfg_size);
+
+ return pp->cfg + offset;
+}
+
+static int dw_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct dw_pcie_port *pp = bus->sysdata;
+ int ret;
+
+ ret = pci_generic_config_read32(bus, devfn, where, size, val);
+
+ if (pp->atu_num == 2 && !pci_is_root_bus(bus))
+ /* reassign ATU0 to map IO space */
+ dw_pcie_atu_outbound_set(pp,
+ PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_IO,
+ pp->io_cpu_addr,
+ pp->io_pci_addr,
+ pp->io_size);
+
+ return ret;
+}
+
+static int dw_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct dw_pcie_port *pp = bus->sysdata;
+ int ret;
+
+ ret = pci_generic_config_write32(bus, devfn, where, size, val);
+
+ if (pp->atu_num == 2 && !pci_is_root_bus(bus))
+ /* reassign ATU0 to map IO space */
+ dw_pcie_atu_outbound_set(pp,
+ PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_IO,
+ pp->io_cpu_addr,
+ pp->io_pci_addr,
+ pp->io_size);
+
+ return ret;
+}
+
+static struct pci_ops dw_pcie_ops = {
+ .map_bus = dw_pcie_map_bus,
+ .read = dw_pcie_config_read,
+ .write = dw_pcie_config_write,
+};
+
+static int dw_pcie_map_reg(struct dw_pcie_port *pp)
+{
+ struct platform_device *pdev = to_platform_device(pp->dev);
+ struct resource *res;
+
+ if (!pp->dbi) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "dbi");
+ pp->dbi = devm_ioremap_resource(pp->dev, res);
+ if (IS_ERR(pp->dbi)) {
+ dev_err(pp->dev, "missing *dbi* reg space\n");
+ return PTR_ERR(pp->dbi);
+ }
+ }
+
+ if (!pp->cfg) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "config");
+ pp->cfg = devm_ioremap_resource(pp->dev, res);
+ if (IS_ERR(pp->cfg)) {
+ dev_err(pp->dev, "missing *config* reg space\n");
+ return PTR_ERR(pp->cfg);
+ }
+
+ pp->cfg_addr = res->start;
+ pp->cfg_size = resource_size(res);
+ }
+
+ return 0;
+}
+
+/*
+ * If ATU number = 2, ATU0 is shared by transaction CFG and IO,
+ * ATU1 is used for transaction MEM
+ * If ATU number > 2, ATU0 is used for transaction CFG
+ * the other ATUs are used for MEM and IO separately.
+ */
+static int dw_pcie_atu_init(struct dw_pcie_port *pp,
+ struct list_head *res,
+ resource_size_t io_base)
+{
+ struct resource_entry *window;
+ struct device *dev = pp->dev;
+ int idx = 1, ret;
+
+ if (pp->atu_num < 2)
+ pp->atu_num = 2;
+
+ resource_list_for_each_entry(window, res) {
+ struct resource *res = window->res;
+ unsigned long restype = resource_type(res);
+
+ switch (restype) {
+ case IORESOURCE_IO:
+ if (pp->atu_num == 2)
+ idx = 0;
+
+ pp->io_cpu_addr = io_base;
+ pp->io_pci_addr = res->start - window->offset;
+ pp->io_size = resource_size(res);
+ dw_pcie_atu_outbound_set(pp,
+ idx,
+ PCIE_ATU_TYPE_IO,
+ pp->io_cpu_addr,
+ pp->io_pci_addr,
+ pp->io_size);
+ ret = pci_remap_iospace(res, io_base);
+ if (ret < 0)
+ return ret;
+ idx++;
+ break;
+ case IORESOURCE_MEM:
+ if (pp->atu_num == 2)
+ idx = 1;
+
+ dw_pcie_atu_outbound_set(pp,
+ idx,
+ PCIE_ATU_TYPE_MEM,
+ res->start,
+ res->start - window->offset,
+ resource_size(res));
+ idx++;
+ break;
+ case IORESOURCE_BUS:
+ break;
+ default:
+ dev_err(dev, "invalid resource %pR\n", res);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static void dw_pcie_msi_init(struct dw_pcie_port *pp)
+{
+ struct device_node *msi_node;
+
+ if (pp->msi_chip)
+ return;
+
+ msi_node = of_parse_phandle(pp->dev->of_node, "msi-parent", 0);
+ if (msi_node)
+ pp->msi_chip = of_pci_find_msi_chip_by_node(msi_node);
+}
+
+int dw_pcie_port_init(struct dw_pcie_port *pp)
+{
+ struct device_node *dn = pp->dev->of_node;
+ resource_size_t iobase = 0;
+ struct pci_bus *bus;
+ int ret;
+ LIST_HEAD(res);
+
+ ret = dw_pcie_map_reg(pp);
+ if (ret)
+ return ret;
+
+ ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
+ if (ret)
+ return ret;
+
+ ret = dw_pcie_atu_init(pp, &res, iobase);
+ if (ret)
+ return ret;
+
+ dw_pcie_msi_init(pp);
+
+ if (!pp->pci_ops)
+ pp->pci_ops = &dw_pcie_ops;
+
+ if (pp->dw_ops->host_init) {
+ if (pp->dw_ops->host_init(pp))
+ return ret;
+ }
+
+ bus = pci_create_root_bus(pp->dev, 0, pp->pci_ops,
+ pp, &res);
+ if (!bus)
+ return -ENOMEM;
+
+ bus->msi = pp->msi_chip;
+
+ pci_scan_child_bus(bus);
+ pci_assign_unassigned_bus_resources(bus);
+ pci_bus_add_devices(bus);
+
+ return 0;
+}
+
+MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
+MODULE_DESCRIPTION("Designware PCIe controller driver with Multiarch support");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/host/pcie-designware-base.h b/drivers/pci/host/pcie-designware-base.h
new file mode 100644
index 0000000..60c82de
--- /dev/null
+++ b/drivers/pci/host/pcie-designware-base.h
@@ -0,0 +1,63 @@
+/*
+ * Synopsys Designware PCIe host controller base driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _PCIE_DESIGNWARE_BASE_H
+#define _PCIE_DESIGNWARE_BASE_H
+
+/* Synopsis specific PCIE configuration registers */
+#define PCIE_ATU_VIEWPORT 0x900
+#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
+#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
+#define PCIE_ATU_CR1 0x904
+#define PCIE_ATU_TYPE_MEM (0x0 << 0)
+#define PCIE_ATU_TYPE_IO (0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_CR2 0x908
+#define PCIE_ATU_ENABLE (0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_LOWER_BASE 0x90C
+#define PCIE_ATU_UPPER_BASE 0x910
+#define PCIE_ATU_LIMIT 0x914
+#define PCIE_ATU_LOWER_TARGET 0x918
+#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET 0x91C
+
+struct dw_pcie_port;
+
+struct dw_host_ops {
+ int (*link_up)(struct dw_pcie_port *pp);
+ int (*host_init)(struct dw_pcie_port *pp);
+};
+
+struct dw_pcie_port {
+ struct device *dev;
+ void __iomem *dbi;
+ void __iomem *cfg;
+ u64 cfg_addr;
+ u32 cfg_size;
+ u64 io_cpu_addr;
+ u64 io_pci_addr;
+ u32 io_size;
+ u32 atu_num;
+ struct dw_host_ops *dw_ops;
+ struct pci_ops *pci_ops;
+ struct msi_controller *msi_chip;
+};
+
+void dw_pcie_dbi_write(struct dw_pcie_port *pp, u32 value, u32 offset);
+u32 dw_pcie_dbi_read(struct dw_pcie_port *pp, u32 offset);
+int dw_pcie_host_link_up(struct dw_pcie_port *pp);
+void dw_pcie_atu_outbound_set(struct dw_pcie_port *pp, int idx, int type,
+ u64 cpu_addr, u64 pci_addr, u32 size);
+int dw_pcie_port_init(struct dw_pcie_port *pp);
+
+#endif /* _PCIE_DESIGNWARE_BASE_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 3/3] pci/layerscape: Add LS2085A PCIe support
2015-04-15 9:48 [PATCH v2 0/3] pci/designware: Add architecture-independent driver for Designware PCIe Minghuan Lian
2015-04-15 9:48 ` [PATCH v2 1/3] arm/pci: Add support architecture-independent PCIe driver Minghuan Lian
2015-04-15 9:48 ` [PATCH v2 2/3] pci/designware: Add base driver for Designware PCIe Minghuan Lian
@ 2015-04-15 9:48 ` Minghuan Lian
2 siblings, 0 replies; 8+ messages in thread
From: Minghuan Lian @ 2015-04-15 9:48 UTC (permalink / raw)
To: linux-arm-kernel
LS2085a is based on arm64 architecture, however, currently,
layerscape PCIe driver based on pci-desginware.c is not
compatible with arm64 architecture. The patch changes code
to reuse PCIe Designware Base driver and provides LS2085a
PCIe support.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
change log:
v1-v2:
1. remove unnecessary code pcie->lut = pp->dbi + PCIE_LUT_BASE
drivers/pci/host/Kconfig | 4 +-
drivers/pci/host/pci-layerscape.c | 184 +++++++++++++++++++-------------
drivers/pci/host/pcie-designware-base.h | 3 +
3 files changed, 112 insertions(+), 79 deletions(-)
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 2a697c0a..e59783a 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -99,8 +99,8 @@ config PCI_XGENE
config PCI_LAYERSCAPE
bool "Freescale Layerscape PCIe controller"
- depends on OF && ARM
- select PCIE_DW
+ depends on OF && (ARM || ARM64)
+ select PCIE_DW_BASE
select MFD_SYSCON
help
Say Y here if you want PCIe controller support on Layerscape SoCs.
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
index 4a6e62f..15c5e47 100644
--- a/drivers/pci/host/pci-layerscape.c
+++ b/drivers/pci/host/pci-layerscape.c
@@ -1,7 +1,7 @@
/*
* PCIe host controller driver for Freescale Layerscape SoCs
*
- * Copyright (C) 2014 Freescale Semiconductor.
+ * Copyright (C) 2014 - 2015 Freescale Semiconductor.
*
* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
*
@@ -11,20 +11,16 @@
*/
#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
-#include <linux/resource.h>
-#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
+#include <linux/resource.h>
-#include "pcie-designware.h"
+#include "pcie-designware-base.h"
/* PEX1/2 Misc Ports Status Register */
#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
@@ -32,26 +28,29 @@
#define LTSSM_STATE_MASK 0x3f
#define LTSSM_PCIE_L0 0x11 /* L0 state */
-/* Symbol Timer Register and Filter Mask Register 1 */
-#define PCIE_STRFMR1 0x71c
+/* PEX LUT registers */
+#define PCIE_LUT_BASE 0x80000
+#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug register */
+
+#define PCIE_ATU_NUM 6
struct ls_pcie {
- struct list_head node;
- struct device *dev;
- struct pci_bus *bus;
- void __iomem *dbi;
- struct regmap *scfg;
- struct pcie_port pp;
- int index;
- int msi_irq;
+ struct dw_pcie_port pp;
+ void __iomem *regs;
+ void __iomem *lut;
+ struct regmap *scfg;
+ int index;
};
#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
-static int ls_pcie_link_up(struct pcie_port *pp)
+static int ls1_pcie_link_up(struct dw_pcie_port *pp)
{
- u32 state;
struct ls_pcie *pcie = to_ls_pcie(pp);
+ u32 state;
+
+ if (!pcie->scfg)
+ return 0;
regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
@@ -62,91 +61,128 @@ static int ls_pcie_link_up(struct pcie_port *pp)
return 1;
}
-static void ls_pcie_host_init(struct pcie_port *pp)
+static int ls1_pcie_host_init(struct dw_pcie_port *pp)
{
struct ls_pcie *pcie = to_ls_pcie(pp);
- int count = 0;
- u32 val;
-
- dw_pcie_setup_rc(pp);
+ u32 val, index[2];
+ int ret;
- while (!ls_pcie_link_up(pp)) {
- usleep_range(100, 1000);
- count++;
- if (count >= 200) {
- dev_err(pp->dev, "phy link never came up\n");
- return;
- }
+ pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
+ "fsl,pcie-scfg");
+ if (IS_ERR(pcie->scfg)) {
+ dev_err(pp->dev, "No syscfg phandle specified\n");
+ return PTR_ERR(pcie->scfg);
}
+ ret = of_property_read_u32_array(pp->dev->of_node,
+ "fsl,pcie-scfg", index, 2);
+ if (ret)
+ return ret;
+
+ pcie->index = index[1];
+
/*
* LS1021A Workaround for internal TKT228622
* to fix the INTx hang issue
*/
- val = ioread32(pcie->dbi + PCIE_STRFMR1);
+ val = dw_pcie_dbi_read(pp, PCIE_SYMBOL_TIMER_1);
val &= 0xffff;
- iowrite32(val, pcie->dbi + PCIE_STRFMR1);
+ dw_pcie_dbi_write(pp, val, PCIE_SYMBOL_TIMER_1);
+
+ /* Fix class value */
+ val = dw_pcie_dbi_read(pp, PCI_CLASS_REVISION);
+ val = (val & 0x0000ffff) | (PCI_CLASS_BRIDGE_PCI << 16);
+ dw_pcie_dbi_write(pp, val, PCI_CLASS_REVISION);
+
+ if (!ls1_pcie_link_up(pp))
+ dev_err(pp->dev, "phy link never came up\n");
+
+ return 0;
}
-static struct pcie_host_ops ls_pcie_host_ops = {
- .link_up = ls_pcie_link_up,
- .host_init = ls_pcie_host_init,
+static struct dw_host_ops ls1_dw_host_ops = {
+ .link_up = ls1_pcie_link_up,
+ .host_init = ls1_pcie_host_init,
};
-static int ls_add_pcie_port(struct ls_pcie *pcie)
+static int ls2_pcie_link_up(struct dw_pcie_port *pp)
{
- struct pcie_port *pp;
- int ret;
+ struct ls_pcie *pcie = to_ls_pcie(pp);
+ u32 state;
- pp = &pcie->pp;
- pp->dev = pcie->dev;
- pp->dbi_base = pcie->dbi;
- pp->root_bus_nr = -1;
- pp->ops = &ls_pcie_host_ops;
+ if (!pcie->lut)
+ return 0;
- ret = dw_pcie_host_init(pp);
- if (ret) {
- dev_err(pp->dev, "failed to initialize host\n");
- return ret;
- }
+ state = ioread32(pcie->lut + PCIE_LUT_DBG) & LTSSM_STATE_MASK;
+ if (state < LTSSM_PCIE_L0)
+ return 0;
+
+ return 1;
+}
+
+static int ls2_pcie_host_init(struct dw_pcie_port *pp)
+{
+ struct ls_pcie *pcie = to_ls_pcie(pp);
+ u32 val;
+
+ dw_pcie_dbi_write(pp, 1, PCIE_DBI_RO_WR_EN);
+ /* Fix class value */
+ val = dw_pcie_dbi_read(pp, PCI_CLASS_REVISION);
+ val = (val & 0x0000ffff) | (PCI_CLASS_BRIDGE_PCI << 16);
+ dw_pcie_dbi_write(pp, val, PCI_CLASS_REVISION);
+ /* clean multi-func bit */
+ val = dw_pcie_dbi_read(pp, PCI_HEADER_TYPE & ~0x3);
+ val &= ~(1 << 23);
+ dw_pcie_dbi_write(pp, val, PCI_HEADER_TYPE & ~0x3);
+ dw_pcie_dbi_write(pp, 0, PCIE_DBI_RO_WR_EN);
+
+ if (!ls2_pcie_link_up(pp))
+ dev_err(pp->dev, "phy link never came up\n");
return 0;
}
+static struct dw_host_ops ls2_dw_host_ops = {
+ .link_up = ls2_pcie_link_up,
+ .host_init = ls2_pcie_host_init,
+};
+
+static const struct of_device_id ls_pcie_of_match[] = {
+ { .compatible = "fsl,ls1021a-pcie", .data = &ls1_dw_host_ops },
+ { .compatible = "fsl,ls2085a-pcie", .data = &ls2_dw_host_ops },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
+
static int __init ls_pcie_probe(struct platform_device *pdev)
{
+ const struct of_device_id *match;
struct ls_pcie *pcie;
- struct resource *dbi_base;
- u32 index[2];
+ struct resource *res;
int ret;
+ match = of_match_device(ls_pcie_of_match, &pdev->dev);
+ if (!match)
+ return -ENODEV;
+
pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
if (!pcie)
return -ENOMEM;
- pcie->dev = &pdev->dev;
-
- dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
- pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
- if (IS_ERR(pcie->dbi)) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+ pcie->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pcie->regs)) {
dev_err(&pdev->dev, "missing *regs* space\n");
- return PTR_ERR(pcie->dbi);
- }
-
- pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
- "fsl,pcie-scfg");
- if (IS_ERR(pcie->scfg)) {
- dev_err(&pdev->dev, "No syscfg phandle specified\n");
- return PTR_ERR(pcie->scfg);
+ return PTR_ERR(pcie->regs);
}
- ret = of_property_read_u32_array(pdev->dev.of_node,
- "fsl,pcie-scfg", index, 2);
- if (ret)
- return ret;
- pcie->index = index[1];
+ pcie->lut = pcie->regs + PCIE_LUT_BASE;
+ pcie->pp.dev = &pdev->dev;
+ pcie->pp.dbi = pcie->regs;
+ pcie->pp.dw_ops = (struct dw_host_ops *)match->data;
+ pcie->pp.atu_num = PCIE_ATU_NUM;
- ret = ls_add_pcie_port(pcie);
+ ret = dw_pcie_port_init(&pcie->pp);
if (ret < 0)
return ret;
@@ -155,12 +191,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id ls_pcie_of_match[] = {
- { .compatible = "fsl,ls1021a-pcie" },
- { },
-};
-MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
-
static struct platform_driver ls_pcie_driver = {
.driver = {
.name = "layerscape-pcie",
diff --git a/drivers/pci/host/pcie-designware-base.h b/drivers/pci/host/pcie-designware-base.h
index 60c82de..98b62d6 100644
--- a/drivers/pci/host/pcie-designware-base.h
+++ b/drivers/pci/host/pcie-designware-base.h
@@ -10,6 +10,9 @@
#define _PCIE_DESIGNWARE_BASE_H
/* Synopsis specific PCIE configuration registers */
+#define PCIE_SYMBOL_TIMER_1 0x71c
+#define PCIE_DBI_RO_WR_EN 0x8bc
+
#define PCIE_ATU_VIEWPORT 0x900
#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
--
1.9.1
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