* [PATCH RESEND 1/3] ARM: Meson6: docs: document bindings
2014-11-14 16:25 [PATCH RESEND 0/3] ARM: Meson6: enable SMP Carlo Caione
@ 2014-11-14 16:25 ` Carlo Caione
2014-11-14 16:25 ` [PATCH RESEND 2/3] ARM: Meson6: Add SMP support for Amlogic Meson6 Carlo Caione
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Carlo Caione @ 2014-11-14 16:25 UTC (permalink / raw)
To: linux-arm-kernel
Documentation for the devicetree bindings introduced with the SMP support
Signed-off-by: Carlo Caione <carlo@caione.org>
---
.../bindings/arm/meson/amlogic,meson6-cpuconfig | 16 +++++++++++++
.../bindings/arm/meson/amlogic,meson6-smp | 26 ++++++++++++++++++++++
2 files changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig
create mode 100644 Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp
diff --git a/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig b/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig
new file mode 100644
index 0000000..2db4cbb
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig
@@ -0,0 +1,16 @@
+Secondary CPU management unit:
+-------------------------------
+
+This document describes the "amlogic,meson6-cpuconfig" node for enabling the
+secondary CPU.
+
+Required node properties:
+- compatible value : = "amlogic,meson6-cpuconfig";
+- reg : physical base address and the size of the registers window
+
+Example:
+
+ cpuconfig at d901ff80 {
+ compatible = "amlogic,meson6-cpuconfig";
+ reg = <0xd901ff80 0x8>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp b/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp
new file mode 100644
index 0000000..4130381
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp
@@ -0,0 +1,26 @@
+Secondary CPU enable-method "amlogic,meson6-smp" binding:
+----------------------------------------------------------
+
+This document describes the "amlogic,meson6-smp" method for enabling secondary
+CPUs. To apply to all CPUs, a single "amlogic,meson6-smp" enable method should
+be defined in the "cpus" node.
+
+Example:
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "amlogic,meson6-smp";
+
+ cpu at 200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0x200>;
+ };
+
+ cpu at 201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0x201>;
+ };
+ };
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH RESEND 2/3] ARM: Meson6: Add SMP support for Amlogic Meson6
2014-11-14 16:25 [PATCH RESEND 0/3] ARM: Meson6: enable SMP Carlo Caione
2014-11-14 16:25 ` [PATCH RESEND 1/3] ARM: Meson6: docs: document bindings Carlo Caione
@ 2014-11-14 16:25 ` Carlo Caione
2014-11-24 15:20 ` Arnd Bergmann
2014-11-14 16:25 ` [PATCH RESEND 3/3] ARM: Meson6: enable SMP in DTS/DTSI Carlo Caione
2014-11-23 11:48 ` [PATCH RESEND 0/3] ARM: Meson6: enable SMP Carlo Caione
3 siblings, 1 reply; 8+ messages in thread
From: Carlo Caione @ 2014-11-14 16:25 UTC (permalink / raw)
To: linux-arm-kernel
Amlogic Meson6 is a dual core Cortex-A9. This patch adds the logic to
boot up the second CPU.
Signed-off-by: Carlo Caione <carlo@caione.org>
---
arch/arm/mach-meson/Kconfig | 1 +
arch/arm/mach-meson/Makefile | 1 +
arch/arm/mach-meson/headsmp.S | 7 ++++
arch/arm/mach-meson/platsmp.c | 80 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 89 insertions(+)
create mode 100644 arch/arm/mach-meson/headsmp.S
create mode 100644 arch/arm/mach-meson/platsmp.c
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 2c1154e..4e96de4 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -2,6 +2,7 @@ menuconfig ARCH_MESON
bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
select GENERIC_IRQ_CHIP
select ARM_GIC
+ select HAVE_ARM_SCU if SMP
if ARCH_MESON
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index 9d7380e..4691966 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_ARCH_MESON) += meson.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-meson/headsmp.S b/arch/arm/mach-meson/headsmp.S
new file mode 100644
index 0000000..3347d88
--- /dev/null
+++ b/arch/arm/mach-meson/headsmp.S
@@ -0,0 +1,7 @@
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ENTRY(meson_secondary_startup)
+ bl v7_invalidate_l1
+ b secondary_startup
+ENDPROC(meson_secondary_startup)
diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c
new file mode 100644
index 0000000..3d4d0cd
--- /dev/null
+++ b/arch/arm/mach-meson/platsmp.c
@@ -0,0 +1,80 @@
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/delay.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+#include <asm/cacheflush.h>
+
+#define MESON_CPU_CONTROL_REG 0x0
+#define MESON_CPU1_CONTROL_ADDR_REG 0x4
+
+#define MESON_CPU_CONTROL_ID(cpu) ((1 << (cpu)) | 1)
+
+static void __iomem *cpucfg_membase;
+static void __iomem *scu_membase;
+
+static DEFINE_SPINLOCK(cpu_lock);
+
+extern void meson_secondary_startup(void);
+
+static void __init meson6_smp_prepare_cpus(unsigned int max_cpus)
+{
+ struct device_node *node;
+
+ node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+ if (!node) {
+ pr_err("Missing Meson6 SCU node\n");
+ return;
+ }
+
+ scu_membase = of_iomap(node, 0);
+ if (!scu_membase) {
+ pr_err("Couln't map Meson6 SCU registers\n");
+ return;
+ }
+
+ node = of_find_compatible_node(NULL, NULL, "amlogic,meson6-cpuconfig");
+ if (!node) {
+ pr_err("Missing Meson6 CPU config node\n");
+ return;
+ }
+
+ cpucfg_membase = of_iomap(node, 0);
+ if (!cpucfg_membase) {
+ pr_err("Couldn't map Meson6 CPU config registers\n");
+ return;
+ }
+
+ scu_enable(scu_membase);
+}
+
+static int meson6_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ if (!cpucfg_membase)
+ return -EFAULT;
+
+ spin_lock(&cpu_lock);
+
+ writel(virt_to_phys(meson_secondary_startup), cpucfg_membase +
+ MESON_CPU1_CONTROL_ADDR_REG);
+ writel(MESON_CPU_CONTROL_ID(cpu), cpucfg_membase +
+ MESON_CPU_CONTROL_REG);
+
+ smp_wmb();
+
+ dsb_sev();
+
+ spin_unlock(&cpu_lock);
+
+ return 0;
+}
+
+static struct smp_operations meson6_smp_ops __initdata = {
+ .smp_prepare_cpus = meson6_smp_prepare_cpus,
+ .smp_boot_secondary = meson6_smp_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(meson6_smp, "amlogic,meson6-smp", &meson6_smp_ops);
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH RESEND 2/3] ARM: Meson6: Add SMP support for Amlogic Meson6
2014-11-14 16:25 ` [PATCH RESEND 2/3] ARM: Meson6: Add SMP support for Amlogic Meson6 Carlo Caione
@ 2014-11-24 15:20 ` Arnd Bergmann
0 siblings, 0 replies; 8+ messages in thread
From: Arnd Bergmann @ 2014-11-24 15:20 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 14 November 2014, Carlo Caione wrote:
> +static void __iomem *cpucfg_membase;
> +static void __iomem *scu_membase;
I don't think you need a global scu_membase variable, you use it only in
one function.
> +static DEFINE_SPINLOCK(cpu_lock);
> +
> +extern void meson_secondary_startup(void);
Better put the extern declaration into a header file.
> +static void __init meson6_smp_prepare_cpus(unsigned int max_cpus)
> +{
> + struct device_node *node;
> +
> + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
> + if (!node) {
> + pr_err("Missing Meson6 SCU node\n");
> + return;
> + }
> +
> + scu_membase = of_iomap(node, 0);
> + if (!scu_membase) {
> + pr_err("Couln't map Meson6 SCU registers\n");
> + return;
> + }
> +
> + node = of_find_compatible_node(NULL, NULL, "amlogic,meson6-cpuconfig");
> + if (!node) {
> + pr_err("Missing Meson6 CPU config node\n");
> + return;
> + }
I'm not sure about the "amlogic,meson6-cpuconfig" device node. Since this
is just an 8-byte register range, I suspect it's actually part of a larger
device, so you should better represent that instead. We can now have
early "syscon" devices (in linux-next I think), so you could instead make
this a device that is compatible with "syscon" and have the smp code
look that up and apply an appropriate offset. Do you have an idea of
which device this is part of?
Arnd
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH RESEND 3/3] ARM: Meson6: enable SMP in DTS/DTSI
2014-11-14 16:25 [PATCH RESEND 0/3] ARM: Meson6: enable SMP Carlo Caione
2014-11-14 16:25 ` [PATCH RESEND 1/3] ARM: Meson6: docs: document bindings Carlo Caione
2014-11-14 16:25 ` [PATCH RESEND 2/3] ARM: Meson6: Add SMP support for Amlogic Meson6 Carlo Caione
@ 2014-11-14 16:25 ` Carlo Caione
2014-11-23 11:48 ` [PATCH RESEND 0/3] ARM: Meson6: enable SMP Carlo Caione
3 siblings, 0 replies; 8+ messages in thread
From: Carlo Caione @ 2014-11-14 16:25 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Carlo Caione <carlo@caione.org>
---
arch/arm/boot/dts/meson.dtsi | 5 +++++
arch/arm/boot/dts/meson6.dtsi | 6 ++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea..6178756 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -64,6 +64,11 @@
interrupts = <0 10 1>;
};
+ scu at c4300000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xc4300000 0x1000>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 4ba4912..6e7230f 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -56,6 +56,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "amlogic,meson6-smp";
cpu at 200 {
device_type = "cpu";
@@ -70,6 +71,11 @@
};
};
+ cpuconfig at d901ff80 {
+ compatible = "amlogic,meson6-cpuconfig";
+ reg = <0xd901ff80 0x8>;
+ };
+
clk81: clk at 0 {
#clock-cells = <0>;
compatible = "fixed-clock";
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH RESEND 0/3] ARM: Meson6: enable SMP
2014-11-14 16:25 [PATCH RESEND 0/3] ARM: Meson6: enable SMP Carlo Caione
` (2 preceding siblings ...)
2014-11-14 16:25 ` [PATCH RESEND 3/3] ARM: Meson6: enable SMP in DTS/DTSI Carlo Caione
@ 2014-11-23 11:48 ` Carlo Caione
2014-11-24 14:24 ` Arnd Bergmann
3 siblings, 1 reply; 8+ messages in thread
From: Carlo Caione @ 2014-11-23 11:48 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Nov 14, 2014 at 5:25 PM, Carlo Caione <carlo@caione.org> wrote:
> Amlogic Meson6 is a dual-core Cortex-A9. This patchset adds all the necessary
> pieces to boot the secondary CPU.
>
> ---
>
> This is a resend of a patchset already submitted a while ago
> http://www.spinics.net/lists/arm-kernel/msg366787.html
>
> Carlo Caione (3):
> ARM: Meson6: docs: document bindings
> ARM: Meson6: Add SMP support for Amlogic Meson6
> ARM: Meson6: enable SMP in DTS/DTSI
>
> .../bindings/arm/meson/amlogic,meson6-cpuconfig | 16 +++++
> .../bindings/arm/meson/amlogic,meson6-smp | 26 +++++++
> arch/arm/boot/dts/meson.dtsi | 5 ++
> arch/arm/boot/dts/meson6.dtsi | 6 ++
> arch/arm/mach-meson/Kconfig | 1 +
> arch/arm/mach-meson/Makefile | 1 +
> arch/arm/mach-meson/headsmp.S | 7 ++
> arch/arm/mach-meson/platsmp.c | 80 ++++++++++++++++++++++
> 8 files changed, 142 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig
> create mode 100644 Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp
> create mode 100644 arch/arm/mach-meson/headsmp.S
> create mode 100644 arch/arm/mach-meson/platsmp.c
Ping
--
Carlo Caione
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH RESEND 0/3] ARM: Meson6: enable SMP
2014-11-23 11:48 ` [PATCH RESEND 0/3] ARM: Meson6: enable SMP Carlo Caione
@ 2014-11-24 14:24 ` Arnd Bergmann
2014-11-24 14:46 ` Carlo Caione
0 siblings, 1 reply; 8+ messages in thread
From: Arnd Bergmann @ 2014-11-24 14:24 UTC (permalink / raw)
To: linux-arm-kernel
On Sunday 23 November 2014 12:48:31 Carlo Caione wrote:
> On Fri, Nov 14, 2014 at 5:25 PM, Carlo Caione <carlo@caione.org> wrote:
> > Amlogic Meson6 is a dual-core Cortex-A9. This patchset adds all the necessary
> > pieces to boot the secondary CPU.
> >
> > ---
> >
> > This is a resend of a patchset already submitted a while ago
> > http://www.spinics.net/lists/arm-kernel/msg366787.html
> >
>
> Ping
Hi Carlo,
Is this for arm-soc? I guess from the contents that it is, but you had
10 people in 'To', and you don't say in the introductory mail what
you would like to happen with these patches.
When you send something for inclusion in arm-soc, please always send
it 'To: arm at kernel.org' with everyone else on Cc instead of To,
and be explicit with whether you think the contents are ready to
be merged or whether you would like to see more review.
Arnd
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH RESEND 0/3] ARM: Meson6: enable SMP
2014-11-24 14:24 ` Arnd Bergmann
@ 2014-11-24 14:46 ` Carlo Caione
0 siblings, 0 replies; 8+ messages in thread
From: Carlo Caione @ 2014-11-24 14:46 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Nov 24, 2014 at 3:24 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Sunday 23 November 2014 12:48:31 Carlo Caione wrote:
>> On Fri, Nov 14, 2014 at 5:25 PM, Carlo Caione <carlo@caione.org> wrote:
>> > Amlogic Meson6 is a dual-core Cortex-A9. This patchset adds all the necessary
>> > pieces to boot the secondary CPU.
>> >
>> > ---
>> >
>> > This is a resend of a patchset already submitted a while ago
>> > http://www.spinics.net/lists/arm-kernel/msg366787.html
>> >
>>
>> Ping
>
> Hi Carlo,
>
> Is this for arm-soc? I guess from the contents that it is, but you had
> 10 people in 'To', and you don't say in the introductory mail what
> you would like to happen with these patches.
>
> When you send something for inclusion in arm-soc, please always send
> it 'To: arm at kernel.org' with everyone else on Cc instead of To,
> and be explicit with whether you think the contents are ready to
> be merged or whether you would like to see more review.
Hi Arnd,
my ping was because I haven't received any feedback on the patchset.
Taking the silence as an ACK I'll take the patches in my repo to pull
to arm-soc within the next pull request.
Thanks,
--
Carlo Caione
^ permalink raw reply [flat|nested] 8+ messages in thread