[PATCH] ARM: use default ioremap alignment for SMP or LPAE

[PATCH] ARM: use default ioremap alignment for SMP or LPAE

[Sergey Dyasly]

16MB alignment for ioremap mappings was added by commit a069c896d0d6 ("[ARM]
3705/1: add supersection support to ioremap()") in order to support supersection
mappings. But __arm_ioremap_pfn_caller uses section and supersection mappings
only in !SMP && !LPAE case. There is no need for such big alignment if either
SMP or LPAE is enabled.

After this change, ioremap will use default maximum alignment of 128 pages.

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: James Bottomley <JBottomley@parallels.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Arnd Bergmann <arnd.bergmann@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Dmitry Safonov <d.safonov@partner.samsung.com>
Link: https://lkml.kernel.org/g/1419328813-2211-1-git-send-email-d.safonov at partner.samsung.com
Signed-off-by: Sergey Dyasly <s.dyasly@samsung.com>
---
 arch/arm/include/asm/memory.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 184def0..c3ef139 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -78,10 +78,12 @@
  */
 #define XIP_VIRT_ADDR(physaddr)  (MODULES_VADDR + ((physaddr) & 0x000fffff))
 
+#if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
 /*
  * Allow 16MB-aligned ioremap pages
  */
 #define IOREMAP_MAX_ORDER	24
+#endif
 
 #else /* CONFIG_MMU */
 
-- 
1.7.9.5

[PATCH] ARM: use default ioremap alignment for SMP or LPAE

[Catalin Marinas]

On Thu, Jan 22, 2015 at 07:17:55AM +0000, Sergey Dyasly wrote:
> 16MB alignment for ioremap mappings was added by commit a069c896d0d6 ("[ARM]
> 3705/1: add supersection support to ioremap()") in order to support supersection
> mappings. But __arm_ioremap_pfn_caller uses section and supersection mappings
> only in !SMP && !LPAE case. There is no need for such big alignment if either
> SMP or LPAE is enabled.
[...]
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 184def0..c3ef139 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -78,10 +78,12 @@
>   */
>  #define XIP_VIRT_ADDR(physaddr)  (MODULES_VADDR + ((physaddr) & 0x000fffff))
>  
> +#if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
>  /*
>   * Allow 16MB-aligned ioremap pages
>   */
>  #define IOREMAP_MAX_ORDER	24
> +#endif

Actually, I think we could make this depend only on CONFIG_IO_36. That's
the only scenario where we get the supersections matter, and maybe make
CONFIG_IO_36 dependent on !SMP or !ARM_LPAE. My assumption is that we
don't support single zImage with CPU_XSC3 enabled (but I haven't
followed the latest developments here).

-- 
Catalin

[PATCH] ARM: use default ioremap alignment for SMP or LPAE

[Arnd Bergmann]

On Thursday 22 January 2015 10:04:41 Catalin Marinas wrote:
> On Thu, Jan 22, 2015 at 07:17:55AM +0000, Sergey Dyasly wrote:
> > 16MB alignment for ioremap mappings was added by commit a069c896d0d6 ("[ARM]
> > 3705/1: add supersection support to ioremap()") in order to support supersection
> > mappings. But __arm_ioremap_pfn_caller uses section and supersection mappings
> > only in !SMP && !LPAE case. There is no need for such big alignment if either
> > SMP or LPAE is enabled.
> [...]
> > diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> > index 184def0..c3ef139 100644
> > --- a/arch/arm/include/asm/memory.h
> > +++ b/arch/arm/include/asm/memory.h
> > @@ -78,10 +78,12 @@
> >   */
> >  #define XIP_VIRT_ADDR(physaddr)  (MODULES_VADDR + ((physaddr) & 0x000fffff))
> >  
> > +#if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
> >  /*
> >   * Allow 16MB-aligned ioremap pages
> >   */
> >  #define IOREMAP_MAX_ORDER    24
> > +#endif
> 
> Actually, I think we could make this depend only on CONFIG_IO_36. That's
> the only scenario where we get the supersections matter, and maybe make
> CONFIG_IO_36 dependent on !SMP or !ARM_LPAE.

Good point, I assumed this was just a performance optimization,
but it is in fact required for dynamic high mappings on XSC3.

> My assumption is that we
> don't support single zImage with CPU_XSC3 enabled (but I haven't
> followed the latest developments here).

I have said in the past that I do not expect any of the xscale or
strongarm based platforms to be used with a single zImage kernel.
This has changed slightly given the work that Robert Jarzmik and
others are doing on mach-pxa with DT conversion. I still don't
think it's likely that they will move on to multiplatform, but I
no longer think it's impossible.

Fortunately, PXA also does not have any high physical address mappings
that I can see. The only platform we have that has these (see
'git grep ioremap_pfn') is mach-iop13xx, and I am still seeing
this in the 'never going to be multiplatform' category.

Unrelated to this question however is whether we want to keep
supersection mappings as a performance optimization to save TLBs.
It seems useful to me, but not critical.

	Arnd

[PATCH] ARM: use default ioremap alignment for SMP or LPAE

[Catalin Marinas]

On Thu, Jan 22, 2015 at 11:03:00AM +0000, Arnd Bergmann wrote:
> Unrelated to this question however is whether we want to keep
> supersection mappings as a performance optimization to save TLBs.
> It seems useful to me, but not critical.

Currently in Linux we allow 16MB mappings only if the phys address is
over 32-bit and !LPAE which makes it unlikely for normal RAM with
pre-LPAE hardware.

IIRC a bigger problem was that supersections are optional in the
architecture but there was no CPUID bit field in ARMv6 (and early ARMv7)
to check for their presence. The ID_MMFR3 contains this information but
for example on early Cortex-A8 that bitfield was reserved and the TRM
states "unpredictable" on read (so probably zero in practice).

On newer ARMv7 (not necessarily with LPAE), we could indeed revisit the
16MB section mapping but it won't go well with single zImage if you want
to support earlier ARMv7 or ARMv6.

-- 
Catalin

[PATCH] ARM: use default ioremap alignment for SMP or LPAE

[Arnd Bergmann]

On Friday 23 January 2015 14:52:36 Catalin Marinas wrote:
> On Thu, Jan 22, 2015 at 11:03:00AM +0000, Arnd Bergmann wrote:
> > Unrelated to this question however is whether we want to keep
> > supersection mappings as a performance optimization to save TLBs.
> > It seems useful to me, but not critical.
> 
> Currently in Linux we allow 16MB mappings only if the phys address is
> over 32-bit and !LPAE which makes it unlikely for normal RAM with
> pre-LPAE hardware.

Ah, I missed this part when looking at the code.

> IIRC a bigger problem was that supersections are optional in the
> architecture but there was no CPUID bit field in ARMv6 (and early ARMv7)
> to check for their presence. The ID_MMFR3 contains this information but
> for example on early Cortex-A8 that bitfield was reserved and the TRM
> states "unpredictable" on read (so probably zero in practice).
> 
> On newer ARMv7 (not necessarily with LPAE), we could indeed revisit the
> 16MB section mapping but it won't go well with single zImage if you want
> to support earlier ARMv7 or ARMv6.

I see. If there is desire to have it as an optimization, we could do
it for armv7ve-only kernels. We don't currently have an build-time
option for those, but we should introduce one anyway, in order to
better make use of the idiv instructions and to prevent one from
enabling LPAE on a multiplatform kernel that contains pre-lpae armv7
machines (Cortex a8/a9/a5, and some others I'm not sure about).

	Arnd