* [PATCH 01/19] ARM: dts: r8a7790: use fallback pcie compatibility string
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
@ 2016-02-25 23:52 ` Simon Horman
2016-02-25 23:52 ` [PATCH 02/19] ARM: dts: r8a7791: " Simon Horman
` (18 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:52 UTC (permalink / raw)
To: linux-arm-kernel
Use recently added fallback compatibility string in r8a7790 device tree.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index c9583fa6cae7..db019f2619c7 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1590,7 +1590,7 @@
};
pciec: pcie at fe000000 {
- compatible = "renesas,pcie-r8a7790";
+ compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 02/19] ARM: dts: r8a7791: use fallback pcie compatibility string
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
2016-02-25 23:52 ` [PATCH 01/19] ARM: dts: r8a7790: use fallback pcie compatibility string Simon Horman
@ 2016-02-25 23:52 ` Simon Horman
2016-02-25 23:52 ` [PATCH 03/19] ARM: dts: r8a7790: use fallback pci " Simon Horman
` (17 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:52 UTC (permalink / raw)
To: linux-arm-kernel
Use recently added fallback compatibility string in r8a7791 device tree.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 14aa62539ff2..4456f54a5005 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1600,7 +1600,7 @@
};
pciec: pcie at fe000000 {
- compatible = "renesas,pcie-r8a7791";
+ compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 03/19] ARM: dts: r8a7790: use fallback pci compatibility string
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
2016-02-25 23:52 ` [PATCH 01/19] ARM: dts: r8a7790: use fallback pcie compatibility string Simon Horman
2016-02-25 23:52 ` [PATCH 02/19] ARM: dts: r8a7791: " Simon Horman
@ 2016-02-25 23:52 ` Simon Horman
2016-02-25 23:52 ` [PATCH 04/19] ARM: dts: r8a7791: " Simon Horman
` (16 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:52 UTC (permalink / raw)
To: linux-arm-kernel
Use recently added fallback compatibility string in r8a7790 device tree.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index db019f2619c7..76ddf5c6cca7 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1499,7 +1499,7 @@
};
pci0: pci at ee090000 {
- compatible = "renesas,pci-r8a7790";
+ compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
@@ -1534,7 +1534,7 @@
};
pci1: pci at ee0b0000 {
- compatible = "renesas,pci-r8a7790";
+ compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee0b0000 0 0xc00>,
<0 0xee0a0000 0 0x1100>;
@@ -1555,7 +1555,7 @@
};
pci2: pci at ee0d0000 {
- compatible = "renesas,pci-r8a7790";
+ compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
device_type = "pci";
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
power-domains = <&cpg_clocks>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 04/19] ARM: dts: r8a7791: use fallback pci compatibility string
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (2 preceding siblings ...)
2016-02-25 23:52 ` [PATCH 03/19] ARM: dts: r8a7790: use fallback pci " Simon Horman
@ 2016-02-25 23:52 ` Simon Horman
2016-02-25 23:52 ` [PATCH 05/19] ARM: dts: r8a7794: " Simon Horman
` (15 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:52 UTC (permalink / raw)
To: linux-arm-kernel
Use recently added fallback compatibility string in r8a7791 device tree.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 4456f54a5005..8910236e64bf 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1530,7 +1530,7 @@
};
pci0: pci at ee090000 {
- compatible = "renesas,pci-r8a7791";
+ compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
@@ -1565,7 +1565,7 @@
};
pci1: pci at ee0d0000 {
- compatible = "renesas,pci-r8a7791";
+ compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 05/19] ARM: dts: r8a7794: use fallback pci compatibility string
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (3 preceding siblings ...)
2016-02-25 23:52 ` [PATCH 04/19] ARM: dts: r8a7791: " Simon Horman
@ 2016-02-25 23:52 ` Simon Horman
2016-02-25 23:52 ` [PATCH 06/19] ARM: dts: porter: fix JP3 jumper description Simon Horman
` (14 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:52 UTC (permalink / raw)
To: linux-arm-kernel
Use recently added fallback compatibility string in r8a7794 device tree.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 7d4c5597af5b..df0861e84a4b 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -681,7 +681,7 @@
};
pci0: pci at ee090000 {
- compatible = "renesas,pci-r8a7794";
+ compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
@@ -716,7 +716,7 @@
};
pci1: pci at ee0d0000 {
- compatible = "renesas,pci-r8a7794";
+ compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 06/19] ARM: dts: porter: fix JP3 jumper description
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (4 preceding siblings ...)
2016-02-25 23:52 ` [PATCH 05/19] ARM: dts: r8a7794: " Simon Horman
@ 2016-02-25 23:52 ` Simon Horman
2016-02-25 23:52 ` [PATCH 07/19] ARM: dts: r8a7790: enable to use thermal-zone Simon Horman
` (13 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
When finishing the Porter sound support patch, I managed to call the JP3
jumper SW3 in the comment. Fix this along with (also miscalled) jumper
positions...
Fixes: 493b4da7c10c ("ARM: dts: porter: add sound support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791-porter.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index ed1f6f884e2b..bf3a0d13cd35 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -11,8 +11,8 @@
/*
* SSI-AK4642
*
- * SW3: 1: AK4642
- * 3: ADV7511
+ * JP3: 2-1: AK4642
+ * 2-3: ADV7511
*
* This command is required before playback/capture:
*
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 07/19] ARM: dts: r8a7790: enable to use thermal-zone
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (5 preceding siblings ...)
2016-02-25 23:52 ` [PATCH 06/19] ARM: dts: porter: fix JP3 jumper description Simon Horman
@ 2016-02-25 23:52 ` Simon Horman
2016-02-25 23:52 ` [PATCH 08/19] ARM: dts: r8a7791: " Simon Horman
` (12 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch enables to use thermal-zone on r8a7790.
This thermal sensor can measure temperature from -40000 to 125000,
but over 117000 can be critical on this chip.
Thus, default critical temperature is now set as 115000 (this driver
is using 5000 steps) (Current critical temperature is using it as
90000, but there is no big reason about it)
And it doesn't check thermal zone periodically (same as current
behavior). You can exchange it by modifying polling-delay[-passive]
property.
You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS,
but you need to take care to use it, since it will call
orderly_poweroff() it it reaches to the value.
echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790.dtsi | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 76ddf5c6cca7..24b773ae133a 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -112,6 +112,25 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+ };
+
gic: interrupt-controller at f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -202,12 +221,15 @@
power-domains = <&cpg_clocks>;
};
- thermal at e61f0000 {
- compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+ thermal: thermal at e61f0000 {
+ compatible = "renesas,thermal-r8a7790",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
power-domains = <&cpg_clocks>;
+ #thermal-sensor-cells = <0>;
};
timer {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 08/19] ARM: dts: r8a7791: enable to use thermal-zone
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (6 preceding siblings ...)
2016-02-25 23:52 ` [PATCH 07/19] ARM: dts: r8a7790: enable to use thermal-zone Simon Horman
@ 2016-02-25 23:52 ` Simon Horman
2016-02-25 23:52 ` [PATCH 09/19] ARM: dts: r8a7793: " Simon Horman
` (11 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch enables to use thermal-zone on r8a7791.
This thermal sensor can measure temperature from -40000 to 125000,
but over 117000 can be critical on this chip.
Thus, default critical temperature is now set as 115000 (this driver
is using 5000 steps) (Current critical temperature is using it as
90000, but there is no big reason about it)
And it doesn't check thermal zone periodically (same as current
behavior). You can exchange it by modifying polling-delay[-passive]
property.
You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS,
but you need to take care to use it, since it will call
orderly_poweroff() it it reaches to the value.
echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791.dtsi | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 8910236e64bf..f1732dde114b 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -69,6 +69,25 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+ };
+
gic: interrupt-controller at f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -185,12 +204,15 @@
power-domains = <&cpg_clocks>;
};
- thermal at e61f0000 {
- compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
+ thermal: thermal at e61f0000 {
+ compatible = "renesas,thermal-r8a7791",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
power-domains = <&cpg_clocks>;
+ #thermal-sensor-cells = <0>;
};
timer {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 09/19] ARM: dts: r8a7793: enable to use thermal-zone
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (7 preceding siblings ...)
2016-02-25 23:52 ` [PATCH 08/19] ARM: dts: r8a7791: " Simon Horman
@ 2016-02-25 23:52 ` Simon Horman
2016-02-25 23:52 ` [PATCH 10/19] ARM: dts: r8a73a4: Add L2 cache-controller nodes Simon Horman
` (10 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch enables to use thermal-zone on r8a7793.
This thermal sensor can measure temperature from -40000 to 125000,
but over 117000 can be critical on this chip.
Thus, default critical temperature is now set as 115000 (this driver
is using 5000 steps) (Current critical temperature is using it as
90000, but there is no big reason about it)
And it doesn't check thermal zone periodically (same as current
behavior). You can exchange it by modifying polling-delay[-passive]
property.
You can set trip temp if your kernel has CONFIG_THERMAL_WRITABLE_TRIPS,
but you need to take care to use it, since it will call
orderly_poweroff() it it reaches to the value.
echo $temp > /sys/class/thermal/thermal_zone0/trip_point_0_temp
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7793.dtsi | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 45dba1c79a43..9837f90f1718 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -54,6 +54,25 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+ };
+
gic: interrupt-controller at f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -170,12 +189,15 @@
power-domains = <&cpg_clocks>;
};
- thermal at e61f0000 {
- compatible = "renesas,thermal-r8a7793", "renesas,rcar-thermal";
+ thermal: thermal at e61f0000 {
+ compatible = "renesas,thermal-r8a7793",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
power-domains = <&cpg_clocks>;
+ #thermal-sensor-cells = <0>;
};
timer {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 10/19] ARM: dts: r8a73a4: Add L2 cache-controller nodes
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (8 preceding siblings ...)
2016-02-25 23:52 ` [PATCH 09/19] ARM: dts: r8a7793: " Simon Horman
@ 2016-02-25 23:52 ` Simon Horman
2016-02-25 23:53 ` [PATCH 11/19] ARM: dts: r8a7790: " Simon Horman
` (9 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a73a4.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 138414a7d170..6583a1dfca1f 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -29,6 +29,7 @@
reg = <0>;
clock-frequency = <1500000000>;
power-domains = <&pd_a2sl>;
+ next-level-cache = <&L2_CA15>;
};
};
@@ -45,6 +46,22 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
+ L2_CA15: cache-controller at 0 {
+ compatible = "cache";
+ clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+ power-domains = <&pd_a3sm>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ L2_CA7: cache-controller at 1 {
+ compatible = "cache";
+ clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+ power-domains = <&pd_a3km>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
dbsc1: memory-controller at e6790000 {
compatible = "renesas,dbsc-r8a73a4";
reg = <0 0xe6790000 0 0x10000>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 11/19] ARM: dts: r8a7790: Add L2 cache-controller nodes
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (9 preceding siblings ...)
2016-02-25 23:52 ` [PATCH 10/19] ARM: dts: r8a73a4: Add L2 cache-controller nodes Simon Horman
@ 2016-02-25 23:53 ` Simon Horman
2016-02-25 23:53 ` [PATCH 12/19] ARM: dts: r8a7791: Add L2 cache-controller node Simon Horman
` (8 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add device nodes for the L2 caches, and link the CPU nodes to them.
The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 24b773ae133a..ba4c2530d79f 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -52,6 +52,7 @@
voltage-tolerance = <1>; /* 1% */
clocks = <&cpg_clocks R8A7790_CLK_Z>;
clock-latency = <300000>; /* 300 us */
+ next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1400000 1000000>,
@@ -67,6 +68,7 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1300000000>;
+ next-level-cache = <&L2_CA15>;
};
cpu2: cpu at 2 {
@@ -74,6 +76,7 @@
compatible = "arm,cortex-a15";
reg = <2>;
clock-frequency = <1300000000>;
+ next-level-cache = <&L2_CA15>;
};
cpu3: cpu at 3 {
@@ -81,6 +84,7 @@
compatible = "arm,cortex-a15";
reg = <3>;
clock-frequency = <1300000000>;
+ next-level-cache = <&L2_CA15>;
};
cpu4: cpu at 4 {
@@ -88,6 +92,7 @@
compatible = "arm,cortex-a7";
reg = <0x100>;
clock-frequency = <780000000>;
+ next-level-cache = <&L2_CA7>;
};
cpu5: cpu at 5 {
@@ -95,6 +100,7 @@
compatible = "arm,cortex-a7";
reg = <0x101>;
clock-frequency = <780000000>;
+ next-level-cache = <&L2_CA7>;
};
cpu6: cpu at 6 {
@@ -102,6 +108,7 @@
compatible = "arm,cortex-a7";
reg = <0x102>;
clock-frequency = <780000000>;
+ next-level-cache = <&L2_CA7>;
};
cpu7: cpu at 7 {
@@ -109,6 +116,7 @@
compatible = "arm,cortex-a7";
reg = <0x103>;
clock-frequency = <780000000>;
+ next-level-cache = <&L2_CA7>;
};
};
@@ -131,6 +139,18 @@
};
};
+ L2_CA15: cache-controller at 0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ L2_CA7: cache-controller at 1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
gic: interrupt-controller at f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 12/19] ARM: dts: r8a7791: Add L2 cache-controller node
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (10 preceding siblings ...)
2016-02-25 23:53 ` [PATCH 11/19] ARM: dts: r8a7790: " Simon Horman
@ 2016-02-25 23:53 ` Simon Horman
2016-02-25 23:53 ` [PATCH 13/19] ARM: dts: r8a7793: " Simon Horman
` (7 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7791.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index f1732dde114b..6439f0569fe2 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -51,6 +51,7 @@
voltage-tolerance = <1>; /* 1% */
clocks = <&cpg_clocks R8A7791_CLK_Z>;
clock-latency = <300000>; /* 300 us */
+ next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
@@ -66,6 +67,7 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
+ next-level-cache = <&L2_CA15>;
};
};
@@ -88,6 +90,12 @@
};
};
+ L2_CA15: cache-controller at 0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
gic: interrupt-controller at f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 13/19] ARM: dts: r8a7793: Add L2 cache-controller node
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (11 preceding siblings ...)
2016-02-25 23:53 ` [PATCH 12/19] ARM: dts: r8a7791: Add L2 cache-controller node Simon Horman
@ 2016-02-25 23:53 ` Simon Horman
2016-02-25 23:53 ` [PATCH 14/19] ARM: dts: r8a7794: " Simon Horman
` (6 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add a device node for the L2 cache, and link the CPU node to it.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 9837f90f1718..b48215945241 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -51,6 +51,7 @@
< 937500 1000000>,
< 750000 1000000>,
< 375000 1000000>;
+ next-level-cache = <&L2_CA15>;
};
};
@@ -73,6 +74,12 @@
};
};
+ L2_CA15: cache-controller at 0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
gic: interrupt-controller at f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 14/19] ARM: dts: r8a7794: Add L2 cache-controller node
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (12 preceding siblings ...)
2016-02-25 23:53 ` [PATCH 13/19] ARM: dts: r8a7793: " Simon Horman
@ 2016-02-25 23:53 ` Simon Horman
2016-02-25 23:53 ` [PATCH 15/19] ARM: dts: r8a7794: replace gpio-key, wakeup with wakeup-source property Simon Horman
` (5 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index df0861e84a4b..21a02df3609b 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -40,6 +40,7 @@
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
+ next-level-cache = <&L2_CA7>;
};
cpu1: cpu at 1 {
@@ -47,9 +48,16 @@
compatible = "arm,cortex-a7";
reg = <1>;
clock-frequency = <1000000000>;
+ next-level-cache = <&L2_CA7>;
};
};
+ L2_CA7: cache-controller at 1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
gic: interrupt-controller at f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 15/19] ARM: dts: r8a7794: replace gpio-key, wakeup with wakeup-source property
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (13 preceding siblings ...)
2016-02-25 23:53 ` [PATCH 14/19] ARM: dts: r8a7794: " Simon Horman
@ 2016-02-25 23:53 ` Simon Horman
2016-02-25 23:53 ` [PATCH 16/19] ARM: dts: r8a7794: add EtherAVB clock Simon Horman
` (4 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:53 UTC (permalink / raw)
To: linux-arm-kernel
Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
check for/support the legacy "gpio-key,wakeup" boolean property to
enable gpio buttons as wakeup source, "wakeup-source" is the new
standard binding.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Changelog text from a similar patch by Sudeep Holla.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
---
arch/arm/boot/dts/r8a7793-gose.dts | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index cfe142c2ba38..87e89ec9dd47 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -67,77 +67,77 @@
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW2-1";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW2-2";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW2-3";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "SW2-4";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
key-a {
gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_A>;
label = "SW30";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
key-b {
gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_B>;
label = "SW31";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
key-c {
gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_C>;
label = "SW32";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
key-d {
gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_D>;
label = "SW33";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
key-e {
gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_E>;
label = "SW34";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
key-f {
gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_F>;
label = "SW35";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
key-g {
gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_G>;
label = "SW36";
- gpio-key,wakeup;
+ wakeup-source;
debounce-interval = <20>;
};
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 16/19] ARM: dts: r8a7794: add EtherAVB clock
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (14 preceding siblings ...)
2016-02-25 23:53 ` [PATCH 15/19] ARM: dts: r8a7794: replace gpio-key, wakeup with wakeup-source property Simon Horman
@ 2016-02-25 23:53 ` Simon Horman
2016-02-25 23:53 ` [PATCH 17/19] ARM: dts: r8a7794: add EtherAVB support Simon Horman
` (3 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Add the EtherAVB clock to the R8A7794 device tree.
Based on the commit eaa870b30553 ("ARM: shmobile: r8a7791: add EtherAVB
clock").
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 7 ++++---
include/dt-bindings/clock/r8a7794-clock.h | 1 +
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 21a02df3609b..042440b6dc8c 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1112,13 +1112,14 @@
mstp8_clks: mstp8_clks at e6150990 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
- clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
+ clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
#clock-cells = <1>;
clock-indices = <
- R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
+ R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
+ R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
>;
clock-output-names =
- "vin1", "vin0", "ether";
+ "vin1", "vin0", "etheravb", "ether";
};
mstp9_clks: mstp9_clks at e6150994 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index a7a7e0370968..f843de6bf377 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -84,6 +84,7 @@
/* MSTP8 */
#define R8A7794_CLK_VIN1 10
#define R8A7794_CLK_VIN0 11
+#define R8A7794_CLK_ETHERAVB 12
#define R8A7794_CLK_ETHER 13
/* MSTP9 */
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 17/19] ARM: dts: r8a7794: add EtherAVB support
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (15 preceding siblings ...)
2016-02-25 23:53 ` [PATCH 16/19] ARM: dts: r8a7794: add EtherAVB clock Simon Horman
@ 2016-02-25 23:53 ` Simon Horman
2016-02-25 23:53 ` [PATCH 18/19] ARM: dts: r8a7790: lager: use demuxer for IIC0/I2C0 Simon Horman
` (2 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Define the generic R8A7794 part of the EtherAVB device node.
Based on the commit 46ece349aa54 ("ARM: shmobile: r8a7791: add EtherAVB DT
support").
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 042440b6dc8c..eacb2b291361 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -544,6 +544,18 @@
status = "disabled";
};
+ avb: ethernet at e6800000 {
+ compatible = "renesas,etheravb-r8a7794",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
+ power-domains = <&cpg_clocks>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
/* The memory map in the User's Manual maps the cores to bus numbers */
i2c0: i2c at e6508000 {
compatible = "renesas,i2c-r8a7794";
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 18/19] ARM: dts: r8a7790: lager: use demuxer for IIC0/I2C0
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (16 preceding siblings ...)
2016-02-25 23:53 ` [PATCH 17/19] ARM: dts: r8a7794: add EtherAVB support Simon Horman
@ 2016-02-25 23:53 ` Simon Horman
2016-02-25 23:53 ` [PATCH 19/19] ARM: dts: r8a7790: use fallback etheravb compatibility string Simon Horman
2016-02-29 15:25 ` [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Arnd Bergmann
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Wolfram Sang <wsa+renesas@sang-engineering.com>
Make it possible to select which I2C IP core you want to run on the
EXIO-A connector. This is the reference how to use this feature. Update
the copyright while we are here.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7790-lager.dts | 32 ++++++++++++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index cdc0414f5f07..aa6ca92a9485 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -3,6 +3,7 @@
*
* Copyright (C) 2013-2014 Renesas Solutions Corp.
* Copyright (C) 2014 Cogent Embedded, Inc.
+ * Copyright (C) 2015-2016 Renesas Electronics Corporation
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -49,6 +50,7 @@
aliases {
serial0 = &scif0;
serial1 = &scifa1;
+ i2c8 = "i2cexio";
};
chosen {
@@ -252,6 +254,23 @@
#clock-cells = <0>;
clock-frequency = <148500000>;
};
+
+ /*
+ * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
+ * We use the I2C demuxer, so the desired IP core can be selected at runtime
+ * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
+ * Note: For testing the I2C slave feature, it is convenient to connect this
+ * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
+ * instantiate the slave device at runtime according to the documentation.
+ * You can then communicate with the slave via IIC3.
+ */
+ i2cexio: i2c at 8 {
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&iic0>, <&i2c0>;
+ i2c-bus-name = "i2c-exio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
&du {
@@ -350,6 +369,11 @@
renesas,function = "msiof1";
};
+ i2c0_pins: i2c0 {
+ renesas,groups = "i2c0";
+ renesas,function = "i2c0";
+ };
+
iic0_pins: iic0 {
renesas,groups = "iic0";
renesas,function = "iic0";
@@ -537,10 +561,14 @@
cpu0-supply = <&vdd_dvfs>;
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "i2c-exio";
+};
+
&iic0 {
- status = "okay";
pinctrl-0 = <&iic0_pins>;
- pinctrl-names = "default";
+ pinctrl-names = "i2c-exio";
};
&iic1 {
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 19/19] ARM: dts: r8a7790: use fallback etheravb compatibility string
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (17 preceding siblings ...)
2016-02-25 23:53 ` [PATCH 18/19] ARM: dts: r8a7790: lager: use demuxer for IIC0/I2C0 Simon Horman
@ 2016-02-25 23:53 ` Simon Horman
2016-02-29 15:25 ` [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Arnd Bergmann
19 siblings, 0 replies; 21+ messages in thread
From: Simon Horman @ 2016-02-25 23:53 UTC (permalink / raw)
To: linux-arm-kernel
Use recently added fallback compatibility string in r8a7790 device tree.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7790.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index ba4c2530d79f..38b706399a6b 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -773,7 +773,8 @@
};
avb: ethernet at e6800000 {
- compatible = "renesas,etheravb-r8a7790";
+ compatible = "renesas,etheravb-r8a7790",
+ "renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 21+ messages in thread* [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6
2016-02-25 23:53 [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.6 Simon Horman
` (18 preceding siblings ...)
2016-02-25 23:53 ` [PATCH 19/19] ARM: dts: r8a7790: use fallback etheravb compatibility string Simon Horman
@ 2016-02-29 15:25 ` Arnd Bergmann
19 siblings, 0 replies; 21+ messages in thread
From: Arnd Bergmann @ 2016-02-29 15:25 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 26 February 2016 08:53:07 Simon Horman wrote:
> Second Round of Renesas ARM Based SoC DT Updates for v4.6
>
> * Add L2 cache-controller nodes to r8a779[0134] and r8a73a4
> * Add etheravb support to r8a7794
> * Correct JP3 jumper description on Porter
> * Enable thermal zone on r8a779[013]
> * Replace gpio-key, wakeup with wakeup-source property on r8a7794
> * Use demuxer for IIC0/I2C0 on lager
> * Use fallback etheravb, pci and pcie compatibility strings as appropriate
>
>
Merged into next/dt, thanks!
Arnd
^ permalink raw reply [flat|nested] 21+ messages in thread