* [PATCH v5 0/3] Add i.MX943 basic dts support
@ 2025-04-10 6:28 Jacky Bai
2025-04-10 6:28 ` [PATCH v5 1/3] dt-bindings: arm: fsl: add i.MX943 EVK board Jacky Bai
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Jacky Bai @ 2025-04-10 6:28 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, shawnguo, s.hauer
Cc: kernel, festevam, devicetree, imx, linux-arm-kernel, aisheng.dong,
peng.fan, frank.li
i.MX943 is the first SoC of the i.MX94 family, all the SoCs
of this family are pin to pin compatible with only several
peripherals differance.
For i.MX943 device tree support, we split the dtsi into two
part, one for the common dtsi that shared for the i.MX94 family,
and an i.MX943 specific part.
Jacky Bai (3):
dt-bindings: arm: fsl: add i.MX943 EVK board
arm64: dts: freescale: Add basic dtsi for imx943
arm64: dts: freescale: Add minimal dts support for imx943 evk
.../devicetree/bindings/arm/fsl.yaml | 6 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx94-clock.h | 195 ++
arch/arm64/boot/dts/freescale/imx94-pinfunc.h | 1570 +++++++++++++++++
arch/arm64/boot/dts/freescale/imx94-power.h | 41 +
arch/arm64/boot/dts/freescale/imx94.dtsi | 1138 ++++++++++++
arch/arm64/boot/dts/freescale/imx943-evk.dts | 195 ++
arch/arm64/boot/dts/freescale/imx943.dtsi | 148 ++
8 files changed, 3294 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx94-clock.h
create mode 100644 arch/arm64/boot/dts/freescale/imx94-pinfunc.h
create mode 100644 arch/arm64/boot/dts/freescale/imx94-power.h
create mode 100644 arch/arm64/boot/dts/freescale/imx94.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx943-evk.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx943.dtsi
--
2.34.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v5 1/3] dt-bindings: arm: fsl: add i.MX943 EVK board 2025-04-10 6:28 [PATCH v5 0/3] Add i.MX943 basic dts support Jacky Bai @ 2025-04-10 6:28 ` Jacky Bai 2025-04-10 6:28 ` [PATCH v5 3/3] arm64: dts: freescale: Add minimal dts support for imx943 evk Jacky Bai [not found] ` <20250410062826.3344545-3-ping.bai@nxp.com> 2 siblings, 0 replies; 8+ messages in thread From: Jacky Bai @ 2025-04-10 6:28 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer Cc: kernel, festevam, devicetree, imx, linux-arm-kernel, aisheng.dong, peng.fan, frank.li Add DT compatible string for NXP i.MX943 EVK board. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- - v5 changes: - no - v4 changes: - no --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 1b90870958a2..873f9eb25cda 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1347,6 +1347,12 @@ properties: - fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board - const: fsl,imx93 + - description: i.MX94 based Boards + items: + - enum: + - fsl,imx943-evk # i.MX943 EVK Board + - const: fsl,imx94 + - description: i.MX95 based Boards items: - enum: -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v5 3/3] arm64: dts: freescale: Add minimal dts support for imx943 evk 2025-04-10 6:28 [PATCH v5 0/3] Add i.MX943 basic dts support Jacky Bai 2025-04-10 6:28 ` [PATCH v5 1/3] dt-bindings: arm: fsl: add i.MX943 EVK board Jacky Bai @ 2025-04-10 6:28 ` Jacky Bai 2025-04-10 6:46 ` Alexander Stein [not found] ` <20250410062826.3344545-3-ping.bai@nxp.com> 2 siblings, 1 reply; 8+ messages in thread From: Jacky Bai @ 2025-04-10 6:28 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer Cc: kernel, festevam, devicetree, imx, linux-arm-kernel, aisheng.dong, peng.fan, frank.li Add the minimal board dts support for i.MX943 EVK. Only the console uart, SD & eMMC are enabled for linux basic boot. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> --- - v5 changes: - remove the unused and not documented 'fsl,cd-gpio-wakeup-disable' property from usdhc node. - v4 changes: - no - v3 changes: - no - v2 changes: - newly added for board dts --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx943-evk.dts | 195 +++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx943-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b6d3fe26d621..2fe86fc6d73a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -303,6 +303,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts new file mode 100644 index 000000000000..b0bb08bb67d5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024-2025 NXP + */ + +/dts-v1/; + +#include "imx943.dtsi" + +/ { + compatible = "fsl,imx943-evk", "fsl,imx94"; + model = "NXP i.MX943 EVK board"; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_SD2_3V3"; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0x0 0x80000000>; + device_type = "memory"; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX94_PAD_UART1_TXD__LPUART1_TX 0x31e + IMX94_PAD_UART1_RXD__LPUART1_RX 0x31e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX94_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX94_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX94_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX94_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX94_PAD_SD2_CD_B__GPIO4_IO20 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_reg_usdhc2_vmmc: usdhc2regvmmcgrp { + fsl,pins = < + IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e + >; + }; +}; + +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + bus-width = <4>; + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v5 3/3] arm64: dts: freescale: Add minimal dts support for imx943 evk 2025-04-10 6:28 ` [PATCH v5 3/3] arm64: dts: freescale: Add minimal dts support for imx943 evk Jacky Bai @ 2025-04-10 6:46 ` Alexander Stein 2025-04-10 7:48 ` Jacky Bai 0 siblings, 1 reply; 8+ messages in thread From: Alexander Stein @ 2025-04-10 6:46 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, linux-arm-kernel Cc: kernel, festevam, devicetree, imx, linux-arm-kernel, aisheng.dong, peng.fan, frank.li, Jacky Bai Hi, Am Donnerstag, 10. April 2025, 08:28:26 CEST schrieb Jacky Bai: > Add the minimal board dts support for i.MX943 EVK. Only the > console uart, SD & eMMC are enabled for linux basic boot. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > Reviewed-by: Frank Li <Frank.Li@nxp.com> > --- > - v5 changes: > - remove the unused and not documented 'fsl,cd-gpio-wakeup-disable' > property from usdhc node. > > - v4 changes: > - no > > - v3 changes: > - no > > - v2 changes: > - newly added for board dts > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > arch/arm64/boot/dts/freescale/imx943-evk.dts | 195 +++++++++++++++++++ > 2 files changed, 196 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx943-evk.dts > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index b6d3fe26d621..2fe86fc6d73a 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -303,6 +303,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb > dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb > dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb Uh, please sort the entries alphabetically, thus imx94 goes before imx95. > > imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo > > diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts > new file mode 100644 > index 000000000000..b0bb08bb67d5 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts > @@ -0,0 +1,195 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2024-2025 NXP > + */ > + > +/dts-v1/; > + > +#include "imx943.dtsi" > + > +/ { > + compatible = "fsl,imx943-evk", "fsl,imx94"; > + model = "NXP i.MX943 EVK board"; > + > + aliases { > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > + serial0 = &lpuart1; > + }; > + > + chosen { > + stdout-path = &lpuart1; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2 { > + compatible = "regulator-fixed"; > + off-on-delay-us = <12000>; > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > + pinctrl-names = "default"; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + regulator-name = "VDD_SD2_3V3"; > + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reserved-memory { > + ranges; > + #address-cells = <2>; > + #size-cells = <2>; > + > + linux,cma { > + compatible = "shared-dma-pool"; > + alloc-ranges = <0 0x80000000 0 0x7f000000>; > + reusable; > + size = <0 0x10000000>; > + linux,cma-default; > + }; > + }; > + > + memory@80000000 { > + reg = <0x0 0x80000000 0x0 0x80000000>; > + device_type = "memory"; > + }; > +}; > + > +&lpuart1 { > + pinctrl-0 = <&pinctrl_uart1>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&scmi_iomuxc { > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + IMX94_PAD_UART1_TXD__LPUART1_TX 0x31e > + IMX94_PAD_UART1_RXD__LPUART1_RX 0x31e > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > + fsl,pins = < > + IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e > + IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e > + IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e > + IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e > + IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e > + IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e > + IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e > + IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e > + IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e > + IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e > + IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > + fsl,pins = < > + IMX94_PAD_SD1_CLK__USDHC1_CLK 0x15fe > + IMX94_PAD_SD1_CMD__USDHC1_CMD 0x13fe > + IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe > + IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe > + IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe > + IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe > + IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe > + IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe > + IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe > + IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe > + IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e > + IMX94_PAD_SD1_CMD__USDHC1_CMD 0x138e > + IMX94_PAD_SD1_DATA0__USDHC1_DATA0 0x138e > + IMX94_PAD_SD1_DATA1__USDHC1_DATA1 0x138e > + IMX94_PAD_SD1_DATA2__USDHC1_DATA2 0x138e > + IMX94_PAD_SD1_DATA3__USDHC1_DATA3 0x138e > + IMX94_PAD_SD1_DATA4__USDHC1_DATA4 0x138e > + IMX94_PAD_SD1_DATA5__USDHC1_DATA5 0x138e > + IMX94_PAD_SD1_DATA6__USDHC1_DATA6 0x138e > + IMX94_PAD_SD1_DATA7__USDHC1_DATA7 0x138e > + IMX94_PAD_SD1_STROBE__USDHC1_STROBE 0x158e > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > + fsl,pins = < > + IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e > + IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e > + IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e > + IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e > + IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e > + IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e > + IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > + fsl,pins = < > + IMX94_PAD_SD2_CLK__USDHC2_CLK 0x15fe > + IMX94_PAD_SD2_CMD__USDHC2_CMD 0x13fe > + IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe > + IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe > + IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe > + IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe > + IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2gpiogrp { > + fsl,pins = < > + IMX94_PAD_SD2_CD_B__GPIO4_IO20 0x31e > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + IMX94_PAD_SD2_CLK__USDHC2_CLK 0x158e > + IMX94_PAD_SD2_CMD__USDHC2_CMD 0x138e > + IMX94_PAD_SD2_DATA0__USDHC2_DATA0 0x138e > + IMX94_PAD_SD2_DATA1__USDHC2_DATA1 0x138e > + IMX94_PAD_SD2_DATA2__USDHC2_DATA2 0x138e > + IMX94_PAD_SD2_DATA3__USDHC2_DATA3 0x138e > + IMX94_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_reg_usdhc2_vmmc: usdhc2regvmmcgrp { > + fsl,pins = < > + IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e > + >; > + }; > +}; > + > +&usdhc1 { > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + pinctrl-3 = <&pinctrl_usdhc1>; > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; Is the sleep pinctrl necessary if it is the same as 'default'? > + bus-width = <8>; > + non-removable; > + no-sdio; > + no-sd; > + status = "okay"; > +}; > + > +&usdhc2 { > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; Same here. > + bus-width = <4>; > + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; > + vmmc-supply = <®_usdhc2_vmmc>; This is probably also 'no-mmc', no? Maybe even 'no-sdio'. Best regards, Alexander > + status = "okay"; > +}; > + > +&wdog3 { > + fsl,ext-reset-output; > + status = "okay"; > +}; > -- TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018 Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider http://www.tq-group.com/ ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v5 3/3] arm64: dts: freescale: Add minimal dts support for imx943 evk 2025-04-10 6:46 ` Alexander Stein @ 2025-04-10 7:48 ` Jacky Bai 0 siblings, 0 replies; 8+ messages in thread From: Jacky Bai @ 2025-04-10 7:48 UTC (permalink / raw) To: Alexander Stein, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, linux-arm-kernel@lists.infradead.org Cc: kernel@pengutronix.de, festevam@gmail.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Aisheng Dong, Peng Fan, Frank Li > Subject: Re: [PATCH v5 3/3] arm64: dts: freescale: Add minimal dts support for > imx943 evk > > Hi, > > Am Donnerstag, 10. April 2025, 08:28:26 CEST schrieb Jacky Bai: > > Add the minimal board dts support for i.MX943 EVK. Only the console > > uart, SD & eMMC are enabled for linux basic boot. > > > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > > Reviewed-by: Frank Li <Frank.Li@nxp.com> > > --- > > - v5 changes: > > - remove the unused and not documented 'fsl,cd-gpio-wakeup-disable' > > property from usdhc node. > > > > - v4 changes: > > - no > > > > - v3 changes: > > - no > > > > - v2 changes: > > - newly added for board dts > > --- > > arch/arm64/boot/dts/freescale/Makefile | 1 + > > arch/arm64/boot/dts/freescale/imx943-evk.dts | 195 > > +++++++++++++++++++ > > 2 files changed, 196 insertions(+) > > create mode 100644 arch/arm64/boot/dts/freescale/imx943-evk.dts > > > > diff --git a/arch/arm64/boot/dts/freescale/Makefile > > b/arch/arm64/boot/dts/freescale/Makefile > > index b6d3fe26d621..2fe86fc6d73a 100644 > > --- a/arch/arm64/boot/dts/freescale/Makefile > > +++ b/arch/arm64/boot/dts/freescale/Makefile > > @@ -303,6 +303,7 @@ dtb-$(CONFIG_ARCH_MXC) += > > imx93-tqma9352-mba93xxla.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb > > +dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb > > Uh, please sort the entries alphabetically, thus imx94 goes before imx95. > Ok > > > > imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb > imx8mm-kontron-dl.dtbo > > > > diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts > > b/arch/arm64/boot/dts/freescale/imx943-evk.dts > > new file mode 100644 > > index 000000000000..b0bb08bb67d5 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts ... > > +&usdhc1 { > > + pinctrl-0 = <&pinctrl_usdhc1>; > > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > > + pinctrl-3 = <&pinctrl_usdhc1>; > > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; > > Is the sleep pinctrl necessary if it is the same as 'default'? > Currently not necessary, I can drop it. > > + bus-width = <8>; > > + non-removable; > > + no-sdio; > > + no-sd; > > + status = "okay"; > > +}; > > + > > +&usdhc2 { > > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > > + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; > > Same here. > > > + bus-width = <4>; > > + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; > > + vmmc-supply = <®_usdhc2_vmmc>; > > This is probably also 'no-mmc', no? Maybe even 'no-sdio'. > This slot is used for SD card, will update it as you suggested in next version. Thx. BR > Best regards, > Alexander > > > + status = "okay"; > > +}; > > + > > +&wdog3 { > > + fsl,ext-reset-output; > > + status = "okay"; > > +}; > > > > > -- > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany > Amtsgericht München, HRB 105018 > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider > http://www.tq-g/ > roup.com%2F&data=05%7C02%7Cping.bai%40nxp.com%7Cb24c8157d23c4d95 > b9a508dd77fb70f0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63 > 8798643991989017%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRyd > WUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D% > 3D%7C0%7C%7C%7C&sdata=wtlbuuuZBHYRvl7SF0GGH5CPI2oFGSURWSG6ZZ4 > EBqg%3D&reserved=0 > ^ permalink raw reply [flat|nested] 8+ messages in thread
[parent not found: <20250410062826.3344545-3-ping.bai@nxp.com>]
* Re: [PATCH v5 2/3] arm64: dts: freescale: Add basic dtsi for imx943 [not found] ` <20250410062826.3344545-3-ping.bai@nxp.com> @ 2025-04-10 15:41 ` Frank Li 2025-04-11 1:46 ` Jacky Bai 0 siblings, 1 reply; 8+ messages in thread From: Frank Li @ 2025-04-10 15:41 UTC (permalink / raw) To: Jacky Bai Cc: robh, krzk+dt, conor+dt, shawnguo, s.hauer, kernel, festevam, devicetree, imx, linux-arm-kernel, aisheng.dong, peng.fan On Thu, Apr 10, 2025 at 02:28:25PM +0800, Jacky Bai wrote: > Add the minimal dtsi support for i.MX943. i.MX943 is the > first SoC of i.MX94 Family, create a common dtsi for the > whole i.MX94 family, and the specific dtsi part for i.MX943. > > The clock, power domain and perf index need to be used by > the device nodes for resource reference, add them along > with the dtsi support. Please wrap at 75 char to maxium use sceen width. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > --- > - v5 changes: > - remove the err irq of edma node as the err irq support in driver is not > ready. We can add it back when the driver is ready. No impact for current > edma support. > > - v4 changes: > - reorder the cpu node compatible string property as suggested by Frank > > - v3 changes: > - remove the blank line > - add PAD config macro define as suggested by Frank Li > - update the device nodes compatible strings for imx94 as suggested by Krzysztof > > - v2 changes: > - remove the unnecessary macro define in clock header as suggested by Krzysztof > - split the dtsi into imx94.dtsi and imx943.dtsi > - use low case in the pinfunc header as Frank suggested > - reorder the device nodes and properties > --- > arch/arm64/boot/dts/freescale/imx94-clock.h | 195 ++ > arch/arm64/boot/dts/freescale/imx94-pinfunc.h | 1570 +++++++++++++++++ > arch/arm64/boot/dts/freescale/imx94-power.h | 41 + > arch/arm64/boot/dts/freescale/imx94.dtsi | 1138 ++++++++++++ > arch/arm64/boot/dts/freescale/imx943.dtsi | 148 ++ > 5 files changed, 3092 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx94-clock.h > create mode 100644 arch/arm64/boot/dts/freescale/imx94-pinfunc.h > create mode 100644 arch/arm64/boot/dts/freescale/imx94-power.h > create mode 100644 arch/arm64/boot/dts/freescale/imx94.dtsi > create mode 100644 arch/arm64/boot/dts/freescale/imx943.dtsi > ... > + #size-cells = <1>; > + > + edma2: dma-controller@42000000 { > + compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; > + reg = <0x42000000 0x210000>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "dma"; > + #dma-cells = <3>; > + dma-channels = <64>; > + interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer 1>, <&a55_irqsteer 2>, > + <&a55_irqsteer 3>, <&a55_irqsteer 4>, <&a55_irqsteer 5>, need align previous line "<" > + <&a55_irqsteer 6>, <&a55_irqsteer 7>, <&a55_irqsteer 8>, Does it work by use interrupt-parent = <&a55_irqsteer>; interrupts = <0>, <1> ... if it works, it will reduce many &a55_irqsteer. Frank > + <&a55_irqsteer 9>, <&a55_irqsteer 10>, <&a55_irqsteer 11>, > + <&a55_irqsteer 12>, <&a55_irqsteer 13>, <&a55_irqsteer 14>, > + <&a55_irqsteer 15>, <&a55_irqsteer 16>, <&a55_irqsteer 17>, > + <&a55_irqsteer 18>, <&a55_irqsteer 19>, <&a55_irqsteer 20>, > + <&a55_irqsteer 21>, <&a55_irqsteer 22>, <&a55_irqsteer 23>, > + <&a55_irqsteer 24>, <&a55_irqsteer 25>, <&a55_irqsteer 26>, > + <&a55_irqsteer 27>, <&a55_irqsteer 28>, <&a55_irqsteer 29>, > + <&a55_irqsteer 30>, <&a55_irqsteer 31>, <&a55_irqsteer 64>, > + <&a55_irqsteer 65>, <&a55_irqsteer 66>, <&a55_irqsteer 67>, > + <&a55_irqsteer 68>, <&a55_irqsteer 69>, <&a55_irqsteer 70>, > + <&a55_irqsteer 71>, <&a55_irqsteer 72>, <&a55_irqsteer 73>, > + <&a55_irqsteer 74>, <&a55_irqsteer 75>, <&a55_irqsteer 76>, > + <&a55_irqsteer 77>, <&a55_irqsteer 78>, <&a55_irqsteer 79>, > + <&a55_irqsteer 80>, <&a55_irqsteer 81>, <&a55_irqsteer 82>, > + <&a55_irqsteer 83>, <&a55_irqsteer 84>, <&a55_irqsteer 85>, > + <&a55_irqsteer 86>, <&a55_irqsteer 87>, <&a55_irqsteer 88>, > + <&a55_irqsteer 89>, <&a55_irqsteer 90>, <&a55_irqsteer 91>, > + <&a55_irqsteer 92>, <&a55_irqsteer 93>, <&a55_irqsteer 94>, > + <&a55_irqsteer 95>; > + }; > + > + mu10: mailbox@42430000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x42430000 0x10000>; > + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + i3c2: i3c@42520000 { > + compatible = "silvaco,i3c-master-v1"; > + reg = <0x42520000 0x10000>; > + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <3>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > + <&scmi_clk IMX94_CLK_I3C2SLOW>, > + <&dummy>; > + clock-names = "pclk", "fast_clk", "slow_clk"; > + status = "disabled"; > + }; > + > + lpi2c3: i2c@42530000 { > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x42530000 0x10000>; > + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPI2C3>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma2 5 0 0>, <&edma2 6 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpi2c4: i2c@42540000 { > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x42540000 0x10000>; > + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPI2C4>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma4 4 0 0>, <&edma4 5 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpspi3: spi@42550000 { > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > + reg = <0x42550000 0x10000>; > + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPSPI3>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma2 7 0 0>, <&edma2 8 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpspi4: spi@42560000 { > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > + reg = <0x42560000 0x10000>; > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPSPI4>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma4 6 0 0>, <&edma4 7 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpuart3: serial@42570000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x42570000 0x1000>; > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART3>; > + clock-names = "ipg"; > + dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 9 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + lpuart4: serial@42580000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x42580000 0x1000>; > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART4>; > + clock-names = "ipg"; > + dmas = <&edma4 10 0 FSL_EDMA_RX>, <&edma4 9 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + lpuart5: serial@42590000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x42590000 0x1000>; > + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART5>; > + clock-names = "ipg"; > + dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 11 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + lpuart6: serial@425a0000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x425a0000 0x1000>; > + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART6>; > + clock-names = "ipg"; > + dmas = <&edma4 12 0 FSL_EDMA_RX>, <&edma4 11 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + flexcan2: can@425b0000 { > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > + reg = <0x425b0000 0x10000>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > + <&scmi_clk IMX94_CLK_CAN2>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN2>; > + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; > + assigned-clock-rates = <80000000>; > + fsl,clk-source = /bits/ 8 <0>; > + status = "disabled"; > + }; > + > + flexcan3: can@425e0000 { > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > + reg = <0x425e0000 0x10000>; > + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > + <&scmi_clk IMX94_CLK_CAN3>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN3>; > + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; > + assigned-clock-rates = <80000000>; > + fsl,clk-source = /bits/ 8 <0>; > + status = "disabled"; > + }; > + > + flexcan4: can@425f0000 { > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > + reg = <0x425f0000 0x10000>; > + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > + <&scmi_clk IMX94_CLK_CAN4>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN4>; > + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; > + assigned-clock-rates = <80000000>; > + fsl,clk-source = /bits/ 8 <0>; > + status = "disabled"; > + }; > + > + flexcan5: can@42600000 { > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > + reg = <0x42600000 0x10000>; > + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > + <&scmi_clk IMX94_CLK_CAN5>; > + clock-names = "ipg", "per"; > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN5>; > + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; > + assigned-clock-rates = <80000000>; > + fsl,clk-source = /bits/ 8 <0>; > + status = "disabled"; > + }; > + > + sai2: sai@42650000 { > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > + reg = <0x42650000 0x10000>; > + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, > + <&scmi_clk IMX94_CLK_SAI2>, <&dummy>, <&dummy>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma2 30 0 FSL_EDMA_RX>, <&edma2 29 0 0>; > + dma-names = "rx", "tx"; > + #sound-dai-cells = <0>; > + status = "disabled"; > + }; > + > + sai3: sai@42660000 { > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > + reg = <0x42660000 0x10000>; > + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, > + <&scmi_clk IMX94_CLK_SAI3>, <&dummy>, <&dummy>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma2 32 0 FSL_EDMA_RX>, <&edma2 31 0 0>; > + dma-names = "rx", "tx"; > + #sound-dai-cells = <0>; > + status = "disabled"; > + }; > + > + sai4: sai@42670000 { > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > + reg = <0x42670000 0x10000>; > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, > + <&scmi_clk IMX94_CLK_SAI4>, <&dummy>, <&dummy>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma2 36 0 FSL_EDMA_RX>, <&edma2 35 0 0>; > + dma-names = "rx", "tx"; > + #sound-dai-cells = <0>; > + status = "disabled"; > + }; > + > + lpuart7: serial@42690000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x42690000 0x1000>; > + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART7>; > + clock-names = "ipg"; > + dmas = <&edma2 46 0 FSL_EDMA_RX>, <&edma2 45 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + lpuart8: serial@426a0000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x426a0000 0x1000>; > + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART8>; > + clock-names = "ipg"; > + dmas = <&edma4 39 0 FSL_EDMA_RX>, <&edma4 38 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + lpi2c5: i2c@426b0000 { > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x426b0000 0x10000>; > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPI2C5>, > + <&scmi_clk IMX94_CLK_BUSAON>; > + clock-names = "per", "ipg"; > + dmas = <&edma2 37 0 0>, <&edma2 38 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpi2c6: i2c@426c0000 { > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x426c0000 0x10000>; > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPI2C6>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma4 30 0 0>, <&edma4 31 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpi2c7: i2c@426d0000 { > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x426d0000 0x10000>; > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPI2C7>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma2 39 0 0>, <&edma2 40 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpi2c8: i2c@426e0000 { > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x426e0000 0x10000>; > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPI2C8>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma4 32 0 0>, <&edma4 33 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpspi5: spi@426f0000 { > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > + reg = <0x426f0000 0x10000>; > + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPSPI5>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma2 41 0 0>, <&edma2 42 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpspi6: spi@42700000 { > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > + reg = <0x42700000 0x10000>; > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPSPI6>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma4 34 0 0>, <&edma4 35 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpspi7: spi@42710000 { > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > + reg = <0x42710000 0x10000>; > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPSPI7>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma2 43 0 0>, <&edma2 44 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpspi8: spi@42720000 { > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > + reg = <0x42720000 0x10000>; > + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPSPI8>, > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "per", "ipg"; > + dmas = <&edma4 36 0 0>, <&edma4 37 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + mu11: mailbox@42730000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x42730000 0x10000>; > + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + edma4: dma-controller@42df0000 { > + compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; > + reg = <0x42df0000 0x210000>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + clock-names = "dma"; > + #dma-cells = <3>; > + dma-channels = <64>; > + interrupts-extended = <&a55_irqsteer 128>, <&a55_irqsteer 129>, > + <&a55_irqsteer 130>, <&a55_irqsteer 131>, > + <&a55_irqsteer 132>, <&a55_irqsteer 133>, > + <&a55_irqsteer 134>, <&a55_irqsteer 135>, > + <&a55_irqsteer 136>, <&a55_irqsteer 137>, > + <&a55_irqsteer 138>, <&a55_irqsteer 139>, > + <&a55_irqsteer 140>, <&a55_irqsteer 141>, > + <&a55_irqsteer 142>, <&a55_irqsteer 143>, > + <&a55_irqsteer 144>, <&a55_irqsteer 145>, > + <&a55_irqsteer 146>, <&a55_irqsteer 147>, > + <&a55_irqsteer 148>, <&a55_irqsteer 149>, > + <&a55_irqsteer 150>, <&a55_irqsteer 151>, > + <&a55_irqsteer 152>, <&a55_irqsteer 153>, > + <&a55_irqsteer 154>, <&a55_irqsteer 155>, > + <&a55_irqsteer 156>, <&a55_irqsteer 157>, > + <&a55_irqsteer 158>, <&a55_irqsteer 159>, > + <&a55_irqsteer 192>, <&a55_irqsteer 193>, > + <&a55_irqsteer 194>, <&a55_irqsteer 195>, > + <&a55_irqsteer 196>, <&a55_irqsteer 197>, > + <&a55_irqsteer 198>, <&a55_irqsteer 199>, > + <&a55_irqsteer 200>, <&a55_irqsteer 201>, > + <&a55_irqsteer 202>, <&a55_irqsteer 203>, > + <&a55_irqsteer 204>, <&a55_irqsteer 205>, > + <&a55_irqsteer 206>, <&a55_irqsteer 207>, > + <&a55_irqsteer 208>, <&a55_irqsteer 209>, > + <&a55_irqsteer 210>, <&a55_irqsteer 211>, > + <&a55_irqsteer 212>, <&a55_irqsteer 213>, > + <&a55_irqsteer 214>, <&a55_irqsteer 215>, > + <&a55_irqsteer 216>, <&a55_irqsteer 217>, > + <&a55_irqsteer 218>, <&a55_irqsteer 219>, > + <&a55_irqsteer 220>, <&a55_irqsteer 221>, > + <&a55_irqsteer 222>, <&a55_irqsteer 223>; > + }; > + }; > + > + aips3: bus@42800000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + reg = <0 0x42800000 0 0x800000>; > + ranges = <0x42800000 0x0 0x42800000 0x800000>, > + <0x28000000 0x0 0x28000000 0x1000000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + usdhc1: mmc@42850000 { > + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; > + reg = <0x42850000 0x10000>; > + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > + <&scmi_clk IMX94_CLK_WAKEUPAXI>, > + <&scmi_clk IMX94_CLK_USDHC1>; > + clock-names = "ipg", "ahb", "per"; > + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC1>; > + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; > + assigned-clock-rates = <400000000>; > + bus-width = <8>; > + fsl,tuning-start-tap = <1>; > + fsl,tuning-step = <2>; > + status = "disabled"; > + }; > + > + usdhc2: mmc@42860000 { > + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; > + reg = <0x42860000 0x10000>; > + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > + <&scmi_clk IMX94_CLK_WAKEUPAXI>, > + <&scmi_clk IMX94_CLK_USDHC2>; > + clock-names = "ipg", "ahb", "per"; > + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC2>; > + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; > + assigned-clock-rates = <200000000>; > + bus-width = <4>; > + fsl,tuning-start-tap = <1>; > + fsl,tuning-step = <2>; > + status = "disabled"; > + }; > + > + usdhc3: mmc@42880000 { > + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; > + reg = <0x42880000 0x10000>; > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > + <&scmi_clk IMX94_CLK_WAKEUPAXI>, > + <&scmi_clk IMX94_CLK_USDHC3>; > + clock-names = "ipg", "ahb", "per"; > + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC3>; > + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; > + assigned-clock-rates = <200000000>; > + bus-width = <4>; > + fsl,tuning-start-tap = <1>; > + fsl,tuning-step = <2>; > + status = "disabled"; > + }; > + > + lpuart9: serial@42a50000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x42a50000 0x1000>; > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART10>; > + clock-names = "ipg"; > + dmas = <&edma2 51 0 FSL_EDMA_RX>, <&edma2 50 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + lpuart10: serial@42a60000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x42a60000 0x1000>; > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART10>; > + clock-names = "ipg"; > + dmas = <&edma4 47 0 FSL_EDMA_RX>, <&edma4 46 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + lpuart11: serial@42a70000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x42a70000 0x1000>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART11>; > + clock-names = "ipg"; > + dmas = <&edma2 53 0 FSL_EDMA_RX>, <&edma2 52 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + lpuart12: serial@42a80000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x42a80000 0x1000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART12>; > + clock-names = "ipg"; > + dmas = <&edma4 49 0 FSL_EDMA_RX>, <&edma4 48 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + mu12: mailbox@42ac0000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x42ac0000 0x10000>; > + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + mu13: mailbox@42ae0000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x42ae0000 0x10000>; > + interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + mu14: mailbox@42b00000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x42b00000 0x10000>; > + interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + mu15: mailbox@42b20000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x42b20000 0x10000>; > + interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + mu16: mailbox@42b40000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x42b40000 0x10000>; > + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + mu17: mailbox@42b60000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x42b60000 0x10000>; > + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + }; > + > + gpio2: gpio@43810000 { > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > + reg = <0x0 0x43810000 0x0 0x1000>; > + #interrupt-cells = <2>; > + interrupt-controller; > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&scmi_iomuxc 0 4 32>; > + }; > + > + gpio3: gpio@43820000 { > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > + reg = <0x0 0x43820000 0x0 0x1000>; > + #interrupt-cells = <2>; > + interrupt-controller; > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&scmi_iomuxc 0 36 26>; > + }; > + > + gpio4: gpio@43840000 { > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > + reg = <0x0 0x43840000 0x0 0x1000>; > + #interrupt-cells = <2>; > + interrupt-controller; > + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&scmi_iomuxc 0 62 4>, <&scmi_iomuxc 4 0 4>, > + <&scmi_iomuxc 8 140 12>, <&scmi_iomuxc 20 164 12>; > + }; > + > + gpio5: gpio@43850000 { > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > + reg = <0x0 0x43850000 0x0 0x1000>; > + #interrupt-cells = <2>; > + interrupt-controller; > + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&scmi_iomuxc 0 108 32>; > + }; > + > + gpio6: gpio@43860000 { > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > + reg = <0x0 0x43860000 0x0 0x1000>; > + #interrupt-cells = <2>; > + interrupt-controller; > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&scmi_iomuxc 0 66 32>; > + }; > + > + gpio7: gpio@43870000 { > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > + reg = <0x0 0x43870000 0x0 0x1000>; > + #interrupt-cells = <2>; > + interrupt-controller; > + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; > + #gpio-cells = <2>; > + gpio-controller; > + gpio-ranges = <&scmi_iomuxc 0 98 10>, <&scmi_iomuxc 16 152 12>; > + }; > + > + aips1: bus@44000000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + reg = <0x0 0x44000000 0x0 0x800000>; > + ranges = <0x44000000 0x0 0x44000000 0x800000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + edma1: dma-controller@44000000 { > + compatible = "fsl,imx94-edma3", "fsl,imx93-edma3"; > + reg = <0x44000000 0x210000>; > + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > + clock-names = "dma"; > + #dma-cells = <3>; > + dma-channels = <32>; > + }; > + > + mu1: mailbox@44220000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x44220000 0x10000>; > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + system_counter: timer@44290000 { > + compatible = "nxp,imx94-sysctr-timer", "nxp,imx95-sysctr-timer"; > + reg = <0x44290000 0x30000>; > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc_24m>; > + clock-names = "per"; > + nxp,no-divider; > + }; > + > + tpm1: pwm@44310000 { > + compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; > + reg = <0x44310000 0x1000>; > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + tpm2: pwm@44320000 { > + compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; > + reg = <0x44320000 0x1000>; > + clocks = <&scmi_clk IMX94_CLK_TPM2>; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + > + i3c1: i3c@44330000 { > + compatible = "silvaco,i3c-master-v1"; > + reg = <0x44330000 0x10000>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <3>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_BUSAON>, > + <&scmi_clk IMX94_CLK_I3C1SLOW>, > + <&dummy>; > + clock-names = "pclk", "fast_clk", "slow_clk"; > + status = "disabled"; > + }; > + > + lpi2c1: i2c@44340000 { > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x44340000 0x10000>; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPI2C1>, > + <&scmi_clk IMX94_CLK_BUSAON>; > + clock-names = "per", "ipg"; > + dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpi2c2: i2c@44350000 { > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x44350000 0x10000>; > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPI2C2>, > + <&scmi_clk IMX94_CLK_BUSAON>; > + clock-names = "per", "ipg"; > + dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpspi1: spi@44360000 { > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > + reg = <0x44360000 0x10000>; > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPSPI2>, > + <&scmi_clk IMX94_CLK_BUSAON>; > + clock-names = "per", "ipg"; > + dmas = <&edma1 16 0 0>, <&edma1 17 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpspi2: spi@44370000 { > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > + reg = <0x44370000 0x10000>; > + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&scmi_clk IMX94_CLK_LPSPI2>, > + <&scmi_clk IMX94_CLK_BUSAON>; > + clock-names = "per", "ipg"; > + dmas = <&edma1 18 0 0>, <&edma1 19 0 FSL_EDMA_RX>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + lpuart1: serial@44380000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x44380000 0x1000>; > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART1>; > + clock-names = "ipg"; > + dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + lpuart2: serial@44390000 { > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > + "fsl,imx7ulp-lpuart"; > + reg = <0x44390000 0x1000>; > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_LPUART2>; > + clock-names = "ipg"; > + dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + flexcan1: can@443a0000 { > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > + reg = <0x443a0000 0x10000>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + sai1: sai@443b0000 { > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > + reg = <0x443b0000 0x10000>; > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSAON>, <&dummy>, > + <&scmi_clk IMX94_CLK_SAI1>, <&dummy>, > + <&dummy>, <&dummy>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; > + dma-names = "rx", "tx"; > + #sound-dai-cells = <0>; > + status = "disabled"; > + }; > + > + adc1: adc@44530000 { > + compatible = "nxp,imx94-adc", "nxp,imx93-adc"; > + reg = <0x44530000 0x10000>; > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_ADC>; > + clock-names = "ipg"; > + #io-channel-cells = <1>; > + status = "disabled"; > + }; > + > + mu2: mailbox@445b0000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x445b0000 0x1000>; > + ranges; > + interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <1>; > + #mbox-cells = <2>; > + > + sram0: sram@445b1000 { > + compatible = "mmio-sram"; > + reg = <0x445b1000 0x400>; > + ranges = <0x0 0x445b1000 0x400>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + scmi_buf0: scmi-sram-section@0 { > + compatible = "arm,scmi-shmem"; > + reg = <0x0 0x80>; > + }; > + > + scmi_buf1: scmi-sram-section@80 { > + compatible = "arm,scmi-shmem"; > + reg = <0x80 0x80>; > + }; > + }; > + }; > + > + mu3: mailbox@445d0000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x445d0000 0x10000>; > + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + mu4: mailbox@445f0000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x445f0000 0x10000>; > + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + mu6: mailbox@44630000 { > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > + reg = <0x44630000 0x10000>; > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <2>; > + status = "disabled"; > + }; > + > + a55_irqsteer: interrupt-controller@446a0000 { > + compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer"; > + reg = <0x446a0000 0x1000>; > + #interrupt-cells = <1>; > + interrupt-controller; > + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > + clock-names = "ipg"; > + fsl,channel = <0>; > + fsl,num-irqs = <960>; > + }; > + }; > + > + aips4: bus@49000000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + reg = <0x0 0x49000000 0x0 0x800000>; > + ranges = <0x49000000 0x0 0x49000000 0x800000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + wdog3: watchdog@49220000 { > + compatible = "fsl,imx94-wdt", "fsl,imx93-wdt"; > + reg = <0x49220000 0x10000>; > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > + timeout-sec = <40>; > + fsl,ext-reset-output; > + status = "disabled"; > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi > new file mode 100644 > index 000000000000..45b8da758e87 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi > @@ -0,0 +1,148 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2025 NXP > + */ > + > +#include "imx94.dtsi" > + > +/ { > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + idle-states { > + entry-method = "psci"; > + > + cpu_pd_wait: cpu-pd-wait { > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010033>; > + local-timer-stop; > + entry-latency-us = <1000>; > + exit-latency-us = <700>; > + min-residency-us = <2700>; > + wakeup-latency-us = <1500>; > + }; > + }; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + reg = <0x0>; > + enable-method = "psci"; > + #cooling-cells = <2>; > + cpu-idle-states = <&cpu_pd_wait>; > + power-domains = <&scmi_perf IMX94_PERF_A55>; > + power-domain-names = "perf"; > + i-cache-size = <32768>; > + i-cache-line-size = <64>; > + i-cache-sets = <128>; > + d-cache-size = <32768>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l0>; > + }; > + > + cpu1: cpu@100 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + reg = <0x100>; > + enable-method = "psci"; > + #cooling-cells = <2>; > + cpu-idle-states = <&cpu_pd_wait>; > + power-domains = <&scmi_perf IMX94_PERF_A55>; > + power-domain-names = "perf"; > + i-cache-size = <32768>; > + i-cache-line-size = <64>; > + i-cache-sets = <128>; > + d-cache-size = <32768>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l1>; > + }; > + > + cpu2: cpu@200 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + reg = <0x200>; > + enable-method = "psci"; > + #cooling-cells = <2>; > + cpu-idle-states = <&cpu_pd_wait>; > + power-domains = <&scmi_perf IMX94_PERF_A55>; > + power-domain-names = "perf"; > + i-cache-size = <32768>; > + i-cache-line-size = <64>; > + i-cache-sets = <128>; > + d-cache-size = <32768>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l2>; > + }; > + > + cpu3: cpu@300 { > + compatible = "arm,cortex-a55"; > + device_type = "cpu"; > + reg = <0x300>; > + enable-method = "psci"; > + #cooling-cells = <2>; > + cpu-idle-states = <&cpu_pd_wait>; > + power-domains = <&scmi_perf IMX94_PERF_A55>; > + power-domain-names = "perf"; > + i-cache-size = <32768>; > + i-cache-line-size = <64>; > + i-cache-sets = <128>; > + d-cache-size = <32768>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l3>; > + }; > + > + l2_cache_l0: l2-cache-l0 { > + compatible = "cache"; > + cache-size = <65536>; > + cache-line-size = <64>; > + cache-sets = <256>; > + cache-level = <2>; > + cache-unified; > + next-level-cache = <&l3_cache>; > + }; > + > + l2_cache_l1: l2-cache-l1 { > + compatible = "cache"; > + cache-size = <65536>; > + cache-line-size = <64>; > + cache-sets = <256>; > + cache-level = <2>; > + cache-unified; > + next-level-cache = <&l3_cache>; > + }; > + > + l2_cache_l2: l2-cache-l2 { > + compatible = "cache"; > + cache-size = <65536>; > + cache-line-size = <64>; > + cache-sets = <256>; > + cache-level = <2>; > + cache-unified; > + next-level-cache = <&l3_cache>; > + }; > + > + l2_cache_l3: l2-cache-l3 { > + compatible = "cache"; > + cache-size = <65536>; > + cache-line-size = <64>; > + cache-sets = <256>; > + cache-level = <2>; > + cache-unified; > + next-level-cache = <&l3_cache>; > + }; > + > + l3_cache: l3-cache { > + compatible = "cache"; > + cache-size = <1048576>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + cache-level = <3>; > + cache-unified; > + }; > + }; > +}; > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v5 2/3] arm64: dts: freescale: Add basic dtsi for imx943 2025-04-10 15:41 ` [PATCH v5 2/3] arm64: dts: freescale: Add basic dtsi for imx943 Frank Li @ 2025-04-11 1:46 ` Jacky Bai 2025-04-11 14:44 ` Frank Li 0 siblings, 1 reply; 8+ messages in thread From: Jacky Bai @ 2025-04-11 1:46 UTC (permalink / raw) To: Frank Li Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Aisheng Dong, Peng Fan > Subject: Re: [PATCH v5 2/3] arm64: dts: freescale: Add basic dtsi for imx943 > > On Thu, Apr 10, 2025 at 02:28:25PM +0800, Jacky Bai wrote: > > Add the minimal dtsi support for i.MX943. i.MX943 is the first SoC of > > i.MX94 Family, create a common dtsi for the whole i.MX94 family, and > > the specific dtsi part for i.MX943. > > > > The clock, power domain and perf index need to be used by the device > > nodes for resource reference, add them along with the dtsi support. > > Please wrap at 75 char to maxium use sceen width. > Ok. > > > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > > --- > > - v5 changes: > > - remove the err irq of edma node as the err irq support in driver is not > > ready. We can add it back when the driver is ready. No impact for > current > > edma support. > > > > - v4 changes: > > - reorder the cpu node compatible string property as suggested by > > Frank > > > > - v3 changes: > > - remove the blank line > > - add PAD config macro define as suggested by Frank Li > > - update the device nodes compatible strings for imx94 as suggested > > by Krzysztof > > > > - v2 changes: > > - remove the unnecessary macro define in clock header as suggested by > Krzysztof > > - split the dtsi into imx94.dtsi and imx943.dtsi > > - use low case in the pinfunc header as Frank suggested > > - reorder the device nodes and properties > > --- > > arch/arm64/boot/dts/freescale/imx94-clock.h | 195 ++ > > arch/arm64/boot/dts/freescale/imx94-pinfunc.h | 1570 > +++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx94-power.h | 41 + > > arch/arm64/boot/dts/freescale/imx94.dtsi | 1138 ++++++++++++ > > arch/arm64/boot/dts/freescale/imx943.dtsi | 148 ++ > > 5 files changed, 3092 insertions(+) > > create mode 100644 arch/arm64/boot/dts/freescale/imx94-clock.h > > create mode 100644 arch/arm64/boot/dts/freescale/imx94-pinfunc.h > > create mode 100644 arch/arm64/boot/dts/freescale/imx94-power.h > > create mode 100644 arch/arm64/boot/dts/freescale/imx94.dtsi > > create mode 100644 arch/arm64/boot/dts/freescale/imx943.dtsi > > > ... > > + #size-cells = <1>; > > + > > + edma2: dma-controller@42000000 { > > + compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; > > + reg = <0x42000000 0x210000>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "dma"; > > + #dma-cells = <3>; > > + dma-channels = <64>; > > + interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer > 1>, <&a55_irqsteer 2>, > > + <&a55_irqsteer 3>, <&a55_irqsteer 4>, > <&a55_irqsteer 5>, > > need align previous line "<" > Ok > > + <&a55_irqsteer 6>, <&a55_irqsteer 7>, > <&a55_irqsteer 8>, > > Does it work by use > > interrupt-parent = <&a55_irqsteer>; > interrupts = <0>, <1> ... > > if it works, it will reduce many &a55_irqsteer. > But if we add the err irq back later after the driver change is merged, we need to change it back again as the err irq is connected GIC. BR Jacky Bai > Frank > > + <&a55_irqsteer 9>, <&a55_irqsteer 10>, > <&a55_irqsteer 11>, > > + <&a55_irqsteer 12>, <&a55_irqsteer 13>, > <&a55_irqsteer 14>, > > + <&a55_irqsteer 15>, <&a55_irqsteer 16>, > <&a55_irqsteer 17>, > > + <&a55_irqsteer 18>, <&a55_irqsteer 19>, > <&a55_irqsteer 20>, > > + <&a55_irqsteer 21>, <&a55_irqsteer 22>, > <&a55_irqsteer 23>, > > + <&a55_irqsteer 24>, <&a55_irqsteer 25>, > <&a55_irqsteer 26>, > > + <&a55_irqsteer 27>, <&a55_irqsteer 28>, > <&a55_irqsteer 29>, > > + <&a55_irqsteer 30>, <&a55_irqsteer 31>, > <&a55_irqsteer 64>, > > + <&a55_irqsteer 65>, <&a55_irqsteer 66>, > <&a55_irqsteer 67>, > > + <&a55_irqsteer 68>, <&a55_irqsteer 69>, > <&a55_irqsteer 70>, > > + <&a55_irqsteer 71>, <&a55_irqsteer 72>, > <&a55_irqsteer 73>, > > + <&a55_irqsteer 74>, <&a55_irqsteer 75>, > <&a55_irqsteer 76>, > > + <&a55_irqsteer 77>, <&a55_irqsteer 78>, > <&a55_irqsteer 79>, > > + <&a55_irqsteer 80>, <&a55_irqsteer 81>, > <&a55_irqsteer 82>, > > + <&a55_irqsteer 83>, <&a55_irqsteer 84>, > <&a55_irqsteer 85>, > > + <&a55_irqsteer 86>, <&a55_irqsteer 87>, > <&a55_irqsteer 88>, > > + <&a55_irqsteer 89>, <&a55_irqsteer 90>, > <&a55_irqsteer 91>, > > + <&a55_irqsteer 92>, <&a55_irqsteer 93>, > <&a55_irqsteer 94>, > > + <&a55_irqsteer 95>; > > + }; > > + > > + mu10: mailbox@42430000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x42430000 0x10000>; > > + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + i3c2: i3c@42520000 { > > + compatible = "silvaco,i3c-master-v1"; > > + reg = <0x42520000 0x10000>; > > + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <3>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX94_CLK_I3C2SLOW>, > > + <&dummy>; > > + clock-names = "pclk", "fast_clk", "slow_clk"; > > + status = "disabled"; > > + }; > > + > > + lpi2c3: i2c@42530000 { > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x42530000 0x10000>; > > + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPI2C3>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma2 5 0 0>, <&edma2 6 0 FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpi2c4: i2c@42540000 { > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x42540000 0x10000>; > > + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPI2C4>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma4 4 0 0>, <&edma4 5 0 FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpspi3: spi@42550000 { > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > + reg = <0x42550000 0x10000>; > > + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPSPI3>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma2 7 0 0>, <&edma2 8 0 FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpspi4: spi@42560000 { > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > + reg = <0x42560000 0x10000>; > > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPSPI4>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma4 6 0 0>, <&edma4 7 0 FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpuart3: serial@42570000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42570000 0x1000>; > > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART3>; > > + clock-names = "ipg"; > > + dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 9 0 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + lpuart4: serial@42580000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42580000 0x1000>; > > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART4>; > > + clock-names = "ipg"; > > + dmas = <&edma4 10 0 FSL_EDMA_RX>, <&edma4 9 0 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + lpuart5: serial@42590000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42590000 0x1000>; > > + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART5>; > > + clock-names = "ipg"; > > + dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 11 0 > 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + lpuart6: serial@425a0000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x425a0000 0x1000>; > > + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART6>; > > + clock-names = "ipg"; > > + dmas = <&edma4 12 0 FSL_EDMA_RX>, <&edma4 11 0 > 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + flexcan2: can@425b0000 { > > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > > + reg = <0x425b0000 0x10000>; > > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX94_CLK_CAN2>; > > + clock-names = "ipg", "per"; > > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN2>; > > + assigned-clock-parents = <&scmi_clk > IMX94_CLK_SYSPLL1_PFD1_DIV2>; > > + assigned-clock-rates = <80000000>; > > + fsl,clk-source = /bits/ 8 <0>; > > + status = "disabled"; > > + }; > > + > > + flexcan3: can@425e0000 { > > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > > + reg = <0x425e0000 0x10000>; > > + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX94_CLK_CAN3>; > > + clock-names = "ipg", "per"; > > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN3>; > > + assigned-clock-parents = <&scmi_clk > IMX94_CLK_SYSPLL1_PFD1_DIV2>; > > + assigned-clock-rates = <80000000>; > > + fsl,clk-source = /bits/ 8 <0>; > > + status = "disabled"; > > + }; > > + > > + flexcan4: can@425f0000 { > > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > > + reg = <0x425f0000 0x10000>; > > + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX94_CLK_CAN4>; > > + clock-names = "ipg", "per"; > > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN4>; > > + assigned-clock-parents = <&scmi_clk > IMX94_CLK_SYSPLL1_PFD1_DIV2>; > > + assigned-clock-rates = <80000000>; > > + fsl,clk-source = /bits/ 8 <0>; > > + status = "disabled"; > > + }; > > + > > + flexcan5: can@42600000 { > > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > > + reg = <0x42600000 0x10000>; > > + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX94_CLK_CAN5>; > > + clock-names = "ipg", "per"; > > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN5>; > > + assigned-clock-parents = <&scmi_clk > IMX94_CLK_SYSPLL1_PFD1_DIV2>; > > + assigned-clock-rates = <80000000>; > > + fsl,clk-source = /bits/ 8 <0>; > > + status = "disabled"; > > + }; > > + > > + sai2: sai@42650000 { > > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > > + reg = <0x42650000 0x10000>; > > + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > <&dummy>, > > + <&scmi_clk IMX94_CLK_SAI2>, <&dummy>, > <&dummy>; > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > + dmas = <&edma2 30 0 FSL_EDMA_RX>, <&edma2 29 0 > 0>; > > + dma-names = "rx", "tx"; > > + #sound-dai-cells = <0>; > > + status = "disabled"; > > + }; > > + > > + sai3: sai@42660000 { > > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > > + reg = <0x42660000 0x10000>; > > + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > <&dummy>, > > + <&scmi_clk IMX94_CLK_SAI3>, <&dummy>, > <&dummy>; > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > + dmas = <&edma2 32 0 FSL_EDMA_RX>, <&edma2 31 0 > 0>; > > + dma-names = "rx", "tx"; > > + #sound-dai-cells = <0>; > > + status = "disabled"; > > + }; > > + > > + sai4: sai@42670000 { > > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > > + reg = <0x42670000 0x10000>; > > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > <&dummy>, > > + <&scmi_clk IMX94_CLK_SAI4>, <&dummy>, > <&dummy>; > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > + dmas = <&edma2 36 0 FSL_EDMA_RX>, <&edma2 35 0 > 0>; > > + dma-names = "rx", "tx"; > > + #sound-dai-cells = <0>; > > + status = "disabled"; > > + }; > > + > > + lpuart7: serial@42690000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42690000 0x1000>; > > + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART7>; > > + clock-names = "ipg"; > > + dmas = <&edma2 46 0 FSL_EDMA_RX>, <&edma2 45 0 > 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + lpuart8: serial@426a0000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x426a0000 0x1000>; > > + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART8>; > > + clock-names = "ipg"; > > + dmas = <&edma4 39 0 FSL_EDMA_RX>, <&edma4 38 0 > 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + lpi2c5: i2c@426b0000 { > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x426b0000 0x10000>; > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPI2C5>, > > + <&scmi_clk IMX94_CLK_BUSAON>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma2 37 0 0>, <&edma2 38 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpi2c6: i2c@426c0000 { > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x426c0000 0x10000>; > > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPI2C6>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma4 30 0 0>, <&edma4 31 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpi2c7: i2c@426d0000 { > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x426d0000 0x10000>; > > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPI2C7>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma2 39 0 0>, <&edma2 40 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpi2c8: i2c@426e0000 { > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x426e0000 0x10000>; > > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPI2C8>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma4 32 0 0>, <&edma4 33 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpspi5: spi@426f0000 { > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > + reg = <0x426f0000 0x10000>; > > + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPSPI5>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma2 41 0 0>, <&edma2 42 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpspi6: spi@42700000 { > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > + reg = <0x42700000 0x10000>; > > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPSPI6>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma4 34 0 0>, <&edma4 35 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpspi7: spi@42710000 { > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > + reg = <0x42710000 0x10000>; > > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPSPI7>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma2 43 0 0>, <&edma2 44 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpspi8: spi@42720000 { > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > + reg = <0x42720000 0x10000>; > > + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPSPI8>, > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma4 36 0 0>, <&edma4 37 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + mu11: mailbox@42730000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x42730000 0x10000>; > > + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + edma4: dma-controller@42df0000 { > > + compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; > > + reg = <0x42df0000 0x210000>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + clock-names = "dma"; > > + #dma-cells = <3>; > > + dma-channels = <64>; > > + interrupts-extended = <&a55_irqsteer 128>, > <&a55_irqsteer 129>, > > + <&a55_irqsteer 130>, <&a55_irqsteer 131>, > > + <&a55_irqsteer 132>, <&a55_irqsteer 133>, > > + <&a55_irqsteer 134>, <&a55_irqsteer 135>, > > + <&a55_irqsteer 136>, <&a55_irqsteer 137>, > > + <&a55_irqsteer 138>, <&a55_irqsteer 139>, > > + <&a55_irqsteer 140>, <&a55_irqsteer 141>, > > + <&a55_irqsteer 142>, <&a55_irqsteer 143>, > > + <&a55_irqsteer 144>, <&a55_irqsteer 145>, > > + <&a55_irqsteer 146>, <&a55_irqsteer 147>, > > + <&a55_irqsteer 148>, <&a55_irqsteer 149>, > > + <&a55_irqsteer 150>, <&a55_irqsteer 151>, > > + <&a55_irqsteer 152>, <&a55_irqsteer 153>, > > + <&a55_irqsteer 154>, <&a55_irqsteer 155>, > > + <&a55_irqsteer 156>, <&a55_irqsteer 157>, > > + <&a55_irqsteer 158>, <&a55_irqsteer 159>, > > + <&a55_irqsteer 192>, <&a55_irqsteer 193>, > > + <&a55_irqsteer 194>, <&a55_irqsteer 195>, > > + <&a55_irqsteer 196>, <&a55_irqsteer 197>, > > + <&a55_irqsteer 198>, <&a55_irqsteer 199>, > > + <&a55_irqsteer 200>, <&a55_irqsteer 201>, > > + <&a55_irqsteer 202>, <&a55_irqsteer 203>, > > + <&a55_irqsteer 204>, <&a55_irqsteer 205>, > > + <&a55_irqsteer 206>, <&a55_irqsteer 207>, > > + <&a55_irqsteer 208>, <&a55_irqsteer 209>, > > + <&a55_irqsteer 210>, <&a55_irqsteer 211>, > > + <&a55_irqsteer 212>, <&a55_irqsteer 213>, > > + <&a55_irqsteer 214>, <&a55_irqsteer 215>, > > + <&a55_irqsteer 216>, <&a55_irqsteer 217>, > > + <&a55_irqsteer 218>, <&a55_irqsteer 219>, > > + <&a55_irqsteer 220>, <&a55_irqsteer 221>, > > + <&a55_irqsteer 222>, <&a55_irqsteer 223>; > > + }; > > + }; > > + > > + aips3: bus@42800000 { > > + compatible = "fsl,aips-bus", "simple-bus"; > > + reg = <0 0x42800000 0 0x800000>; > > + ranges = <0x42800000 0x0 0x42800000 0x800000>, > > + <0x28000000 0x0 0x28000000 0x1000000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + usdhc1: mmc@42850000 { > > + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; > > + reg = <0x42850000 0x10000>; > > + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX94_CLK_WAKEUPAXI>, > > + <&scmi_clk IMX94_CLK_USDHC1>; > > + clock-names = "ipg", "ahb", "per"; > > + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC1>; > > + assigned-clock-parents = <&scmi_clk > IMX94_CLK_SYSPLL1_PFD1>; > > + assigned-clock-rates = <400000000>; > > + bus-width = <8>; > > + fsl,tuning-start-tap = <1>; > > + fsl,tuning-step = <2>; > > + status = "disabled"; > > + }; > > + > > + usdhc2: mmc@42860000 { > > + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; > > + reg = <0x42860000 0x10000>; > > + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX94_CLK_WAKEUPAXI>, > > + <&scmi_clk IMX94_CLK_USDHC2>; > > + clock-names = "ipg", "ahb", "per"; > > + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC2>; > > + assigned-clock-parents = <&scmi_clk > IMX94_CLK_SYSPLL1_PFD1>; > > + assigned-clock-rates = <200000000>; > > + bus-width = <4>; > > + fsl,tuning-start-tap = <1>; > > + fsl,tuning-step = <2>; > > + status = "disabled"; > > + }; > > + > > + usdhc3: mmc@42880000 { > > + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; > > + reg = <0x42880000 0x10000>; > > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX94_CLK_WAKEUPAXI>, > > + <&scmi_clk IMX94_CLK_USDHC3>; > > + clock-names = "ipg", "ahb", "per"; > > + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC3>; > > + assigned-clock-parents = <&scmi_clk > IMX94_CLK_SYSPLL1_PFD1>; > > + assigned-clock-rates = <200000000>; > > + bus-width = <4>; > > + fsl,tuning-start-tap = <1>; > > + fsl,tuning-step = <2>; > > + status = "disabled"; > > + }; > > + > > + lpuart9: serial@42a50000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42a50000 0x1000>; > > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART10>; > > + clock-names = "ipg"; > > + dmas = <&edma2 51 0 FSL_EDMA_RX>, <&edma2 50 0 > 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + lpuart10: serial@42a60000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42a60000 0x1000>; > > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART10>; > > + clock-names = "ipg"; > > + dmas = <&edma4 47 0 FSL_EDMA_RX>, <&edma4 46 0 > 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + lpuart11: serial@42a70000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42a70000 0x1000>; > > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART11>; > > + clock-names = "ipg"; > > + dmas = <&edma2 53 0 FSL_EDMA_RX>, <&edma2 52 0 > 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + lpuart12: serial@42a80000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42a80000 0x1000>; > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART12>; > > + clock-names = "ipg"; > > + dmas = <&edma4 49 0 FSL_EDMA_RX>, <&edma4 48 0 > 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + mu12: mailbox@42ac0000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x42ac0000 0x10000>; > > + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + mu13: mailbox@42ae0000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x42ae0000 0x10000>; > > + interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + mu14: mailbox@42b00000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x42b00000 0x10000>; > > + interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + mu15: mailbox@42b20000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x42b20000 0x10000>; > > + interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + mu16: mailbox@42b40000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x42b40000 0x10000>; > > + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + mu17: mailbox@42b60000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x42b60000 0x10000>; > > + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + }; > > + > > + gpio2: gpio@43810000 { > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x43810000 0x0 0x1000>; > > + #interrupt-cells = <2>; > > + interrupt-controller; > > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > > + #gpio-cells = <2>; > > + gpio-controller; > > + gpio-ranges = <&scmi_iomuxc 0 4 32>; > > + }; > > + > > + gpio3: gpio@43820000 { > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x43820000 0x0 0x1000>; > > + #interrupt-cells = <2>; > > + interrupt-controller; > > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > > + #gpio-cells = <2>; > > + gpio-controller; > > + gpio-ranges = <&scmi_iomuxc 0 36 26>; > > + }; > > + > > + gpio4: gpio@43840000 { > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x43840000 0x0 0x1000>; > > + #interrupt-cells = <2>; > > + interrupt-controller; > > + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; > > + #gpio-cells = <2>; > > + gpio-controller; > > + gpio-ranges = <&scmi_iomuxc 0 62 4>, <&scmi_iomuxc 4 0 4>, > > + <&scmi_iomuxc 8 140 12>, <&scmi_iomuxc 20 164 > 12>; > > + }; > > + > > + gpio5: gpio@43850000 { > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x43850000 0x0 0x1000>; > > + #interrupt-cells = <2>; > > + interrupt-controller; > > + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; > > + #gpio-cells = <2>; > > + gpio-controller; > > + gpio-ranges = <&scmi_iomuxc 0 108 32>; > > + }; > > + > > + gpio6: gpio@43860000 { > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x43860000 0x0 0x1000>; > > + #interrupt-cells = <2>; > > + interrupt-controller; > > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; > > + #gpio-cells = <2>; > > + gpio-controller; > > + gpio-ranges = <&scmi_iomuxc 0 66 32>; > > + }; > > + > > + gpio7: gpio@43870000 { > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x43870000 0x0 0x1000>; > > + #interrupt-cells = <2>; > > + interrupt-controller; > > + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; > > + #gpio-cells = <2>; > > + gpio-controller; > > + gpio-ranges = <&scmi_iomuxc 0 98 10>, <&scmi_iomuxc 16 152 > 12>; > > + }; > > + > > + aips1: bus@44000000 { > > + compatible = "fsl,aips-bus", "simple-bus"; > > + reg = <0x0 0x44000000 0x0 0x800000>; > > + ranges = <0x44000000 0x0 0x44000000 0x800000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + edma1: dma-controller@44000000 { > > + compatible = "fsl,imx94-edma3", "fsl,imx93-edma3"; > > + reg = <0x44000000 0x210000>; > > + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > > + clock-names = "dma"; > > + #dma-cells = <3>; > > + dma-channels = <32>; > > + }; > > + > > + mu1: mailbox@44220000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x44220000 0x10000>; > > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + system_counter: timer@44290000 { > > + compatible = "nxp,imx94-sysctr-timer", > "nxp,imx95-sysctr-timer"; > > + reg = <0x44290000 0x30000>; > > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&osc_24m>; > > + clock-names = "per"; > > + nxp,no-divider; > > + }; > > + > > + tpm1: pwm@44310000 { > > + compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; > > + reg = <0x44310000 0x1000>; > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + > > + tpm2: pwm@44320000 { > > + compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; > > + reg = <0x44320000 0x1000>; > > + clocks = <&scmi_clk IMX94_CLK_TPM2>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + > > + i3c1: i3c@44330000 { > > + compatible = "silvaco,i3c-master-v1"; > > + reg = <0x44330000 0x10000>; > > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <3>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>, > > + <&scmi_clk IMX94_CLK_I3C1SLOW>, > > + <&dummy>; > > + clock-names = "pclk", "fast_clk", "slow_clk"; > > + status = "disabled"; > > + }; > > + > > + lpi2c1: i2c@44340000 { > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x44340000 0x10000>; > > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPI2C1>, > > + <&scmi_clk IMX94_CLK_BUSAON>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma1 12 0 0>, <&edma1 13 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpi2c2: i2c@44350000 { > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x44350000 0x10000>; > > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPI2C2>, > > + <&scmi_clk IMX94_CLK_BUSAON>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma1 14 0 0>, <&edma1 15 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpspi1: spi@44360000 { > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > + reg = <0x44360000 0x10000>; > > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPSPI2>, > > + <&scmi_clk IMX94_CLK_BUSAON>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma1 16 0 0>, <&edma1 17 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpspi2: spi@44370000 { > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > + reg = <0x44370000 0x10000>; > > + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + clocks = <&scmi_clk IMX94_CLK_LPSPI2>, > > + <&scmi_clk IMX94_CLK_BUSAON>; > > + clock-names = "per", "ipg"; > > + dmas = <&edma1 18 0 0>, <&edma1 19 0 > FSL_EDMA_RX>; > > + dma-names = "tx", "rx"; > > + status = "disabled"; > > + }; > > + > > + lpuart1: serial@44380000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x44380000 0x1000>; > > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART1>; > > + clock-names = "ipg"; > > + dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 > 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + lpuart2: serial@44390000 { > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x44390000 0x1000>; > > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_LPUART2>; > > + clock-names = "ipg"; > > + dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 > 0>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > + > > + flexcan1: can@443a0000 { > > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > > + reg = <0x443a0000 0x10000>; > > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + }; > > + > > + sai1: sai@443b0000 { > > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > > + reg = <0x443b0000 0x10000>; > > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>, <&dummy>, > > + <&scmi_clk IMX94_CLK_SAI1>, <&dummy>, > > + <&dummy>, <&dummy>; > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > + dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 > 0>; > > + dma-names = "rx", "tx"; > > + #sound-dai-cells = <0>; > > + status = "disabled"; > > + }; > > + > > + adc1: adc@44530000 { > > + compatible = "nxp,imx94-adc", "nxp,imx93-adc"; > > + reg = <0x44530000 0x10000>; > > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_ADC>; > > + clock-names = "ipg"; > > + #io-channel-cells = <1>; > > + status = "disabled"; > > + }; > > + > > + mu2: mailbox@445b0000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x445b0000 0x1000>; > > + ranges; > > + interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + #mbox-cells = <2>; > > + > > + sram0: sram@445b1000 { > > + compatible = "mmio-sram"; > > + reg = <0x445b1000 0x400>; > > + ranges = <0x0 0x445b1000 0x400>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + scmi_buf0: scmi-sram-section@0 { > > + compatible = "arm,scmi-shmem"; > > + reg = <0x0 0x80>; > > + }; > > + > > + scmi_buf1: scmi-sram-section@80 { > > + compatible = "arm,scmi-shmem"; > > + reg = <0x80 0x80>; > > + }; > > + }; > > + }; > > + > > + mu3: mailbox@445d0000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x445d0000 0x10000>; > > + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + mu4: mailbox@445f0000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x445f0000 0x10000>; > > + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + mu6: mailbox@44630000 { > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > + reg = <0x44630000 0x10000>; > > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + a55_irqsteer: interrupt-controller@446a0000 { > > + compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer"; > > + reg = <0x446a0000 0x1000>; > > + #interrupt-cells = <1>; > > + interrupt-controller; > > + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > > + clock-names = "ipg"; > > + fsl,channel = <0>; > > + fsl,num-irqs = <960>; > > + }; > > + }; > > + > > + aips4: bus@49000000 { > > + compatible = "fsl,aips-bus", "simple-bus"; > > + reg = <0x0 0x49000000 0x0 0x800000>; > > + ranges = <0x49000000 0x0 0x49000000 0x800000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + wdog3: watchdog@49220000 { > > + compatible = "fsl,imx94-wdt", "fsl,imx93-wdt"; > > + reg = <0x49220000 0x10000>; > > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > + timeout-sec = <40>; > > + fsl,ext-reset-output; > > + status = "disabled"; > > + }; > > + }; > > + }; > > +}; > > diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi > > b/arch/arm64/boot/dts/freescale/imx943.dtsi > > new file mode 100644 > > index 000000000000..45b8da758e87 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi > > @@ -0,0 +1,148 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Copyright 2025 NXP > > + */ > > + > > +#include "imx94.dtsi" > > + > > +/ { > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + idle-states { > > + entry-method = "psci"; > > + > > + cpu_pd_wait: cpu-pd-wait { > > + compatible = "arm,idle-state"; > > + arm,psci-suspend-param = <0x0010033>; > > + local-timer-stop; > > + entry-latency-us = <1000>; > > + exit-latency-us = <700>; > > + min-residency-us = <2700>; > > + wakeup-latency-us = <1500>; > > + }; > > + }; > > + > > + cpu0: cpu@0 { > > + compatible = "arm,cortex-a55"; > > + device_type = "cpu"; > > + reg = <0x0>; > > + enable-method = "psci"; > > + #cooling-cells = <2>; > > + cpu-idle-states = <&cpu_pd_wait>; > > + power-domains = <&scmi_perf IMX94_PERF_A55>; > > + power-domain-names = "perf"; > > + i-cache-size = <32768>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <128>; > > + d-cache-size = <32768>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + next-level-cache = <&l2_cache_l0>; > > + }; > > + > > + cpu1: cpu@100 { > > + compatible = "arm,cortex-a55"; > > + device_type = "cpu"; > > + reg = <0x100>; > > + enable-method = "psci"; > > + #cooling-cells = <2>; > > + cpu-idle-states = <&cpu_pd_wait>; > > + power-domains = <&scmi_perf IMX94_PERF_A55>; > > + power-domain-names = "perf"; > > + i-cache-size = <32768>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <128>; > > + d-cache-size = <32768>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + next-level-cache = <&l2_cache_l1>; > > + }; > > + > > + cpu2: cpu@200 { > > + compatible = "arm,cortex-a55"; > > + device_type = "cpu"; > > + reg = <0x200>; > > + enable-method = "psci"; > > + #cooling-cells = <2>; > > + cpu-idle-states = <&cpu_pd_wait>; > > + power-domains = <&scmi_perf IMX94_PERF_A55>; > > + power-domain-names = "perf"; > > + i-cache-size = <32768>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <128>; > > + d-cache-size = <32768>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + next-level-cache = <&l2_cache_l2>; > > + }; > > + > > + cpu3: cpu@300 { > > + compatible = "arm,cortex-a55"; > > + device_type = "cpu"; > > + reg = <0x300>; > > + enable-method = "psci"; > > + #cooling-cells = <2>; > > + cpu-idle-states = <&cpu_pd_wait>; > > + power-domains = <&scmi_perf IMX94_PERF_A55>; > > + power-domain-names = "perf"; > > + i-cache-size = <32768>; > > + i-cache-line-size = <64>; > > + i-cache-sets = <128>; > > + d-cache-size = <32768>; > > + d-cache-line-size = <64>; > > + d-cache-sets = <128>; > > + next-level-cache = <&l2_cache_l3>; > > + }; > > + > > + l2_cache_l0: l2-cache-l0 { > > + compatible = "cache"; > > + cache-size = <65536>; > > + cache-line-size = <64>; > > + cache-sets = <256>; > > + cache-level = <2>; > > + cache-unified; > > + next-level-cache = <&l3_cache>; > > + }; > > + > > + l2_cache_l1: l2-cache-l1 { > > + compatible = "cache"; > > + cache-size = <65536>; > > + cache-line-size = <64>; > > + cache-sets = <256>; > > + cache-level = <2>; > > + cache-unified; > > + next-level-cache = <&l3_cache>; > > + }; > > + > > + l2_cache_l2: l2-cache-l2 { > > + compatible = "cache"; > > + cache-size = <65536>; > > + cache-line-size = <64>; > > + cache-sets = <256>; > > + cache-level = <2>; > > + cache-unified; > > + next-level-cache = <&l3_cache>; > > + }; > > + > > + l2_cache_l3: l2-cache-l3 { > > + compatible = "cache"; > > + cache-size = <65536>; > > + cache-line-size = <64>; > > + cache-sets = <256>; > > + cache-level = <2>; > > + cache-unified; > > + next-level-cache = <&l3_cache>; > > + }; > > + > > + l3_cache: l3-cache { > > + compatible = "cache"; > > + cache-size = <1048576>; > > + cache-line-size = <64>; > > + cache-sets = <1024>; > > + cache-level = <3>; > > + cache-unified; > > + }; > > + }; > > +}; > > -- > > 2.34.1 > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v5 2/3] arm64: dts: freescale: Add basic dtsi for imx943 2025-04-11 1:46 ` Jacky Bai @ 2025-04-11 14:44 ` Frank Li 0 siblings, 0 replies; 8+ messages in thread From: Frank Li @ 2025-04-11 14:44 UTC (permalink / raw) To: Jacky Bai Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Aisheng Dong, Peng Fan On Fri, Apr 11, 2025 at 01:46:28AM +0000, Jacky Bai wrote: > > Subject: Re: [PATCH v5 2/3] arm64: dts: freescale: Add basic dtsi for imx943 > > > > On Thu, Apr 10, 2025 at 02:28:25PM +0800, Jacky Bai wrote: > > > Add the minimal dtsi support for i.MX943. i.MX943 is the first SoC of > > > i.MX94 Family, create a common dtsi for the whole i.MX94 family, and > > > the specific dtsi part for i.MX943. > > > > > > The clock, power domain and perf index need to be used by the device > > > nodes for resource reference, add them along with the dtsi support. > > > > Please wrap at 75 char to maxium use sceen width. > > > > Ok. > > > > > > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > > > --- > > > - v5 changes: > > > - remove the err irq of edma node as the err irq support in driver is not > > > ready. We can add it back when the driver is ready. No impact for > > current > > > edma support. > > > > > > - v4 changes: > > > - reorder the cpu node compatible string property as suggested by > > > Frank > > > > > > - v3 changes: > > > - remove the blank line > > > - add PAD config macro define as suggested by Frank Li > > > - update the device nodes compatible strings for imx94 as suggested > > > by Krzysztof > > > > > > - v2 changes: > > > - remove the unnecessary macro define in clock header as suggested by > > Krzysztof > > > - split the dtsi into imx94.dtsi and imx943.dtsi > > > - use low case in the pinfunc header as Frank suggested > > > - reorder the device nodes and properties > > > --- > > > arch/arm64/boot/dts/freescale/imx94-clock.h | 195 ++ > > > arch/arm64/boot/dts/freescale/imx94-pinfunc.h | 1570 > > +++++++++++++++++ > > > arch/arm64/boot/dts/freescale/imx94-power.h | 41 + > > > arch/arm64/boot/dts/freescale/imx94.dtsi | 1138 ++++++++++++ > > > arch/arm64/boot/dts/freescale/imx943.dtsi | 148 ++ > > > 5 files changed, 3092 insertions(+) > > > create mode 100644 arch/arm64/boot/dts/freescale/imx94-clock.h > > > create mode 100644 arch/arm64/boot/dts/freescale/imx94-pinfunc.h > > > create mode 100644 arch/arm64/boot/dts/freescale/imx94-power.h > > > create mode 100644 arch/arm64/boot/dts/freescale/imx94.dtsi > > > create mode 100644 arch/arm64/boot/dts/freescale/imx943.dtsi > > > > > ... > > > + #size-cells = <1>; > > > + > > > + edma2: dma-controller@42000000 { > > > + compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; > > > + reg = <0x42000000 0x210000>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "dma"; > > > + #dma-cells = <3>; > > > + dma-channels = <64>; > > > + interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer > > 1>, <&a55_irqsteer 2>, > > > + <&a55_irqsteer 3>, <&a55_irqsteer 4>, > > <&a55_irqsteer 5>, > > > > need align previous line "<" > > > > Ok > > > > + <&a55_irqsteer 6>, <&a55_irqsteer 7>, > > <&a55_irqsteer 8>, > > > > Does it work by use > > > > interrupt-parent = <&a55_irqsteer>; > > interrupts = <0>, <1> ... > > > > if it works, it will reduce many &a55_irqsteer. > > > > But if we add the err irq back later after the driver change is merged, we need to change > it back again as the err irq is connected GIC. Make sense, thanks! Frank > > BR > Jacky Bai > > Frank > > > + <&a55_irqsteer 9>, <&a55_irqsteer 10>, > > <&a55_irqsteer 11>, > > > + <&a55_irqsteer 12>, <&a55_irqsteer 13>, > > <&a55_irqsteer 14>, > > > + <&a55_irqsteer 15>, <&a55_irqsteer 16>, > > <&a55_irqsteer 17>, > > > + <&a55_irqsteer 18>, <&a55_irqsteer 19>, > > <&a55_irqsteer 20>, > > > + <&a55_irqsteer 21>, <&a55_irqsteer 22>, > > <&a55_irqsteer 23>, > > > + <&a55_irqsteer 24>, <&a55_irqsteer 25>, > > <&a55_irqsteer 26>, > > > + <&a55_irqsteer 27>, <&a55_irqsteer 28>, > > <&a55_irqsteer 29>, > > > + <&a55_irqsteer 30>, <&a55_irqsteer 31>, > > <&a55_irqsteer 64>, > > > + <&a55_irqsteer 65>, <&a55_irqsteer 66>, > > <&a55_irqsteer 67>, > > > + <&a55_irqsteer 68>, <&a55_irqsteer 69>, > > <&a55_irqsteer 70>, > > > + <&a55_irqsteer 71>, <&a55_irqsteer 72>, > > <&a55_irqsteer 73>, > > > + <&a55_irqsteer 74>, <&a55_irqsteer 75>, > > <&a55_irqsteer 76>, > > > + <&a55_irqsteer 77>, <&a55_irqsteer 78>, > > <&a55_irqsteer 79>, > > > + <&a55_irqsteer 80>, <&a55_irqsteer 81>, > > <&a55_irqsteer 82>, > > > + <&a55_irqsteer 83>, <&a55_irqsteer 84>, > > <&a55_irqsteer 85>, > > > + <&a55_irqsteer 86>, <&a55_irqsteer 87>, > > <&a55_irqsteer 88>, > > > + <&a55_irqsteer 89>, <&a55_irqsteer 90>, > > <&a55_irqsteer 91>, > > > + <&a55_irqsteer 92>, <&a55_irqsteer 93>, > > <&a55_irqsteer 94>, > > > + <&a55_irqsteer 95>; > > > + }; > > > + > > > + mu10: mailbox@42430000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x42430000 0x10000>; > > > + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + i3c2: i3c@42520000 { > > > + compatible = "silvaco,i3c-master-v1"; > > > + reg = <0x42520000 0x10000>; > > > + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <3>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > > + <&scmi_clk IMX94_CLK_I3C2SLOW>, > > > + <&dummy>; > > > + clock-names = "pclk", "fast_clk", "slow_clk"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpi2c3: i2c@42530000 { > > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > > + reg = <0x42530000 0x10000>; > > > + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPI2C3>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma2 5 0 0>, <&edma2 6 0 FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpi2c4: i2c@42540000 { > > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > > + reg = <0x42540000 0x10000>; > > > + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPI2C4>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma4 4 0 0>, <&edma4 5 0 FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpspi3: spi@42550000 { > > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > > + reg = <0x42550000 0x10000>; > > > + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPSPI3>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma2 7 0 0>, <&edma2 8 0 FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpspi4: spi@42560000 { > > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > > + reg = <0x42560000 0x10000>; > > > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPSPI4>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma4 6 0 0>, <&edma4 7 0 FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart3: serial@42570000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x42570000 0x1000>; > > > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART3>; > > > + clock-names = "ipg"; > > > + dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 9 0 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart4: serial@42580000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x42580000 0x1000>; > > > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART4>; > > > + clock-names = "ipg"; > > > + dmas = <&edma4 10 0 FSL_EDMA_RX>, <&edma4 9 0 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart5: serial@42590000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x42590000 0x1000>; > > > + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART5>; > > > + clock-names = "ipg"; > > > + dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 11 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart6: serial@425a0000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x425a0000 0x1000>; > > > + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART6>; > > > + clock-names = "ipg"; > > > + dmas = <&edma4 12 0 FSL_EDMA_RX>, <&edma4 11 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + flexcan2: can@425b0000 { > > > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > > > + reg = <0x425b0000 0x10000>; > > > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > > + <&scmi_clk IMX94_CLK_CAN2>; > > > + clock-names = "ipg", "per"; > > > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN2>; > > > + assigned-clock-parents = <&scmi_clk > > IMX94_CLK_SYSPLL1_PFD1_DIV2>; > > > + assigned-clock-rates = <80000000>; > > > + fsl,clk-source = /bits/ 8 <0>; > > > + status = "disabled"; > > > + }; > > > + > > > + flexcan3: can@425e0000 { > > > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > > > + reg = <0x425e0000 0x10000>; > > > + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > > + <&scmi_clk IMX94_CLK_CAN3>; > > > + clock-names = "ipg", "per"; > > > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN3>; > > > + assigned-clock-parents = <&scmi_clk > > IMX94_CLK_SYSPLL1_PFD1_DIV2>; > > > + assigned-clock-rates = <80000000>; > > > + fsl,clk-source = /bits/ 8 <0>; > > > + status = "disabled"; > > > + }; > > > + > > > + flexcan4: can@425f0000 { > > > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > > > + reg = <0x425f0000 0x10000>; > > > + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > > + <&scmi_clk IMX94_CLK_CAN4>; > > > + clock-names = "ipg", "per"; > > > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN4>; > > > + assigned-clock-parents = <&scmi_clk > > IMX94_CLK_SYSPLL1_PFD1_DIV2>; > > > + assigned-clock-rates = <80000000>; > > > + fsl,clk-source = /bits/ 8 <0>; > > > + status = "disabled"; > > > + }; > > > + > > > + flexcan5: can@42600000 { > > > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > > > + reg = <0x42600000 0x10000>; > > > + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > > + <&scmi_clk IMX94_CLK_CAN5>; > > > + clock-names = "ipg", "per"; > > > + assigned-clocks = <&scmi_clk IMX94_CLK_CAN5>; > > > + assigned-clock-parents = <&scmi_clk > > IMX94_CLK_SYSPLL1_PFD1_DIV2>; > > > + assigned-clock-rates = <80000000>; > > > + fsl,clk-source = /bits/ 8 <0>; > > > + status = "disabled"; > > > + }; > > > + > > > + sai2: sai@42650000 { > > > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > > > + reg = <0x42650000 0x10000>; > > > + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > <&dummy>, > > > + <&scmi_clk IMX94_CLK_SAI2>, <&dummy>, > > <&dummy>; > > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > > + dmas = <&edma2 30 0 FSL_EDMA_RX>, <&edma2 29 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + #sound-dai-cells = <0>; > > > + status = "disabled"; > > > + }; > > > + > > > + sai3: sai@42660000 { > > > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > > > + reg = <0x42660000 0x10000>; > > > + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > <&dummy>, > > > + <&scmi_clk IMX94_CLK_SAI3>, <&dummy>, > > <&dummy>; > > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > > + dmas = <&edma2 32 0 FSL_EDMA_RX>, <&edma2 31 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + #sound-dai-cells = <0>; > > > + status = "disabled"; > > > + }; > > > + > > > + sai4: sai@42670000 { > > > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > > > + reg = <0x42670000 0x10000>; > > > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > <&dummy>, > > > + <&scmi_clk IMX94_CLK_SAI4>, <&dummy>, > > <&dummy>; > > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > > + dmas = <&edma2 36 0 FSL_EDMA_RX>, <&edma2 35 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + #sound-dai-cells = <0>; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart7: serial@42690000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x42690000 0x1000>; > > > + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART7>; > > > + clock-names = "ipg"; > > > + dmas = <&edma2 46 0 FSL_EDMA_RX>, <&edma2 45 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart8: serial@426a0000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x426a0000 0x1000>; > > > + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART8>; > > > + clock-names = "ipg"; > > > + dmas = <&edma4 39 0 FSL_EDMA_RX>, <&edma4 38 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpi2c5: i2c@426b0000 { > > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > > + reg = <0x426b0000 0x10000>; > > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPI2C5>, > > > + <&scmi_clk IMX94_CLK_BUSAON>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma2 37 0 0>, <&edma2 38 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpi2c6: i2c@426c0000 { > > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > > + reg = <0x426c0000 0x10000>; > > > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPI2C6>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma4 30 0 0>, <&edma4 31 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpi2c7: i2c@426d0000 { > > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > > + reg = <0x426d0000 0x10000>; > > > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPI2C7>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma2 39 0 0>, <&edma2 40 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpi2c8: i2c@426e0000 { > > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > > + reg = <0x426e0000 0x10000>; > > > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPI2C8>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma4 32 0 0>, <&edma4 33 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpspi5: spi@426f0000 { > > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > > + reg = <0x426f0000 0x10000>; > > > + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPSPI5>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma2 41 0 0>, <&edma2 42 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpspi6: spi@42700000 { > > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > > + reg = <0x42700000 0x10000>; > > > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPSPI6>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma4 34 0 0>, <&edma4 35 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpspi7: spi@42710000 { > > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > > + reg = <0x42710000 0x10000>; > > > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPSPI7>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma2 43 0 0>, <&edma2 44 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpspi8: spi@42720000 { > > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > > + reg = <0x42720000 0x10000>; > > > + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPSPI8>, > > > + <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma4 36 0 0>, <&edma4 37 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + mu11: mailbox@42730000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x42730000 0x10000>; > > > + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + edma4: dma-controller@42df0000 { > > > + compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; > > > + reg = <0x42df0000 0x210000>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + clock-names = "dma"; > > > + #dma-cells = <3>; > > > + dma-channels = <64>; > > > + interrupts-extended = <&a55_irqsteer 128>, > > <&a55_irqsteer 129>, > > > + <&a55_irqsteer 130>, <&a55_irqsteer 131>, > > > + <&a55_irqsteer 132>, <&a55_irqsteer 133>, > > > + <&a55_irqsteer 134>, <&a55_irqsteer 135>, > > > + <&a55_irqsteer 136>, <&a55_irqsteer 137>, > > > + <&a55_irqsteer 138>, <&a55_irqsteer 139>, > > > + <&a55_irqsteer 140>, <&a55_irqsteer 141>, > > > + <&a55_irqsteer 142>, <&a55_irqsteer 143>, > > > + <&a55_irqsteer 144>, <&a55_irqsteer 145>, > > > + <&a55_irqsteer 146>, <&a55_irqsteer 147>, > > > + <&a55_irqsteer 148>, <&a55_irqsteer 149>, > > > + <&a55_irqsteer 150>, <&a55_irqsteer 151>, > > > + <&a55_irqsteer 152>, <&a55_irqsteer 153>, > > > + <&a55_irqsteer 154>, <&a55_irqsteer 155>, > > > + <&a55_irqsteer 156>, <&a55_irqsteer 157>, > > > + <&a55_irqsteer 158>, <&a55_irqsteer 159>, > > > + <&a55_irqsteer 192>, <&a55_irqsteer 193>, > > > + <&a55_irqsteer 194>, <&a55_irqsteer 195>, > > > + <&a55_irqsteer 196>, <&a55_irqsteer 197>, > > > + <&a55_irqsteer 198>, <&a55_irqsteer 199>, > > > + <&a55_irqsteer 200>, <&a55_irqsteer 201>, > > > + <&a55_irqsteer 202>, <&a55_irqsteer 203>, > > > + <&a55_irqsteer 204>, <&a55_irqsteer 205>, > > > + <&a55_irqsteer 206>, <&a55_irqsteer 207>, > > > + <&a55_irqsteer 208>, <&a55_irqsteer 209>, > > > + <&a55_irqsteer 210>, <&a55_irqsteer 211>, > > > + <&a55_irqsteer 212>, <&a55_irqsteer 213>, > > > + <&a55_irqsteer 214>, <&a55_irqsteer 215>, > > > + <&a55_irqsteer 216>, <&a55_irqsteer 217>, > > > + <&a55_irqsteer 218>, <&a55_irqsteer 219>, > > > + <&a55_irqsteer 220>, <&a55_irqsteer 221>, > > > + <&a55_irqsteer 222>, <&a55_irqsteer 223>; > > > + }; > > > + }; > > > + > > > + aips3: bus@42800000 { > > > + compatible = "fsl,aips-bus", "simple-bus"; > > > + reg = <0 0x42800000 0 0x800000>; > > > + ranges = <0x42800000 0x0 0x42800000 0x800000>, > > > + <0x28000000 0x0 0x28000000 0x1000000>; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + > > > + usdhc1: mmc@42850000 { > > > + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; > > > + reg = <0x42850000 0x10000>; > > > + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > > + <&scmi_clk IMX94_CLK_WAKEUPAXI>, > > > + <&scmi_clk IMX94_CLK_USDHC1>; > > > + clock-names = "ipg", "ahb", "per"; > > > + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC1>; > > > + assigned-clock-parents = <&scmi_clk > > IMX94_CLK_SYSPLL1_PFD1>; > > > + assigned-clock-rates = <400000000>; > > > + bus-width = <8>; > > > + fsl,tuning-start-tap = <1>; > > > + fsl,tuning-step = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + usdhc2: mmc@42860000 { > > > + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; > > > + reg = <0x42860000 0x10000>; > > > + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > > + <&scmi_clk IMX94_CLK_WAKEUPAXI>, > > > + <&scmi_clk IMX94_CLK_USDHC2>; > > > + clock-names = "ipg", "ahb", "per"; > > > + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC2>; > > > + assigned-clock-parents = <&scmi_clk > > IMX94_CLK_SYSPLL1_PFD1>; > > > + assigned-clock-rates = <200000000>; > > > + bus-width = <4>; > > > + fsl,tuning-start-tap = <1>; > > > + fsl,tuning-step = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + usdhc3: mmc@42880000 { > > > + compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; > > > + reg = <0x42880000 0x10000>; > > > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, > > > + <&scmi_clk IMX94_CLK_WAKEUPAXI>, > > > + <&scmi_clk IMX94_CLK_USDHC3>; > > > + clock-names = "ipg", "ahb", "per"; > > > + assigned-clocks = <&scmi_clk IMX94_CLK_USDHC3>; > > > + assigned-clock-parents = <&scmi_clk > > IMX94_CLK_SYSPLL1_PFD1>; > > > + assigned-clock-rates = <200000000>; > > > + bus-width = <4>; > > > + fsl,tuning-start-tap = <1>; > > > + fsl,tuning-step = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart9: serial@42a50000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x42a50000 0x1000>; > > > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART10>; > > > + clock-names = "ipg"; > > > + dmas = <&edma2 51 0 FSL_EDMA_RX>, <&edma2 50 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart10: serial@42a60000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x42a60000 0x1000>; > > > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART10>; > > > + clock-names = "ipg"; > > > + dmas = <&edma4 47 0 FSL_EDMA_RX>, <&edma4 46 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart11: serial@42a70000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x42a70000 0x1000>; > > > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART11>; > > > + clock-names = "ipg"; > > > + dmas = <&edma2 53 0 FSL_EDMA_RX>, <&edma2 52 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart12: serial@42a80000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x42a80000 0x1000>; > > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART12>; > > > + clock-names = "ipg"; > > > + dmas = <&edma4 49 0 FSL_EDMA_RX>, <&edma4 48 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + mu12: mailbox@42ac0000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x42ac0000 0x10000>; > > > + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + mu13: mailbox@42ae0000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x42ae0000 0x10000>; > > > + interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + mu14: mailbox@42b00000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x42b00000 0x10000>; > > > + interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + mu15: mailbox@42b20000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x42b20000 0x10000>; > > > + interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + mu16: mailbox@42b40000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x42b40000 0x10000>; > > > + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + mu17: mailbox@42b60000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x42b60000 0x10000>; > > > + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + }; > > > + > > > + gpio2: gpio@43810000 { > > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > > + reg = <0x0 0x43810000 0x0 0x1000>; > > > + #interrupt-cells = <2>; > > > + interrupt-controller; > > > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > > > + #gpio-cells = <2>; > > > + gpio-controller; > > > + gpio-ranges = <&scmi_iomuxc 0 4 32>; > > > + }; > > > + > > > + gpio3: gpio@43820000 { > > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > > + reg = <0x0 0x43820000 0x0 0x1000>; > > > + #interrupt-cells = <2>; > > > + interrupt-controller; > > > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > > > + #gpio-cells = <2>; > > > + gpio-controller; > > > + gpio-ranges = <&scmi_iomuxc 0 36 26>; > > > + }; > > > + > > > + gpio4: gpio@43840000 { > > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > > + reg = <0x0 0x43840000 0x0 0x1000>; > > > + #interrupt-cells = <2>; > > > + interrupt-controller; > > > + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; > > > + #gpio-cells = <2>; > > > + gpio-controller; > > > + gpio-ranges = <&scmi_iomuxc 0 62 4>, <&scmi_iomuxc 4 0 4>, > > > + <&scmi_iomuxc 8 140 12>, <&scmi_iomuxc 20 164 > > 12>; > > > + }; > > > + > > > + gpio5: gpio@43850000 { > > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > > + reg = <0x0 0x43850000 0x0 0x1000>; > > > + #interrupt-cells = <2>; > > > + interrupt-controller; > > > + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; > > > + #gpio-cells = <2>; > > > + gpio-controller; > > > + gpio-ranges = <&scmi_iomuxc 0 108 32>; > > > + }; > > > + > > > + gpio6: gpio@43860000 { > > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > > + reg = <0x0 0x43860000 0x0 0x1000>; > > > + #interrupt-cells = <2>; > > > + interrupt-controller; > > > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; > > > + #gpio-cells = <2>; > > > + gpio-controller; > > > + gpio-ranges = <&scmi_iomuxc 0 66 32>; > > > + }; > > > + > > > + gpio7: gpio@43870000 { > > > + compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; > > > + reg = <0x0 0x43870000 0x0 0x1000>; > > > + #interrupt-cells = <2>; > > > + interrupt-controller; > > > + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; > > > + #gpio-cells = <2>; > > > + gpio-controller; > > > + gpio-ranges = <&scmi_iomuxc 0 98 10>, <&scmi_iomuxc 16 152 > > 12>; > > > + }; > > > + > > > + aips1: bus@44000000 { > > > + compatible = "fsl,aips-bus", "simple-bus"; > > > + reg = <0x0 0x44000000 0x0 0x800000>; > > > + ranges = <0x44000000 0x0 0x44000000 0x800000>; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + > > > + edma1: dma-controller@44000000 { > > > + compatible = "fsl,imx94-edma3", "fsl,imx93-edma3"; > > > + reg = <0x44000000 0x210000>; > > > + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > > > + clock-names = "dma"; > > > + #dma-cells = <3>; > > > + dma-channels = <32>; > > > + }; > > > + > > > + mu1: mailbox@44220000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x44220000 0x10000>; > > > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + system_counter: timer@44290000 { > > > + compatible = "nxp,imx94-sysctr-timer", > > "nxp,imx95-sysctr-timer"; > > > + reg = <0x44290000 0x30000>; > > > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&osc_24m>; > > > + clock-names = "per"; > > > + nxp,no-divider; > > > + }; > > > + > > > + tpm1: pwm@44310000 { > > > + compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; > > > + reg = <0x44310000 0x1000>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > > > + #pwm-cells = <3>; > > > + status = "disabled"; > > > + }; > > > + > > > + tpm2: pwm@44320000 { > > > + compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; > > > + reg = <0x44320000 0x1000>; > > > + clocks = <&scmi_clk IMX94_CLK_TPM2>; > > > + #pwm-cells = <3>; > > > + status = "disabled"; > > > + }; > > > + > > > + i3c1: i3c@44330000 { > > > + compatible = "silvaco,i3c-master-v1"; > > > + reg = <0x44330000 0x10000>; > > > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <3>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>, > > > + <&scmi_clk IMX94_CLK_I3C1SLOW>, > > > + <&dummy>; > > > + clock-names = "pclk", "fast_clk", "slow_clk"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpi2c1: i2c@44340000 { > > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > > + reg = <0x44340000 0x10000>; > > > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPI2C1>, > > > + <&scmi_clk IMX94_CLK_BUSAON>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma1 12 0 0>, <&edma1 13 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpi2c2: i2c@44350000 { > > > + compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; > > > + reg = <0x44350000 0x10000>; > > > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPI2C2>, > > > + <&scmi_clk IMX94_CLK_BUSAON>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma1 14 0 0>, <&edma1 15 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpspi1: spi@44360000 { > > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > > + reg = <0x44360000 0x10000>; > > > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPSPI2>, > > > + <&scmi_clk IMX94_CLK_BUSAON>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma1 16 0 0>, <&edma1 17 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpspi2: spi@44370000 { > > > + compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; > > > + reg = <0x44370000 0x10000>; > > > + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + clocks = <&scmi_clk IMX94_CLK_LPSPI2>, > > > + <&scmi_clk IMX94_CLK_BUSAON>; > > > + clock-names = "per", "ipg"; > > > + dmas = <&edma1 18 0 0>, <&edma1 19 0 > > FSL_EDMA_RX>; > > > + dma-names = "tx", "rx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart1: serial@44380000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x44380000 0x1000>; > > > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART1>; > > > + clock-names = "ipg"; > > > + dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + lpuart2: serial@44390000 { > > > + compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", > > > + "fsl,imx7ulp-lpuart"; > > > + reg = <0x44390000 0x1000>; > > > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_LPUART2>; > > > + clock-names = "ipg"; > > > + dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + status = "disabled"; > > > + }; > > > + > > > + flexcan1: can@443a0000 { > > > + compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; > > > + reg = <0x443a0000 0x10000>; > > > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > > > + status = "disabled"; > > > + }; > > > + > > > + sai1: sai@443b0000 { > > > + compatible = "fsl,imx94-sai", "fsl,imx95-sai"; > > > + reg = <0x443b0000 0x10000>; > > > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>, <&dummy>, > > > + <&scmi_clk IMX94_CLK_SAI1>, <&dummy>, > > > + <&dummy>, <&dummy>; > > > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > > + dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 > > 0>; > > > + dma-names = "rx", "tx"; > > > + #sound-dai-cells = <0>; > > > + status = "disabled"; > > > + }; > > > + > > > + adc1: adc@44530000 { > > > + compatible = "nxp,imx94-adc", "nxp,imx93-adc"; > > > + reg = <0x44530000 0x10000>; > > > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_ADC>; > > > + clock-names = "ipg"; > > > + #io-channel-cells = <1>; > > > + status = "disabled"; > > > + }; > > > + > > > + mu2: mailbox@445b0000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x445b0000 0x1000>; > > > + ranges; > > > + interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + #mbox-cells = <2>; > > > + > > > + sram0: sram@445b1000 { > > > + compatible = "mmio-sram"; > > > + reg = <0x445b1000 0x400>; > > > + ranges = <0x0 0x445b1000 0x400>; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + > > > + scmi_buf0: scmi-sram-section@0 { > > > + compatible = "arm,scmi-shmem"; > > > + reg = <0x0 0x80>; > > > + }; > > > + > > > + scmi_buf1: scmi-sram-section@80 { > > > + compatible = "arm,scmi-shmem"; > > > + reg = <0x80 0x80>; > > > + }; > > > + }; > > > + }; > > > + > > > + mu3: mailbox@445d0000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x445d0000 0x10000>; > > > + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + mu4: mailbox@445f0000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x445f0000 0x10000>; > > > + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + mu6: mailbox@44630000 { > > > + compatible = "fsl,imx94-mu", "fsl,imx95-mu"; > > > + reg = <0x44630000 0x10000>; > > > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > > > + #mbox-cells = <2>; > > > + status = "disabled"; > > > + }; > > > + > > > + a55_irqsteer: interrupt-controller@446a0000 { > > > + compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer"; > > > + reg = <0x446a0000 0x1000>; > > > + #interrupt-cells = <1>; > > > + interrupt-controller; > > > + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSAON>; > > > + clock-names = "ipg"; > > > + fsl,channel = <0>; > > > + fsl,num-irqs = <960>; > > > + }; > > > + }; > > > + > > > + aips4: bus@49000000 { > > > + compatible = "fsl,aips-bus", "simple-bus"; > > > + reg = <0x0 0x49000000 0x0 0x800000>; > > > + ranges = <0x49000000 0x0 0x49000000 0x800000>; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + > > > + wdog3: watchdog@49220000 { > > > + compatible = "fsl,imx94-wdt", "fsl,imx93-wdt"; > > > + reg = <0x49220000 0x10000>; > > > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; > > > + timeout-sec = <40>; > > > + fsl,ext-reset-output; > > > + status = "disabled"; > > > + }; > > > + }; > > > + }; > > > +}; > > > diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi > > > b/arch/arm64/boot/dts/freescale/imx943.dtsi > > > new file mode 100644 > > > index 000000000000..45b8da758e87 > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi > > > @@ -0,0 +1,148 @@ > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > > +/* > > > + * Copyright 2025 NXP > > > + */ > > > + > > > +#include "imx94.dtsi" > > > + > > > +/ { > > > + cpus { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + idle-states { > > > + entry-method = "psci"; > > > + > > > + cpu_pd_wait: cpu-pd-wait { > > > + compatible = "arm,idle-state"; > > > + arm,psci-suspend-param = <0x0010033>; > > > + local-timer-stop; > > > + entry-latency-us = <1000>; > > > + exit-latency-us = <700>; > > > + min-residency-us = <2700>; > > > + wakeup-latency-us = <1500>; > > > + }; > > > + }; > > > + > > > + cpu0: cpu@0 { > > > + compatible = "arm,cortex-a55"; > > > + device_type = "cpu"; > > > + reg = <0x0>; > > > + enable-method = "psci"; > > > + #cooling-cells = <2>; > > > + cpu-idle-states = <&cpu_pd_wait>; > > > + power-domains = <&scmi_perf IMX94_PERF_A55>; > > > + power-domain-names = "perf"; > > > + i-cache-size = <32768>; > > > + i-cache-line-size = <64>; > > > + i-cache-sets = <128>; > > > + d-cache-size = <32768>; > > > + d-cache-line-size = <64>; > > > + d-cache-sets = <128>; > > > + next-level-cache = <&l2_cache_l0>; > > > + }; > > > + > > > + cpu1: cpu@100 { > > > + compatible = "arm,cortex-a55"; > > > + device_type = "cpu"; > > > + reg = <0x100>; > > > + enable-method = "psci"; > > > + #cooling-cells = <2>; > > > + cpu-idle-states = <&cpu_pd_wait>; > > > + power-domains = <&scmi_perf IMX94_PERF_A55>; > > > + power-domain-names = "perf"; > > > + i-cache-size = <32768>; > > > + i-cache-line-size = <64>; > > > + i-cache-sets = <128>; > > > + d-cache-size = <32768>; > > > + d-cache-line-size = <64>; > > > + d-cache-sets = <128>; > > > + next-level-cache = <&l2_cache_l1>; > > > + }; > > > + > > > + cpu2: cpu@200 { > > > + compatible = "arm,cortex-a55"; > > > + device_type = "cpu"; > > > + reg = <0x200>; > > > + enable-method = "psci"; > > > + #cooling-cells = <2>; > > > + cpu-idle-states = <&cpu_pd_wait>; > > > + power-domains = <&scmi_perf IMX94_PERF_A55>; > > > + power-domain-names = "perf"; > > > + i-cache-size = <32768>; > > > + i-cache-line-size = <64>; > > > + i-cache-sets = <128>; > > > + d-cache-size = <32768>; > > > + d-cache-line-size = <64>; > > > + d-cache-sets = <128>; > > > + next-level-cache = <&l2_cache_l2>; > > > + }; > > > + > > > + cpu3: cpu@300 { > > > + compatible = "arm,cortex-a55"; > > > + device_type = "cpu"; > > > + reg = <0x300>; > > > + enable-method = "psci"; > > > + #cooling-cells = <2>; > > > + cpu-idle-states = <&cpu_pd_wait>; > > > + power-domains = <&scmi_perf IMX94_PERF_A55>; > > > + power-domain-names = "perf"; > > > + i-cache-size = <32768>; > > > + i-cache-line-size = <64>; > > > + i-cache-sets = <128>; > > > + d-cache-size = <32768>; > > > + d-cache-line-size = <64>; > > > + d-cache-sets = <128>; > > > + next-level-cache = <&l2_cache_l3>; > > > + }; > > > + > > > + l2_cache_l0: l2-cache-l0 { > > > + compatible = "cache"; > > > + cache-size = <65536>; > > > + cache-line-size = <64>; > > > + cache-sets = <256>; > > > + cache-level = <2>; > > > + cache-unified; > > > + next-level-cache = <&l3_cache>; > > > + }; > > > + > > > + l2_cache_l1: l2-cache-l1 { > > > + compatible = "cache"; > > > + cache-size = <65536>; > > > + cache-line-size = <64>; > > > + cache-sets = <256>; > > > + cache-level = <2>; > > > + cache-unified; > > > + next-level-cache = <&l3_cache>; > > > + }; > > > + > > > + l2_cache_l2: l2-cache-l2 { > > > + compatible = "cache"; > > > + cache-size = <65536>; > > > + cache-line-size = <64>; > > > + cache-sets = <256>; > > > + cache-level = <2>; > > > + cache-unified; > > > + next-level-cache = <&l3_cache>; > > > + }; > > > + > > > + l2_cache_l3: l2-cache-l3 { > > > + compatible = "cache"; > > > + cache-size = <65536>; > > > + cache-line-size = <64>; > > > + cache-sets = <256>; > > > + cache-level = <2>; > > > + cache-unified; > > > + next-level-cache = <&l3_cache>; > > > + }; > > > + > > > + l3_cache: l3-cache { > > > + compatible = "cache"; > > > + cache-size = <1048576>; > > > + cache-line-size = <64>; > > > + cache-sets = <1024>; > > > + cache-level = <3>; > > > + cache-unified; > > > + }; > > > + }; > > > +}; > > > -- > > > 2.34.1 > > > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-04-11 15:05 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
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2025-04-10 6:28 [PATCH v5 0/3] Add i.MX943 basic dts support Jacky Bai
2025-04-10 6:28 ` [PATCH v5 1/3] dt-bindings: arm: fsl: add i.MX943 EVK board Jacky Bai
2025-04-10 6:28 ` [PATCH v5 3/3] arm64: dts: freescale: Add minimal dts support for imx943 evk Jacky Bai
2025-04-10 6:46 ` Alexander Stein
2025-04-10 7:48 ` Jacky Bai
[not found] ` <20250410062826.3344545-3-ping.bai@nxp.com>
2025-04-10 15:41 ` [PATCH v5 2/3] arm64: dts: freescale: Add basic dtsi for imx943 Frank Li
2025-04-11 1:46 ` Jacky Bai
2025-04-11 14:44 ` Frank Li
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