From: Paul Walmsley <pjw@kernel.org>
To: Xixin Liu <liuxixin@kylinos.cn>
Cc: linux-riscv@lists.infradead.org, atish.patra@linux.dev,
anup@brainfault.org, will@kernel.org, mark.rutland@arm.com,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] perf: RISC-V: store available counter mask as bitmap
Date: Tue, 1 Sep 2026 12:52:50 -0600 (MDT) [thread overview]
Message-ID: <460ddaff-bdad-0eb6-a504-1ea43689d6dc@kernel.org> (raw)
In-Reply-To: <prpmask02cmap.v2.1786434000.git.liuxixin@kylinos.cn>
Hi,
On Tue, 18 Aug 2026, Xixin Liu wrote:
> The available-counter mask was a single unsigned long, but iteration
> uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object.
> Filling with an unsigned-long bit at index 32 and above is also wrong.
>
> Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word
> into CFG_MATCH when checking events, when allocating an index, and when
> stopping all counters. Set the counter base to i times BITS_PER_LONG.
> Share the CFG_MATCH ecall through a small helper so the 32-bit argument
> split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits
> above XLEN set, so the first word alone is not enough.
This patch results in several 'checkpatch.pl --strict' "check" messages.
I've fixed them in the queued patches, but please run 'checkpatch.pl
--strict' next time.
thanks,
- Paul
next prev parent reply other threads:[~2026-09-01 18:54 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-07 8:50 [PATCH v1 0/2] perf: RISC-V: fix SBI PMU masks for RV32 Xixin Liu
2026-08-07 8:50 ` [PATCH v1 2/2] perf: RISC-V: store available counter mask as bitmap Xixin Liu
2026-08-08 0:32 ` Paul Walmsley
2026-08-18 9:15 ` Xixin Liu
2026-08-07 8:50 ` [PATCH v1 1/2] perf: RISC-V: use BIT_ULL for u64 overflow masks Xixin Liu
2026-08-08 0:46 ` Paul Walmsley
2026-08-18 9:10 ` [PATCH v2 0/2] perf: RISC-V: fix SBI PMU masks for RV32 Xixin Liu
2026-08-18 9:10 ` [PATCH v2 2/2] perf: RISC-V: store available counter mask as bitmap Xixin Liu
2026-09-01 1:20 ` patchwork-bot+linux-riscv
2026-09-01 18:52 ` Paul Walmsley [this message]
2026-09-02 0:55 ` Xixin Liu
2026-08-18 9:10 ` [PATCH v2 1/2] perf: RISC-V: use BIT_ULL for u64 overflow masks Xixin Liu
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