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From: Xixin Liu <liuxixin@kylinos.cn>
To: pjw@kernel.org
Cc: linux-riscv@lists.infradead.org, atish.patra@linux.dev,
	anup@brainfault.org, will@kernel.org, mark.rutland@arm.com,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
	linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	liuxixin@kylinos.cn
Subject: Re: [PATCH v2 2/2] perf: RISC-V: store available counter mask as bitmap
Date: Wed, 2 Sep 2026 08:55:00 +0800	[thread overview]
Message-ID: <reply.pjw.pmumask22chk.1787383200.git.liuxixin@kylinos.cn> (raw)
In-Reply-To: <460ddaff-bdad-0eb6-a504-1ea43689d6dc@kernel.org>

Hi Paul,

Thanks for fixing those in your queued copy. I will run checkpatch.pl
--strict before send going forward.

Thanks,
Xixin



      reply	other threads:[~2026-09-02  1:00 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-07  8:50 [PATCH v1 0/2] perf: RISC-V: fix SBI PMU masks for RV32 Xixin Liu
2026-08-07  8:50 ` [PATCH v1 2/2] perf: RISC-V: store available counter mask as bitmap Xixin Liu
2026-08-08  0:32   ` Paul Walmsley
2026-08-18  9:15     ` Xixin Liu
2026-08-07  8:50 ` [PATCH v1 1/2] perf: RISC-V: use BIT_ULL for u64 overflow masks Xixin Liu
2026-08-08  0:46   ` Paul Walmsley
2026-08-18  9:10 ` [PATCH v2 0/2] perf: RISC-V: fix SBI PMU masks for RV32 Xixin Liu
2026-08-18  9:10   ` [PATCH v2 1/2] perf: RISC-V: use BIT_ULL for u64 overflow masks Xixin Liu
2026-08-18  9:10   ` [PATCH v2 2/2] perf: RISC-V: store available counter mask as bitmap Xixin Liu
2026-09-01  1:20     ` patchwork-bot+linux-riscv
2026-09-01 18:52     ` Paul Walmsley
2026-09-02  0:55       ` Xixin Liu [this message]

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