From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: "Chen-Yu Tsai" <wenst@chromium.org>,
"Nícolas F. R. A. Prado" <nfraprado@collabora.com>
Cc: Stephen Boyd <sboyd@kernel.org>,
kernel@collabora.com, Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Ikjoon Jang <ikjn@chromium.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Michael Turquette <mturquette@baylibre.com>,
Miles Chen <miles.chen@mediatek.com>,
Ran Jianping <ran.jianping@zte.com.cn>,
Weiyi Lu <weiyi.lu@mediatek.com>,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org
Subject: Re: [PATCH] clk: mediatek: Don't check HW status for mt8192/5's imp_iic_wrap clocks
Date: Tue, 12 Jul 2022 12:55:42 +0200 [thread overview]
Message-ID: <473aa749-fcfe-bd38-0d83-95375aeef8a3@collabora.com> (raw)
In-Reply-To: <CAGXv+5Enkz20o8BLXmnCUBmB930sH+20U=XvTWA82neaiqqc2A@mail.gmail.com>
Il 12/07/22 12:44, Chen-Yu Tsai ha scritto:
> Hi,
>
> On Tue, Jul 12, 2022 at 4:57 AM Nícolas F. R. A. Prado
> <nfraprado@collabora.com> wrote:
>>
>> The imp_iic_wrap clocks on mt8192/mt8195 require that the i2c_sel parent
>> clock be enabled before their hardware status can be checked. Since this
>> wasn't taken into account, reading from the clk_summary debugfs file
>> would cause the system to completely freeze.
>>
>> Assuming that this clock is managed only by the kernel, and not by any
>> firmware, simply drop the is_enabled() optional callback and instead
>> rely on the enable count for the imp_iic_wrap clocks.
>
> That's the wrong way to go about it.
>
> The I2C clocks already have the CLK_OPS_PARENT_ENABLE flag set. So the
> issue is that somewhere in the clk core, a piece of code is not honoring
> that flag.
>
> And it seems that's in more than one place.
>
Uhm, you're right. I gave my Tested-by, but not a Reviewed-by because I
wasn't really convinced about this solution being the best.
Now that I think of it, the solution may be as simple as:
clk.c
static bool clk_core_is_enabled(struct clk_core *core)
{
bool ret = false;
/*
* If this clock needs parent enabled, but its parent is
* off, we directly return false for two reasons:
* 1. This clock being enabled would be impossible
* 2. The platform may crash for unclocked access while
* reading the status of this clock (where a .is_enabled
* callback is provided).
*/
if (core->flags & CLK_OPS_PARENT_ENABLE &&
!clk_core_is_enabled(core->parent))
return false;
... etc etc etc ...
}
Nícolas, did you try this approach?
> Regards
> ChenYu
>
>> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>>
>> ---
>>
>> drivers/clk/mediatek/clk-gate.c | 6 ++++++
>> drivers/clk/mediatek/clk-gate.h | 1 +
>> drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c | 2 +-
>> drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c | 2 +-
>> 4 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
>> index 421806236228..8e7c719a69b3 100644
>> --- a/drivers/clk/mediatek/clk-gate.c
>> +++ b/drivers/clk/mediatek/clk-gate.c
>> @@ -124,6 +124,12 @@ static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
>> mtk_cg_clr_bit_no_setclr(hw);
>> }
>>
>> +const struct clk_ops mtk_clk_gate_ops_setclr_counted = {
>> + .enable = mtk_cg_enable,
>> + .disable = mtk_cg_disable,
>> +};
>> +EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_counted);
>> +
>> const struct clk_ops mtk_clk_gate_ops_setclr = {
>> .is_enabled = mtk_cg_bit_is_cleared,
>> .enable = mtk_cg_enable,
>> diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
>> index d9897ef53528..b5502b2911f5 100644
>> --- a/drivers/clk/mediatek/clk-gate.h
>> +++ b/drivers/clk/mediatek/clk-gate.h
>> @@ -19,6 +19,7 @@ extern const struct clk_ops mtk_clk_gate_ops_setclr;
>> extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
>> extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
>> extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
>> +extern const struct clk_ops mtk_clk_gate_ops_setclr_counted;
>>
>> struct mtk_gate_regs {
>> u32 sta_ofs;
>> diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c
>> index 700356ac6a58..900ee601169c 100644
>> --- a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c
>> +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c
>> @@ -20,7 +20,7 @@ static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
>>
>> #define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
>> GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
>> - &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
>> + &mtk_clk_gate_ops_setclr_counted, CLK_OPS_PARENT_ENABLE)
>>
>> static const struct mtk_gate imp_iic_wrap_c_clks[] = {
>> GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C10, "imp_iic_wrap_c_i2c10", "infra_i2c0", 0),
>> diff --git a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
>> index fbc809d05072..e50a77b844f4 100644
>> --- a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
>> +++ b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c
>> @@ -18,7 +18,7 @@ static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
>>
>> #define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
>> GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
>> - &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
>> + &mtk_clk_gate_ops_setclr_counted, CLK_OPS_PARENT_ENABLE)
>>
>> static const struct mtk_gate imp_iic_wrap_s_clks[] = {
>> GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C5, "imp_iic_wrap_s_i2c5", "top_i2c", 0),
>> --
>> 2.37.0
>>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-07-12 10:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-11 20:57 [PATCH] clk: mediatek: Don't check HW status for mt8192/5's imp_iic_wrap clocks Nícolas F. R. A. Prado
2022-07-12 10:41 ` AngeloGioacchino Del Regno
2022-07-12 10:44 ` Chen-Yu Tsai
2022-07-12 10:55 ` AngeloGioacchino Del Regno [this message]
2022-07-12 10:56 ` Chen-Yu Tsai
2022-07-12 10:57 ` AngeloGioacchino Del Regno
2022-07-12 14:00 ` Nícolas F. R. A. Prado
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=473aa749-fcfe-bd38-0d83-95375aeef8a3@collabora.com \
--to=angelogioacchino.delregno@collabora.com \
--cc=chun-jie.chen@mediatek.com \
--cc=ikjn@chromium.org \
--cc=kernel@collabora.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=miles.chen@mediatek.com \
--cc=mturquette@baylibre.com \
--cc=nfraprado@collabora.com \
--cc=ran.jianping@zte.com.cn \
--cc=sboyd@kernel.org \
--cc=weiyi.lu@mediatek.com \
--cc=wenst@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox