[PATCH v3 0/2] ARM: dts: aspeed: ASRock Rack X470D4U BMC support

[PATCH v3 0/2] ARM: dts: aspeed: ASRock Rack X470D4U BMC support

[Tan Siewert]

This series adds support for the BMC of the ASRock Rack X470D4U mainboard,
which uses an ASPEED AST2500.

The mainboard exists in three known flavors, the "normal" X470D4U, the
X470D4U2-2T (with 2x10G RJ45) and the X470D4U2/1N1 (an ODM version with
2x1G RJ45 that is now available in retail). The 1N1 version also has a 64MB
BMC SPI by default, but they are all swappable.

There are two device trees, one that has all the config and uses a 32MB
flash layout, and another one called "data64" (similar to facebook-fuji)
that uses the 64MB flash layout.

Please note that this board has been fully reverse-engineered.

Thanks,
Tan

Signed-off-by: Tan Siewert <tan@siewert.io>
---
Changes in v3:
- remove mdio pinctrl from mac1 nc-si interface [Andrew Jeffrey]
- remove "st,24c128" compatibility from fru eeprom [Tan]
- enable uart1-4 [Tan]
- add a data64 tree as alternative for boards with a 64M SPI [Zev]
- add hog to bmc-ready GPIO pin as required by the host BIOS [Tan]
- fix offenses reported by scripts/dtc/dt-check-style --mode strict [Tan]
- Link to v2: https://lore.kernel.org/all/20251011112124.17588-1-tan@siewert.io/

Changes in v2:
- fix led node names [robh]
- fix missing gfx memory region and other fixable dtbs_check issues [Tan]
- Link to v1: https://lore.kernel.org/all/20250919185621.6647-1-tan@siewert.io/

To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Joel Stanley <joel@jms.id.au>
To: Andrew Jeffery <andrew@codeconstruct.com.au>
Cc: Zev Weiss <zev@bewilderbeest.net>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-aspeed@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org

---
Tan Siewert (2):
      dt-bindings: arm: aspeed: add ASRock X470D4U BMC
      ARM: dts: aspeed: add asrock x470d4u bmc

 .../devicetree/bindings/arm/aspeed/aspeed.yaml     |   2 +
 arch/arm/boot/dts/aspeed/Makefile                  |   2 +
 .../aspeed/aspeed-bmc-asrock-x470d4u-data64.dts    |  15 +
 .../boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts  | 381 +++++++++++++++++++++
 4 files changed, 400 insertions(+)
---
base-commit: 749c34389679f8d56cb200a69b62f9a64670034f
change-id: 20251017-ts-x470d4u-54b9e98e4333

Best regards,
--  
Tan Siewert <tan@siewert.io>

[PATCH v3 1/2] dt-bindings: arm: aspeed: add ASRock X470D4U BMC

[Tan Siewert]

Document ASRock's X470D4U BMC board compatible.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tan Siewert <tan@siewert.io>
---
 Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index dd7996960de3..277c0e03cf48 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -40,6 +40,8 @@ properties:
               - asrock,e3c256d4i-bmc
               - asrock,romed8hm3-bmc
               - asrock,spc621d8hm3-bmc
+              - asrock,x470d4u-bmc
+              - asrock,x470d4u-data64-bmc
               - asrock,x570d4u-bmc
               - bytedance,g220a-bmc
               - facebook,cmm-bmc

-- 
2.54.0

[PATCH v3 2/2] ARM: dts: aspeed: add asrock x470d4u bmc

[Tan Siewert]

The ASRock Rack X470D4U X470D4U is a single-socket X470-based microATX
motherboard for Ryzen processors with an AST2500 BMC and either 32MB or
64MB SPI flash.

This mainboard exists in three known "flavors" which only differ in the
used host NIC, the BMC SPI size and some parts that may be un-populated.

To allow the use of the full SPI flash, add two trees, one of which has
the 32M layout with the base config, and a 64M tree that includes the
base tree.

Signed-off-by: Tan Siewert <tan@siewert.io>
---
 arch/arm/boot/dts/aspeed/Makefile                  |   2 +
 .../aspeed/aspeed-bmc-asrock-x470d4u-data64.dts    |  15 +
 .../boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts  | 381 +++++++++++++++++++++
 3 files changed, 398 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
index 6b68671f9379..e27d33e85fb2 100644
--- a/arch/arm/boot/dts/aspeed/Makefile
+++ b/arch/arm/boot/dts/aspeed/Makefile
@@ -15,6 +15,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-asrock-paul-ipmi-card.dtb \
 	aspeed-bmc-asrock-romed8hm3.dtb \
 	aspeed-bmc-asrock-spc621d8hm3.dtb \
+	aspeed-bmc-asrock-x470d4u.dtb \
+	aspeed-bmc-asrock-x470d4u-data64.dtb \
 	aspeed-bmc-asrock-x570d4u.dtb \
 	aspeed-bmc-asus-kommando-ipmi-card.dtb \
 	aspeed-bmc-asus-x4tf.dtb \
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u-data64.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u-data64.dts
new file mode 100644
index 000000000000..6f11aeab087c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u-data64.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "aspeed-bmc-asrock-x470d4u.dts"
+
+/ {
+	compatible = "asrock,x470d4u-data64-bmc", "aspeed,ast2500";
+	model = "Asrock Rack X470D4U-series BMC (64MB store)";
+};
+
+&fmc {
+	flash@0 {
+		/delete-node/partitions;
+#include "openbmc-flash-layout-64.dtsi"
+	};
+};
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts
new file mode 100644
index 000000000000..80fb2b7c1e0c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "asrock,x470d4u-bmc", "aspeed,ast2500";
+	model = "Asrock Rack X470D4U-series BMC";
+
+	aliases {
+		serial4 = &uart5;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+	};
+
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>,
+			      <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>,
+			      <&adc 10>, <&adc 11>, <&adc 12>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-heartbeat {
+			/* led-heartbeat-n */
+			gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>;
+			label = "platform:heartbeat";
+			linux,default-trigger = "timer";
+		};
+
+		led-identify {
+			/* led-identify-n */
+			gpios = <&gpio ASPEED_GPIO(D, 6) GPIO_ACTIVE_LOW>;
+			label = "platform:identify";
+		};
+
+		led-systemfault {
+			/* led-fault-n */
+			gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>;
+			label = "platform:systemfault";
+			panic-indicator;
+		};
+	};
+
+	memory@80000000 {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pci_memory: region@9a000000 {
+			reg = <0x9a000000 0x00010000>; /* 64K */
+			no-map;
+		};
+
+		gfx_memory: framebuffer {
+			compatible = "shared-dma-pool";
+			alignment = <0x01000000>;
+			reusable;
+			size = <0x01000000>;
+		};
+
+		video_engine_memory: jpegbuffer {
+			compatible = "shared-dma-pool";
+			alignment = <0x01000000>;
+			reusable;
+			size = <0x02800000>;	/* 40M */
+		};
+	};
+};
+
+&adc {
+	pinctrl-0 = <&pinctrl_adc0_default	/* 3VSB */
+		    &pinctrl_adc1_default	/* 5VSB */
+		    &pinctrl_adc2_default	/* VCPU */
+		    &pinctrl_adc3_default	/* VSOC */
+		    &pinctrl_adc4_default	/* VCCM */
+		    &pinctrl_adc5_default	/* APU-VDDP */
+		    &pinctrl_adc6_default	/* 1V05-PROM-S5 */
+		    &pinctrl_adc7_default	/* 2V5-PROM */
+		    &pinctrl_adc8_default	/* 1V05-PROM-RUN */
+		    &pinctrl_adc9_default	/* VBAT */
+		    &pinctrl_adc10_default	/* 3V */
+		    &pinctrl_adc11_default	/* 5V */
+		    &pinctrl_adc12_default>;	/* 12V */
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&fmc {
+	status = "okay";
+
+	flash@0 {
+		label = "bmc";
+		spi-max-frequency = <10000000>;
+		m25p,fast-read;
+
+		status = "okay";
+
+#include "openbmc-flash-layout.dtsi"
+	};
+};
+
+&gfx {
+	memory-region = <&gfx_memory>;
+
+	status = "okay";
+};
+
+&gpio {
+	gpio-line-names =
+	/*  A */ "input-locatorled-n", "", "", "", "", "", "", "",
+	/*  B */ "input-bios-post-cmplt-n", "", "", "", "", "", "", "",
+	/*  C */ "", "", "", "", "", "", "", "",
+	/*  D */ "button-power-n", "control-power-n", "button-reset-n",
+		 "control-reset-n", "", "", "", "",
+	/*  E */ "", "", "", "", "", "", "", "",
+	/*  F */ "", "", "", "", "", "", "", "",
+	/*  G */ "output-hwm-vbat-enable", "input-id0-n", "input-id1-n",
+		 "input-id2-n", "input-aux-smb-alert-n", "",
+		 "input-psu-smb-alert-n", "",
+	/*  H */ "", "", "", "", "input-mfg-mode-n", "",
+		 "led-heartbeat-n", "input-case-open-n",
+	/*  I */ "", "", "", "", "", "", "", "",
+	/*  J */ "output-bmc-ready-n", "output-bios-cs-n", "", "", "", "",
+		 "", "",
+	/*  K */ "", "", "", "", "", "", "", "",
+	/*  L */ "", "", "", "", "", "", "", "",
+	/*  M */ "", "", "", "", "", "", "", "",
+	/*  N */ "", "", "", "", "", "", "", "",
+	/*  O */ "", "", "", "", "", "", "", "",
+	/*  P */ "", "", "", "", "", "", "", "",
+	/*  Q */ "", "", "", "", "input-bmc-smb-present-n", "", "",
+		 "input-pcie-wake-n",
+	/*  R */ "", "", "", "", "", "", "", "",
+	/*  S */ "input-bmc-pchhot-n", "", "", "", "", "", "", "",
+	/*  T */ "", "", "", "", "", "", "", "",
+	/*  U */ "", "", "", "", "", "", "", "",
+	/*  V */ "", "", "", "", "", "", "", "",
+	/*  W */ "", "", "", "", "", "", "", "",
+	/*  X */ "", "", "", "", "", "", "", "",
+	/*  Y */ "input-sleep-s3-n", "input-sleep-s5-n", "", "", "", "",
+		 "", "",
+	/*  Z */ "", "", "led-fault-n", "output-bmc-throttle-n", "", "",
+		 "", "",
+	/* AA */ "input-cpu1-thermtrip-latch-n", "",
+		 "input-cpu1-prochot-n", "", "", "", "", "",
+	/* AB */ "", "input-power-good", "", "hard-power-off", "", "", "", "",
+	/* AC */ "", "", "", "", "", "", "", "";
+
+	bmc-ready-hog {
+		gpio-hog;
+		gpios = <ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
+		output-high;
+	};
+};
+
+&i2c0 {
+	/* SMBus on auxiliary panel header (AUX_PANEL1) */
+	status = "okay";
+};
+
+&i2c1 {
+	/* Hardware monitoring SMBus */
+	status = "okay";
+
+	w83773g@4c {
+		compatible = "nuvoton,w83773g";
+		reg = <0x4c>;
+	};
+};
+
+&i2c2 {
+	/* PSU SMBus (PSU_SMB1) */
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c6 {
+	/* SMBus on BMC connector (BMC_SMB_1) */
+	status = "okay";
+};
+
+&i2c7 {
+	/* FRU EEPROM */
+	status = "okay";
+
+	eeprom@57 {
+		compatible = "atmel,24c128";
+		reg = <0x57>;
+		pagesize = <16>;
+
+		nvmem-layout {
+			compatible = "fixed-layout";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			eth0_macaddress: macaddress@3f80 {
+				reg = <0x3f80 6>;
+			};
+
+			eth1_macaddress: macaddress@3f88 {
+				reg = <0x3f88 6>;
+			};
+		};
+	};
+};
+
+&kcs3 {
+	aspeed,lpc-io-reg = <0xca2>;
+
+	status = "okay";
+};
+
+&lpc_ctrl {
+	status = "okay";
+};
+
+&lpc_snoop {
+	snoop-ports = <0x80>;
+
+	status = "okay";
+};
+
+&mac0 {
+	nvmem-cells = <&eth0_macaddress>;
+	nvmem-cell-names = "mac-address";
+
+	pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&mac1 {
+	nvmem-cells = <&eth1_macaddress>;
+	nvmem-cell-names = "mac-address";
+
+	pinctrl-0 = <&pinctrl_rmii2_default>;
+	pinctrl-names = "default";
+	use-ncsi;
+
+	status = "okay";
+};
+
+&pwm_tacho {
+	pinctrl-0 = <&pinctrl_pwm0_default
+		    &pinctrl_pwm1_default
+		    &pinctrl_pwm2_default
+		    &pinctrl_pwm3_default
+		    &pinctrl_pwm4_default
+		    &pinctrl_pwm5_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	fan@0 {
+		/* FAN1 (4-pin) */
+		reg = <0x00>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+	};
+
+	fan@1 {
+		/* FAN2 (4-pin) */
+		reg = <0x01>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+	};
+
+	fan@2 {
+		/* FAN3 (4-pin) */
+		reg = <0x02>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+	};
+
+	fan@3 {
+		/* FAN4 (6-pin) */
+		reg = <0x03>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>;
+	};
+
+	fan@4 {
+		/* FAN5 (6-pin) */
+		reg = <0x04>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0d>;
+	};
+
+	fan@5 {
+		/* FAN6 (6-pin) */
+		reg = <0x05>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0e>;
+	};
+};
+
+&p2a {
+	memory-region = <&pci_memory>;
+
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-0 = <&pinctrl_spi1_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash@0 {
+		label = "bios";
+		/* Frequency extracted from original ROM */
+		spi-max-frequency = <24000000>; /* 24 MHz */
+		m25p,fast-read;
+
+		status = "okay";
+	};
+};
+
+&uhci {
+	status = "okay";
+};
+
+&vhub {
+	status = "okay";
+};
+
+&video {
+	memory-region = <&video_engine_memory>;
+
+	status = "okay";
+};
+
+&vuart {
+	aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+	aspeed,lpc-io-reg = <0x2f8>;
+
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&uart_routing {
+	status = "okay";
+};

-- 
2.54.0

Re: [PATCH v3 2/2] ARM: dts: aspeed: add asrock x470d4u bmc

[Zev Weiss]

Hi Tan,

Looks good overall to me, just a couple small notes below...

On Wed, Aug 12, 2026 at 01:28:27PM PDT, Tan Siewert wrote:
>The ASRock Rack X470D4U X470D4U is a single-socket X470-based microATX
>motherboard for Ryzen processors with an AST2500 BMC and either 32MB or
>64MB SPI flash.
>
>This mainboard exists in three known "flavors" which only differ in the
>used host NIC, the BMC SPI size and some parts that may be un-populated.
>
>To allow the use of the full SPI flash, add two trees, one of which has
>the 32M layout with the base config, and a 64M tree that includes the
>base tree.
>
>Signed-off-by: Tan Siewert <tan@siewert.io>
>---
> arch/arm/boot/dts/aspeed/Makefile                  |   2 +
> .../aspeed/aspeed-bmc-asrock-x470d4u-data64.dts    |  15 +
> .../boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts  | 381 +++++++++++++++++++++
> 3 files changed, 398 insertions(+)
>
>diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
>index 6b68671f9379..e27d33e85fb2 100644
>--- a/arch/arm/boot/dts/aspeed/Makefile
>+++ b/arch/arm/boot/dts/aspeed/Makefile
>@@ -15,6 +15,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
> 	aspeed-bmc-asrock-paul-ipmi-card.dtb \
> 	aspeed-bmc-asrock-romed8hm3.dtb \
> 	aspeed-bmc-asrock-spc621d8hm3.dtb \
>+	aspeed-bmc-asrock-x470d4u.dtb \
>+	aspeed-bmc-asrock-x470d4u-data64.dtb \
> 	aspeed-bmc-asrock-x570d4u.dtb \
> 	aspeed-bmc-asus-kommando-ipmi-card.dtb \
> 	aspeed-bmc-asus-x4tf.dtb \
>diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u-data64.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u-data64.dts
>new file mode 100644
>index 000000000000..6f11aeab087c
>--- /dev/null
>+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u-data64.dts
>@@ -0,0 +1,15 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+
>+#include "aspeed-bmc-asrock-x470d4u.dts"
>+
>+/ {
>+	compatible = "asrock,x470d4u-data64-bmc", "aspeed,ast2500";
>+	model = "Asrock Rack X470D4U-series BMC (64MB store)";

Nit: for consistency with how they spell it, and (at least *most* of) 
the other aspeed-bmc-asrock-*.dts files, I'd suggest "ASRock" instead of 
"Asrock".  (And IMO s/store/flash/ would be a touch clearer.)

Also, looks like the other nearby DTS files pretty consistently have 
compatible & model in the opposite order, so matching that might be nice 
too.

>+};
>+
>+&fmc {
>+	flash@0 {
>+		/delete-node/partitions;
>+#include "openbmc-flash-layout-64.dtsi"
>+	};
>+};
>diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts
>new file mode 100644
>index 000000000000..80fb2b7c1e0c
>--- /dev/null
>+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts

<snip>

>+
>+	fan@3 {
>+		/* FAN4 (6-pin) */
>+		reg = <0x03>;
>+		aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>;
>+	};
>+
>+	fan@4 {
>+		/* FAN5 (6-pin) */
>+		reg = <0x04>;
>+		aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0d>;
>+	};
>+
>+	fan@5 {
>+		/* FAN6 (6-pin) */
>+		reg = <0x05>;
>+		aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0e>;
>+	};
>+};

Just to confirm, skipping channel 0xc here is intentional I assume?  
(Most other related platforms have them contiguously numbered, but not 
all, so another slight oddity wouldn't be too shocking.)


Thanks,
Zev

Re: [PATCH v3 2/2] ARM: dts: aspeed: add asrock x470d4u bmc

[Tan Siewert]

Hi Zev,

Many thanks for your review!

On 16.08.26 06:49, Zev Weiss wrote:
> On Wed, Aug 12, 2026 at 01:28:27PM PDT, Tan Siewert wrote:
>> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u- 
>> data64.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u- 
>> data64.dts
>> new file mode 100644
>> index 000000000000..6f11aeab087c
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u-data64.dts
>> @@ -0,0 +1,15 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +
>> +#include "aspeed-bmc-asrock-x470d4u.dts"
>> +
>> +/ {
>> +    compatible = "asrock,x470d4u-data64-bmc", "aspeed,ast2500";
>> +    model = "Asrock Rack X470D4U-series BMC (64MB store)";
> 
> Nit: for consistency with how they spell it, and (at least *most* of) 
> the other aspeed-bmc-asrock-*.dts files, I'd suggest "ASRock" instead of 
> "Asrock".  (And IMO s/store/flash/ would be a touch clearer.)
> 

Agreed on both, will fix it in v4.

> Also, looks like the other nearby DTS files pretty consistently have 
> compatible & model in the opposite order, so matching that might be nice 
> too.

This is something that was reported by `scripts/dtc/dt-style-check 
--mode strict`. Depending on how much time I have next week I'll look 
into fixing the dtc offsenses for arm/dts/aspeed (tho that'd come from 
my employer email).

> 
>> +};
>> +
>> +&fmc {
>> +    flash@0 {
>> +        /delete-node/partitions;
>> +#include "openbmc-flash-layout-64.dtsi"
>> +    };
>> +};
>> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts b/ 
>> arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts
>> new file mode 100644
>> index 000000000000..80fb2b7c1e0c
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x470d4u.dts
> 
> <snip>
> 
>> +
>> +    fan@3 {
>> +        /* FAN4 (6-pin) */
>> +        reg = <0x03>;
>> +        aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>;
>> +    };
>> +
>> +    fan@4 {
>> +        /* FAN5 (6-pin) */
>> +        reg = <0x04>;
>> +        aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0d>;
>> +    };
>> +
>> +    fan@5 {
>> +        /* FAN6 (6-pin) */
>> +        reg = <0x05>;
>> +        aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0e>;
>> +    };
>> +};
> 
> Just to confirm, skipping channel 0xc here is intentional I assume? 
> (Most other related platforms have them contiguously numbered, but not 
> all, so another slight oddity wouldn't be too shocking.)

The skip is intentional. That is what I found out during reverse 
engineering the SDR file in the vendor firmware.

Cheers,
Tan