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From: Mark Brown <broonie@kernel.org>
To: Bill Roberts <bill.roberts@foss.arm.com>
Cc: Jesse Huang <jesse.huang@sifive.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	linux-arm-kernel@lists.infradead.org,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	linux-hardening@vger.kernel.org, linux-api@vger.kernel.org,
	dave.hansen@linux.intel.com, rick.p.edgecombe@intel.com,
	debug@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com
Subject: Re: Shadow Stack Locking Semantics between arch's
Date: Wed, 9 Sep 2026 19:06:09 +0100	[thread overview]
Message-ID: <522bcf96-499c-491b-aaf0-34e6bbd42929@sirena.org.uk> (raw)
In-Reply-To: <0ef9f4ab-4c9f-4089-bed3-f7726ec97804@foss.arm.com>

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On Wed, Sep 09, 2026 at 12:57:57PM -0500, Bill Roberts wrote:

> > > unsigned long locked = 0x2; // Kernel Task State -> LOCK WRITE
> > > unsigned long cur_val = 0x3; // Kernel Task State -> WRITE and SHADOWSTACK
> > > ENABLED
> > > unsigned long new_val = 0x0; // Userspace Feature Change via syscall ->
> > > DISABLE
> > > | x86-64 | risc-v | arm64 |
> > > | ---------- | -------- | --------- |
> > > | Works  | Fails  | Fails     |

> > I would not have expected that combination to work at all with the
> > prctl() (as opposed to arch_prctl()) interface TBH, if you've locked
> > write on you shouldn't be able to disable it.  The reason that works on
> > x86 at the minute is that for x86 you can only change one bit at a time
> > so the new value when disabling is effectively 0x2, not 0x0.

> Yes, this is exactly what I am pointing out. Implementation aside, is that
> the behavior we want?

It seems more helpful to support changing more than one bit at once.

> > I think for ABI compatibility RISC-V will have to continue accepting 0
> > as being equivalent to locking PR_SHADOW_STACK_ENABLE (or everything,
> > but it only supports that one bit right now).

> TL;DR - No users, lets fix it before risc-v lands the userspace side IIUC

Oh, that would be even better if we could do that!  Thanks for checking
the userspace situation.

> > > 3. riscv should return -EPERM vs -EINVAL

> > If you mean for arch_lock_shadow_stack_status() I think -EINVAL is a
> > sensible error code when the system or task does not support shadow
> > stacks, I'm not sure we should return -EPERM at all.  On arm64 we
> > support locking any bit, not just the ones that we currently know about.
> > This is for future proofing, userspace can lock unknown flags.

> No, I mean when setting a locked bit via prctl
> and PR_SET_SHADOW_STACK_STATUS.
> Currently, the error codes for changing a locked bit:
> x86: EPERM
> arm64: EBUSY (Which we discussed offline about changing to EPERM)

Yes, I'll post a patch for that this week all being well.

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  reply	other threads:[~2026-09-09 18:06 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-27 17:15 Shadow Stack Locking Semantics between arch's Bill Roberts
2026-08-27 17:52 ` Bill Roberts
2026-08-27 18:14   ` Mark Brown
2026-08-27 21:27     ` Edgecombe, Rick P
2026-08-27 21:41       ` Mark Brown
2026-08-27 22:37         ` Edgecombe, Rick P
2026-08-28 13:27           ` Mark Brown
2026-08-28 16:48             ` Edgecombe, Rick P
2026-08-28 17:11               ` Mark Brown
2026-09-09 17:57     ` Bill Roberts
2026-09-09 18:06       ` Mark Brown [this message]
2026-09-09 20:01         ` Bill Roberts
2026-09-10 14:19       ` Bill Roberts

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