* [PATCH v3 0/4] Add initial Freescale Vybrid MVF600 support
@ 2013-05-16 6:10 Jingchang Lu
2013-05-16 6:10 ` [PATCH v3 1/4] ARM: imx: add MVF600 clock support Jingchang Lu
` (3 more replies)
0 siblings, 4 replies; 19+ messages in thread
From: Jingchang Lu @ 2013-05-16 6:10 UTC (permalink / raw)
To: linux-arm-kernel
Vybird MVF600 is a heterogeneous dual-core eMPU using ARM Cortex-A5 and
Cortex-M4 cores. The kernel are implemented on the Cortex-A5 core.
The core is different with current I.MX serial. However, This SOC
still shares some IPs with I.MX serials, such as FEC, ESDHC, WATCHDOG,
I2C, ASRC and ESAI, This SOC also shares some IPs with ColdFire platform,
such as eDMA and DSPI. And this SOC still have its own IPs such as PIT,
SAI, UART, QuadSPI and DCU.
Jingchang Lu (4):
ARM: imx: add MVF600 clock support
ARM: imx: add initial support for MVF600
ARM: dts: add SoC level device tree source for MVF600
ARM: dts: add initial MVF600 Tower board dts support
Documentation/devicetree/bindings/clock/mvf600-clock.txt | 26 ++
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/mvf600-pinfunc.h | 810 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mvf600-twr.dts | 108 +++++
arch/arm/boot/dts/mvf600.dtsi | 475 ++++++++++++++++++++
arch/arm/mach-imx/Kconfig | 15 +
arch/arm/mach-imx/Makefile | 2 +
arch/arm/mach-imx/clk-mvf600.c | 322 ++++++++++++++
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/mach-mvf600.c | 70 +++
include/dt-bindings/clock/mvf600-clock.h | 163 +++++++
11 files changed, 1994 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt
create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h
create mode 100644 arch/arm/boot/dts/mvf600-twr.dts
create mode 100644 arch/arm/boot/dts/mvf600.dtsi
create mode 100644 arch/arm/mach-imx/clk-mvf600.c
create mode 100644 arch/arm/mach-imx/mach-mvf600.c
create mode 100644 include/dt-bindings/clock/mvf600-clock.h
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v3 1/4] ARM: imx: add MVF600 clock support 2013-05-16 6:10 [PATCH v3 0/4] Add initial Freescale Vybrid MVF600 support Jingchang Lu @ 2013-05-16 6:10 ` Jingchang Lu 2013-05-16 6:10 ` [PATCH v3 2/4] ARM: imx: add initial support for MVF600 Jingchang Lu ` (2 subsequent siblings) 3 siblings, 0 replies; 19+ messages in thread From: Jingchang Lu @ 2013-05-16 6:10 UTC (permalink / raw) To: linux-arm-kernel Add clock support for Vybrid MVF600. It uses dtc macro support to define all clock IDs in mvf600-clock.h to keep clock IDs coherence between kernel and DT. Signed-off-by: Jingchang Lu <b35083@freescale.com> --- v3: use DTC macro support to define these clock IDs. remove unused #include header lines. name clocks close to reference manual. .../devicetree/bindings/clock/mvf600-clock.txt | 26 ++ arch/arm/mach-imx/clk-mvf600.c | 322 +++++++++++++++++++++ include/dt-bindings/clock/mvf600-clock.h | 163 +++++++++++ 3 files changed, 511 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mvf600-clock.txt create mode 100644 arch/arm/mach-imx/clk-mvf600.c create mode 100644 include/dt-bindings/clock/mvf600-clock.h diff --git a/Documentation/devicetree/bindings/clock/mvf600-clock.txt b/Documentation/devicetree/bindings/clock/mvf600-clock.txt new file mode 100644 index 0000000..34c0abb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mvf600-clock.txt @@ -0,0 +1,26 @@ +* Clock bindings for Freescale Vybrid MVF600 SOC + +Required properties: +- compatible: Should be "fsl,mvf600-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/mvf600-clock.h +for the full list of MVF600 clock IDs. + +Examples: + +clks: ccm at 4006b000 { + compatible = "fsl,mvf600-ccm"; + reg = <0x4006b000 0x1000>; + #clock-cells = <1>; +}; + +uart1: serial at 40028000 { + compatible = "fsl,mvf600-uart"; + reg = <0x40028000 0x1000>; + interrupts = <0 62 0x04>; + clocks = <&clks MVF600_CLK_UART1>; + clock-names = "ipg"; +}; diff --git a/arch/arm/mach-imx/clk-mvf600.c b/arch/arm/mach-imx/clk-mvf600.c new file mode 100644 index 0000000..58c0065 --- /dev/null +++ b/arch/arm/mach-imx/clk-mvf600.c @@ -0,0 +1,322 @@ +/* + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <linux/of_address.h> +#include <linux/clk.h> +#include <dt-bindings/clock/mvf600-clock.h> + +#include "clk.h" + +#define CCM_CCR (ccm_base + 0x00) +#define CCM_CSR (ccm_base + 0x04) +#define CCM_CCSR (ccm_base + 0x08) +#define CCM_CACRR (ccm_base + 0x0c) +#define CCM_CSCMR1 (ccm_base + 0x10) +#define CCM_CSCDR1 (ccm_base + 0x14) +#define CCM_CSCDR2 (ccm_base + 0x18) +#define CCM_CSCDR3 (ccm_base + 0x1c) +#define CCM_CSCMR2 (ccm_base + 0x20) +#define CCM_CSCDR4 (ccm_base + 0x24) +#define CCM_CLPCR (ccm_base + 0x2c) +#define CCM_CISR (ccm_base + 0x30) +#define CCM_CIMR (ccm_base + 0x34) +#define CCM_CGPR (ccm_base + 0x3c) +#define CCM_CCGR0 (ccm_base + 0x40) +#define CCM_CCGR1 (ccm_base + 0x44) +#define CCM_CCGR2 (ccm_base + 0x48) +#define CCM_CCGR3 (ccm_base + 0x4c) +#define CCM_CCGR4 (ccm_base + 0x50) +#define CCM_CCGR5 (ccm_base + 0x54) +#define CCM_CCGR6 (ccm_base + 0x58) +#define CCM_CCGR7 (ccm_base + 0x5c) +#define CCM_CCGR8 (ccm_base + 0x60) +#define CCM_CCGR9 (ccm_base + 0x64) +#define CCM_CCGR10 (ccm_base + 0x68) +#define CCM_CCGR11 (ccm_base + 0x6c) +#define CCM_CMEOR0 (ccm_base + 0x70) +#define CCM_CMEOR1 (ccm_base + 0x74) +#define CCM_CMEOR2 (ccm_base + 0x78) +#define CCM_CMEOR3 (ccm_base + 0x7c) +#define CCM_CMEOR4 (ccm_base + 0x80) +#define CCM_CMEOR5 (ccm_base + 0x84) +#define CCM_CPPDSR (ccm_base + 0x88) +#define CCM_CCOWR (ccm_base + 0x8c) +#define CCM_CCPGR0 (ccm_base + 0x90) +#define CCM_CCPGR1 (ccm_base + 0x94) +#define CCM_CCPGR2 (ccm_base + 0x98) +#define CCM_CCPGR3 (ccm_base + 0x9c) + +#define CCM_CCGRx_CGn(n) ((n) * 2) + +#define PFD_PLL1_BASE (anatop_base + 0x2b0) +#define PFD_PLL2_BASE (anatop_base + 0x100) +#define PFD_PLL3_BASE (anatop_base + 0xf0) + +static void __iomem *anatop_base; +static void __iomem *ccm_base; + +/* sources for multiplexer clocks, this is used multiple times */ +static const char const *fast_sels[] = { "firc", "fxosc", }; +static const char const *slow_sels[] = { "sirc_32k", "sxosc", }; +static const char const *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; +static const char const *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; +static const char const *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", }; +static const char const *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; +static const char const *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; +static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; +static const char const *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; +static const char const *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; +static const char const *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; +static const char const *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; +static const char const *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; +static const char const *dcu_sels[] = { "pll1_pfd2", "pll3_main", }; +static const char const *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; +static const char const *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; +/* FTM counter clock source, not module clock */ +static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; +static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; + +static struct clk_div_table pll4_main_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 6 }, + { .val = 3, .div = 8 }, + { .val = 4, .div = 10 }, + { .val = 5, .div = 12 }, + { .val = 6, .div = 14 }, + { .val = 7, .div = 16 }, + { } +}; + +static struct clk *clk[MVF600_CLK_END]; +static struct clk_onecell_data clk_data; + +int __init mvf600_clocks_init(void) +{ + struct device_node *np; + + of_clk_init(NULL); + + clk[MVF600_CLK_DUMMY] = imx_clk_fixed("dummy", 0); + clk[MVF600_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); + clk[MVF600_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); + clk[MVF600_CLK_FIRC] = imx_clk_fixed("firc", 24000000); + + clk[MVF600_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0); + clk[MVF600_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0); + clk[MVF600_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0); + clk[MVF600_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0); + + clk[MVF600_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); + + np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-anatop"); + anatop_base = of_iomap(np, 0); + WARN_ON(!anatop_base); + + np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-ccm"); + ccm_base = of_iomap(np, 0); + WARN_ON(!ccm_base); + + clk[MVF600_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); + clk[MVF600_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); + + clk[MVF600_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1); + clk[MVF600_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0); + clk[MVF600_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1); + clk[MVF600_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2); + clk[MVF600_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3); + + clk[MVF600_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1); + clk[MVF600_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0); + clk[MVF600_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1); + clk[MVF600_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2); + clk[MVF600_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3); + + clk[MVF600_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1); + clk[MVF600_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0); + clk[MVF600_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1); + clk[MVF600_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2); + clk[MVF600_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3); + + clk[MVF600_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1); + /* Enet pll: fixed 50Mhz */ + clk[MVF600_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); + /* pll6: default 960Mhz */ + clk[MVF600_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); + clk[MVF600_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); + clk[MVF600_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); + clk[MVF600_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); + clk[MVF600_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels)); + clk[MVF600_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3); + clk[MVF600_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); + clk[MVF600_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); + + clk[MVF600_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1); + clk[MVF600_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); + clk[MVF600_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); + + clk[MVF600_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4)); + clk[MVF600_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4)); + + clk[MVF600_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); + clk[MVF600_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); + clk[MVF600_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2); + clk[MVF600_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1); + clk[MVF600_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1); + clk[MVF600_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4)); + + clk[MVF600_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4); + clk[MVF600_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12); + clk[MVF600_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2); + clk[MVF600_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1); + clk[MVF600_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); + clk[MVF600_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4)); + + clk[MVF600_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10); + clk[MVF600_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20); + clk[MVF600_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4); + clk[MVF600_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); + clk[MVF600_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); + clk[MVF600_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23); + + clk[MVF600_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); + + clk[MVF600_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7)); + clk[MVF600_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); + clk[MVF600_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); + clk[MVF600_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); + + clk[MVF600_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); + clk[MVF600_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); + + clk[MVF600_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12)); + clk[MVF600_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13)); + clk[MVF600_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12)); + clk[MVF600_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13)); + + clk[MVF600_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14)); + + clk[MVF600_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4); + clk[MVF600_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28); + clk[MVF600_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4); + clk[MVF600_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1)); + + clk[MVF600_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4); + clk[MVF600_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29); + clk[MVF600_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4); + clk[MVF600_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2)); + + /* + * ftm_ext_clk and ftm_fix_clk are FTM timer counter's + * selectable clock sources, both use a common enable bit + * in CCM_CSCDR1, selecting "dummy" clock as parent of + * "ftm0_ext_fix" make it serve only for enable/disable. + */ + clk[MVF600_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4); + clk[MVF600_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2); + clk[MVF600_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25); + clk[MVF600_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4); + clk[MVF600_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2); + clk[MVF600_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26); + clk[MVF600_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4); + clk[MVF600_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2); + clk[MVF600_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27); + clk[MVF600_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4); + clk[MVF600_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2); + clk[MVF600_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28); + + /* ftm(n)_clk are FTM module operation clock */ + clk[MVF600_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8)); + clk[MVF600_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9)); + clk[MVF600_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8)); + clk[MVF600_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9)); + + clk[MVF600_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2); + clk[MVF600_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19); + clk[MVF600_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3); + clk[MVF600_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); + clk[MVF600_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2); + clk[MVF600_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23); + clk[MVF600_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); + clk[MVF600_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); + + clk[MVF600_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); + clk[MVF600_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); + clk[MVF600_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4); + clk[MVF600_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2)); + + clk[MVF600_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4); + clk[MVF600_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16); + clk[MVF600_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4); + clk[MVF600_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15)); + + clk[MVF600_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4); + clk[MVF600_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17); + clk[MVF600_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4); + clk[MVF600_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0)); + + clk[MVF600_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4); + clk[MVF600_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18); + clk[MVF600_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4); + clk[MVF600_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1)); + + clk[MVF600_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4); + clk[MVF600_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19); + clk[MVF600_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4); + clk[MVF600_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2)); + + clk[MVF600_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4); + clk[MVF600_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9); + clk[MVF600_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3); + clk[MVF600_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4); + clk[MVF600_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0)); + + clk[MVF600_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2); + clk[MVF600_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10); + clk[MVF600_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15)); + + clk[MVF600_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3); + clk[MVF600_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22); + clk[MVF600_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2); + clk[MVF600_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2); + clk[MVF600_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7)); + + clk[MVF600_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11)); + clk[MVF600_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11)); + clk[MVF600_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12)); + clk[MVF600_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13)); + + clk[MVF600_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); + + clk[MVF600_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); + clk[MVF600_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); + + clk_set_parent(clk[MVF600_CLK_QSPI0_SEL], clk[MVF600_CLK_PLL1_PFD4]); + clk_set_rate(clk[MVF600_CLK_QSPI0_X4_DIV], clk_get_rate(clk[MVF600_CLK_QSPI0_SEL]) / 2); + clk_set_rate(clk[MVF600_CLK_QSPI0_X2_DIV], clk_get_rate(clk[MVF600_CLK_QSPI0_X4_DIV]) / 2); + clk_set_rate(clk[MVF600_CLK_QSPI0_X1_DIV], clk_get_rate(clk[MVF600_CLK_QSPI0_X2_DIV]) / 2); + + clk_set_parent(clk[MVF600_CLK_QSPI1_SEL], clk[MVF600_CLK_PLL1_PFD4]); + clk_set_rate(clk[MVF600_CLK_QSPI1_X4_DIV], clk_get_rate(clk[MVF600_CLK_QSPI1_SEL]) / 2); + clk_set_rate(clk[MVF600_CLK_QSPI1_X2_DIV], clk_get_rate(clk[MVF600_CLK_QSPI1_X4_DIV]) / 2); + clk_set_rate(clk[MVF600_CLK_QSPI1_X1_DIV], clk_get_rate(clk[MVF600_CLK_QSPI1_X2_DIV]) / 2); + + clk_set_parent(clk[MVF600_CLK_SAI0_EN], clk[MVF600_CLK_AUDIO_EXT]); + clk_set_parent(clk[MVF600_CLK_SAI1_EN], clk[MVF600_CLK_AUDIO_EXT]); + clk_set_parent(clk[MVF600_CLK_SAI2_EN], clk[MVF600_CLK_AUDIO_EXT]); + clk_set_parent(clk[MVF600_CLK_SAI3_EN], clk[MVF600_CLK_AUDIO_EXT]); + + /* Add the clocks to provider list */ + clk_data.clks = clk; + clk_data.clk_num = ARRAY_SIZE(clk); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + return 0; +} diff --git a/include/dt-bindings/clock/mvf600-clock.h b/include/dt-bindings/clock/mvf600-clock.h new file mode 100644 index 0000000..7c43c8a --- /dev/null +++ b/include/dt-bindings/clock/mvf600-clock.h @@ -0,0 +1,163 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_MVF600_H +#define __DT_BINDINGS_CLOCK_MVF600_H + +#define MVF600_CLK_DUMMY 0 +#define MVF600_CLK_SIRC_128K 1 +#define MVF600_CLK_SIRC_32K 2 +#define MVF600_CLK_FIRC 3 +#define MVF600_CLK_SXOSC 4 +#define MVF600_CLK_FXOSC 5 +#define MVF600_CLK_FXOSC_HALF 6 +#define MVF600_CLK_SLOW_CLK_SEL 7 +#define MVF600_CLK_FASK_CLK_SEL 8 +#define MVF600_CLK_AUDIO_EXT 9 +#define MVF600_CLK_ENET_EXT 10 +#define MVF600_CLK_PLL1_MAIN 11 +#define MVF600_CLK_PLL1_PFD1 12 +#define MVF600_CLK_PLL1_PFD2 13 +#define MVF600_CLK_PLL1_PFD3 14 +#define MVF600_CLK_PLL1_PFD4 15 +#define MVF600_CLK_PLL2_MAIN 16 +#define MVF600_CLK_PLL2_PFD1 17 +#define MVF600_CLK_PLL2_PFD2 18 +#define MVF600_CLK_PLL2_PFD3 19 +#define MVF600_CLK_PLL2_PFD4 20 +#define MVF600_CLK_PLL3_MAIN 21 +#define MVF600_CLK_PLL3_PFD1 22 +#define MVF600_CLK_PLL3_PFD2 23 +#define MVF600_CLK_PLL3_PFD3 24 +#define MVF600_CLK_PLL3_PFD4 25 +#define MVF600_CLK_PLL4_MAIN 26 +#define MVF600_CLK_PLL5_MAIN 27 +#define MVF600_CLK_PLL6_MAIN 28 +#define MVF600_CLK_PLL3_MAIN_DIV 29 +#define MVF600_CLK_PLL4_MAIN_DIV 30 +#define MVF600_CLK_PLL6_MAIN_DIV 31 +#define MVF600_CLK_PLL1_PFD_SEL 32 +#define MVF600_CLK_PLL2_PFD_SEL 33 +#define MVF600_CLK_SYS_SEL 34 +#define MVF600_CLK_DDR_SEL 35 +#define MVF600_CLK_SYS_BUS 36 +#define MVF600_CLK_PLATFORM_BUS 37 +#define MVF600_CLK_IPG_BUS 38 +#define MVF600_CLK_UART0 39 +#define MVF600_CLK_UART1 40 +#define MVF600_CLK_UART2 41 +#define MVF600_CLK_UART3 42 +#define MVF600_CLK_UART4 43 +#define MVF600_CLK_UART5 44 +#define MVF600_CLK_PIT 45 +#define MVF600_CLK_I2C0 46 +#define MVF600_CLK_I2C1 47 +#define MVF600_CLK_I2C2 48 +#define MVF600_CLK_I2C3 49 +#define MVF600_CLK_FTM0_EXT_SEL 50 +#define MVF600_CLK_FTM0_FIX_SEL 51 +#define MVF600_CLK_FTM0_EXT_FIX_EN 52 +#define MVF600_CLK_FTM1_EXT_SEL 53 +#define MVF600_CLK_FTM1_FIX_SEL 54 +#define MVF600_CLK_FTM1_EXT_FIX_EN 55 +#define MVF600_CLK_FTM2_EXT_SEL 56 +#define MVF600_CLK_FTM2_FIX_SEL 57 +#define MVF600_CLK_FTM2_EXT_FIX_EN 58 +#define MVF600_CLK_FTM3_EXT_SEL 59 +#define MVF600_CLK_FTM3_FIX_SEL 60 +#define MVF600_CLK_FTM3_EXT_FIX_EN 61 +#define MVF600_CLK_FTM0 62 +#define MVF600_CLK_FTM1 63 +#define MVF600_CLK_FTM2 64 +#define MVF600_CLK_FTM3 65 +#define MVF600_CLK_ENET_50M 66 +#define MVF600_CLK_ENET_25M 67 +#define MVF600_CLK_ENET_SEL 68 +#define MVF600_CLK_ENET 69 +#define MVF600_CLK_ENET_TS_SEL 70 +#define MVF600_CLK_ENET_TS 71 +#define MVF600_CLK_DSPI0 72 +#define MVF600_CLK_DSPI1 73 +#define MVF600_CLK_DSPI2 74 +#define MVF600_CLK_DSPI3 75 +#define MVF600_CLK_WDT 76 +#define MVF600_CLK_ESDHC0_SEL 77 +#define MVF600_CLK_ESDHC0_EN 78 +#define MVF600_CLK_ESDHC0_DIV 79 +#define MVF600_CLK_ESDHC0 80 +#define MVF600_CLK_ESDHC1_SEL 81 +#define MVF600_CLK_ESDHC1_EN 82 +#define MVF600_CLK_ESDHC1_DIV 83 +#define MVF600_CLK_ESDHC1 84 +#define MVF600_CLK_DCU0_SEL 85 +#define MVF600_CLK_DCU0_EN 86 +#define MVF600_CLK_DCU0_DIV 87 +#define MVF600_CLK_DCU0 88 +#define MVF600_CLK_DCU1_SEL 89 +#define MVF600_CLK_DCU1_EN 90 +#define MVF600_CLK_DCU1_DIV 91 +#define MVF600_CLK_DCU1 92 +#define MVF600_CLK_ESAI_SEL 93 +#define MVF600_CLK_ESAI_EN 94 +#define MVF600_CLK_ESAI_DIV 95 +#define MVF600_CLK_ESAI 96 +#define MVF600_CLK_SAI0_SEL 97 +#define MVF600_CLK_SAI0_EN 98 +#define MVF600_CLK_SAI0_DIV 99 +#define MVF600_CLK_SAI0 100 +#define MVF600_CLK_SAI1_SEL 101 +#define MVF600_CLK_SAI1_EN 102 +#define MVF600_CLK_SAI1_DIV 103 +#define MVF600_CLK_SAI1 104 +#define MVF600_CLK_SAI2_SEL 105 +#define MVF600_CLK_SAI2_EN 106 +#define MVF600_CLK_SAI2_DIV 107 +#define MVF600_CLK_SAI2 108 +#define MVF600_CLK_SAI3_SEL 109 +#define MVF600_CLK_SAI3_EN 110 +#define MVF600_CLK_SAI3_DIV 111 +#define MVF600_CLK_SAI3 112 +#define MVF600_CLK_USBC0 113 +#define MVF600_CLK_USBC1 114 +#define MVF600_CLK_QSPI0_SEL 115 +#define MVF600_CLK_QSPI0_EN 116 +#define MVF600_CLK_QSPI0_X4_DIV 117 +#define MVF600_CLK_QSPI0_X2_DIV 118 +#define MVF600_CLK_QSPI0_X1_DIV 119 +#define MVF600_CLK_QSPI1_SEL 120 +#define MVF600_CLK_QSPI1_EN 121 +#define MVF600_CLK_QSPI1_X4_DIV 122 +#define MVF600_CLK_QSPI1_X2_DIV 123 +#define MVF600_CLK_QSPI1_X1_DIV 124 +#define MVF600_CLK_QSPI0 125 +#define MVF600_CLK_QSPI1 126 +#define MVF600_CLK_NFC_SEL 127 +#define MVF600_CLK_NFC_EN 128 +#define MVF600_CLK_NFC_PRE_DIV 129 +#define MVF600_CLK_NFC_FRAC_DIV 130 +#define MVF600_CLK_NFC_INV 131 +#define MVF600_CLK_NFC 132 +#define MVF600_CLK_VADC_SEL 133 +#define MVF600_CLK_VADC_EN 134 +#define MVF600_CLK_VADC_DIV 135 +#define MVF600_CLK_VADC_DIV_HALF 136 +#define MVF600_CLK_VADC 137 +#define MVF600_CLK_ADC0 138 +#define MVF600_CLK_ADC1 139 +#define MVF600_CLK_DAC0 140 +#define MVF600_CLK_DAC1 141 +#define MVF600_CLK_FLEXCAN0 142 +#define MVF600_CLK_FLEXCAN1 143 +#define MVF600_CLK_ASRC 144 +#define MVF600_CLK_GPU_SEL 145 +#define MVF600_CLK_GPU_EN 146 +#define MVF600_CLK_GPU2D 147 +#define MVF600_CLK_END 148 + +#endif /* __DT_BINDINGS_CLOCK_MVF600_H */ -- 1.8.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-16 6:10 [PATCH v3 0/4] Add initial Freescale Vybrid MVF600 support Jingchang Lu 2013-05-16 6:10 ` [PATCH v3 1/4] ARM: imx: add MVF600 clock support Jingchang Lu @ 2013-05-16 6:10 ` Jingchang Lu 2013-05-16 10:29 ` Arnd Bergmann ` (2 more replies) 2013-05-16 6:10 ` [PATCH v3 3/4] ARM: dts: add SoC level device tree source " Jingchang Lu 2013-05-16 6:10 ` [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts support Jingchang Lu 3 siblings, 3 replies; 19+ messages in thread From: Jingchang Lu @ 2013-05-16 6:10 UTC (permalink / raw) To: linux-arm-kernel Add initial support for Vybrid MVF600 SoC. Signed-off-by: Jingchang Lu <b35083@freescale.com> --- v3: remove unused #include header lines. use common mxc restart function. arch/arm/mach-imx/Kconfig | 15 +++++++++ arch/arm/mach-imx/Makefile | 2 ++ arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/mach-mvf600.c | 70 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 88 insertions(+) create mode 100644 arch/arm/mach-imx/mach-mvf600.c diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index a402248..b9c01a1 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -835,6 +835,21 @@ config SOC_IMX6SL help This enables support for Freescale i.MX6 SoloLite processor. +config SOC_MVF600 + bool "Vybrid Family MVF600 support" + select CPU_V7 + select ARM_GIC + select CLKSRC_OF + select PINCTRL + select PINCTRL_MVF600 + select MVF600_PIT_TIMER + select PL310_ERRATA_588369 if CACHE_PL310 + select PL310_ERRATA_727915 if CACHE_PL310 + select PL310_ERRATA_769419 if CACHE_PL310 + + help + This enable support for Freescale Vybrid MVF600 processor. + endif source "arch/arm/mach-imx/devices/Kconfig" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 2a4754d..28d8b4c 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -112,4 +112,6 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o obj-$(CONFIG_SOC_IMX53) += mach-imx53.o +obj-$(CONFIG_SOC_MVF600) += clk-mvf600.o mach-mvf600.o + obj-y += devices/ diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 208e76f..55cdba0 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -70,6 +70,7 @@ extern int mx51_clocks_init_dt(void); extern int mx53_clocks_init_dt(void); extern int mx6q_clocks_init(void); extern int imx6sl_clocks_init(void); +extern int mvf600_clocks_init(void); extern struct platform_device *mxc_register_gpio(char *name, int id, resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); extern void mxc_set_cpu_type(unsigned int type); diff --git a/arch/arm/mach-imx/mach-mvf600.c b/arch/arm/mach-imx/mach-mvf600.c new file mode 100644 index 0000000..deffe74 --- /dev/null +++ b/arch/arm/mach-imx/mach-mvf600.c @@ -0,0 +1,70 @@ +/* + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/clk.h> +#include <linux/clocksource.h> +#include <linux/irqchip.h> +#include <linux/irqchip/arm-gic.h> +#include <asm/mach/arch.h> +#include <asm/hardware/cache-l2x0.h> +#include <asm/system_misc.h> + +#include "common.h" + +static void __init mvf600_init_machine(void) +{ + mxc_arch_reset_init_dt(); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static void __init mvf600_init_irq(void) +{ + struct device_node *np; + void __iomem *mscm_base; + int i; + + l2x0_of_init(0, ~0UL); + + np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-mscm"); + mscm_base = of_iomap(np, 0); + if (!mscm_base) + return; + + /* route all shared peripheral interrupts to CP0 */ + for (i = 0; i < 111; i++) + __raw_writew(1, mscm_base + 0x880 + 2 * i); + + iounmap(mscm_base); + + irqchip_init(); +} + +static void __init mvf600_init_time(void) +{ + mvf600_clocks_init(); + clocksource_of_init(); +} + +static const char *mvf600_dt_compat[] __initdata = { + "fsl,mvf600", + NULL, +}; + +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid MVF600 (Device Tree)") + .init_irq = mvf600_init_irq, + .init_time = mvf600_init_time, + .init_machine = mvf600_init_machine, + .dt_compat = mvf600_dt_compat, + .restart = mxc_restart, +MACHINE_END -- 1.8.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-16 6:10 ` [PATCH v3 2/4] ARM: imx: add initial support for MVF600 Jingchang Lu @ 2013-05-16 10:29 ` Arnd Bergmann 2013-05-17 8:57 ` Shawn Guo 2013-05-17 9:08 ` Shawn Guo 2013-05-18 1:27 ` Shawn Guo 2 siblings, 1 reply; 19+ messages in thread From: Arnd Bergmann @ 2013-05-16 10:29 UTC (permalink / raw) To: linux-arm-kernel On Thursday 16 May 2013 14:10:46 Jingchang Lu wrote: > index a402248..b9c01a1 100644 > --- a/arch/arm/mach-imx/Kconfig > +++ b/arch/arm/mach-imx/Kconfig > @@ -835,6 +835,21 @@ config SOC_IMX6SL > help > This enables support for Freescale i.MX6 SoloLite processor. > > +config SOC_MVF600 > + bool "Vybrid Family MVF600 support" > + select CPU_V7 > + select ARM_GIC > + select CLKSRC_OF > + select PINCTRL > + select PINCTRL_MVF600 > + select MVF600_PIT_TIMER > + select PL310_ERRATA_588369 if CACHE_PL310 > + select PL310_ERRATA_727915 if CACHE_PL310 > + select PL310_ERRATA_769419 if CACHE_PL310 > + > + help > + This enable support for Freescale Vybrid MVF600 processor. > + > endif Shouldn't that 'depends on ARCH_MULTI_V7'? Can you describe how much Vybrid is actually like MXC? Do you actually use most of the mach-imx code? > diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h > index 208e76f..55cdba0 100644 > --- a/arch/arm/mach-imx/common.h > +++ b/arch/arm/mach-imx/common.h > @@ -70,6 +70,7 @@ extern int mx51_clocks_init_dt(void); > extern int mx53_clocks_init_dt(void); > extern int mx6q_clocks_init(void); > extern int imx6sl_clocks_init(void); > +extern int mvf600_clocks_init(void); > extern struct platform_device *mxc_register_gpio(char *name, int id, > resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); > extern void mxc_set_cpu_type(unsigned int type); This hunk belongs into the first patch, right? Actually I think you should move that driver to drivers/clk and use of_clk_init(NULL) to initialize it. > +static void __init mvf600_init_machine(void) > +{ > + mxc_arch_reset_init_dt(); I don't see the mxc_arch_reset_init_dt function in 3.10-rc1. Where does it get introduced? It would be nice if we could integrate that into the watchdog driver, so that driver just registers a pm_restart function when it gets loaded. It is a rather small driver, so it would not hurt to always load it. > + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); > +} It would be nicer if you could just use the default init_machine. > +static void __init mvf600_init_irq(void) > +{ > + struct device_node *np; > + void __iomem *mscm_base; > + int i; > + > + l2x0_of_init(0, ~0UL); > + > + np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-mscm"); > + mscm_base = of_iomap(np, 0); > + if (!mscm_base) > + return; > + > + /* route all shared peripheral interrupts to CP0 */ > + for (i = 0; i < 111; i++) > + __raw_writew(1, mscm_base + 0x880 + 2 * i); > + > + iounmap(mscm_base); > + > + irqchip_init(); > +} What is the mscm? Shouldn't the boot loader have set this up correctly? If you can remove that code from the kernel, you can use the default irqchip_init call. > +static void __init mvf600_init_time(void) > +{ > + mvf600_clocks_init(); > + clocksource_of_init(); > +} I would like to call of_clk_init(NULL) unconditionally on all machines in 3.11, so this function could also go away. > +static const char *mvf600_dt_compat[] __initdata = { > + "fsl,mvf600", > + NULL, > +}; > + > +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid MVF600 (Device Tree)") > + .init_irq = mvf600_init_irq, > + .init_time = mvf600_init_time, > + .init_machine = mvf600_init_machine, > + .dt_compat = mvf600_dt_compat, > + .restart = mxc_restart, > +MACHINE_END If we can do all of the above, we can actually remove the entire machine descriptor here, since all its members are NULL. Arnd ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-16 10:29 ` Arnd Bergmann @ 2013-05-17 8:57 ` Shawn Guo 2013-05-17 12:29 ` Arnd Bergmann 0 siblings, 1 reply; 19+ messages in thread From: Shawn Guo @ 2013-05-17 8:57 UTC (permalink / raw) To: linux-arm-kernel Arnd, Allow me help respond a little bit. On Thu, May 16, 2013 at 12:29:28PM +0200, Arnd Bergmann wrote: > On Thursday 16 May 2013 14:10:46 Jingchang Lu wrote: > > > index a402248..b9c01a1 100644 > > --- a/arch/arm/mach-imx/Kconfig > > +++ b/arch/arm/mach-imx/Kconfig > > @@ -835,6 +835,21 @@ config SOC_IMX6SL > > help > > This enables support for Freescale i.MX6 SoloLite processor. > > > > +config SOC_MVF600 > > + bool "Vybrid Family MVF600 support" > > + select CPU_V7 > > + select ARM_GIC > > + select CLKSRC_OF > > + select PINCTRL > > + select PINCTRL_MVF600 > > + select MVF600_PIT_TIMER > > + select PL310_ERRATA_588369 if CACHE_PL310 > > + select PL310_ERRATA_727915 if CACHE_PL310 > > + select PL310_ERRATA_769419 if CACHE_PL310 > > + > > + help > > + This enable support for Freescale Vybrid MVF600 processor. > > + > > endif > > Shouldn't that 'depends on ARCH_MULTI_V7'? > SOC_MVF600 is added as a sub-item of ARCH_MXC which already handles the ARCH_MULTI_* dependency. > Can you describe how much Vybrid is actually like MXC? Do you actually > use most of the mach-imx code? > Jingchang mentioned some IP blocks shared between IMX and Vybrid. Right now, mvf600 reuses mxc_restart() and some amount of clk code clk-pllv3.c, clk-gate2.c clk.c etc. in arch/arm/mach-imx. > > diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h > > index 208e76f..55cdba0 100644 > > --- a/arch/arm/mach-imx/common.h > > +++ b/arch/arm/mach-imx/common.h > > @@ -70,6 +70,7 @@ extern int mx51_clocks_init_dt(void); > > extern int mx53_clocks_init_dt(void); > > extern int mx6q_clocks_init(void); > > extern int imx6sl_clocks_init(void); > > +extern int mvf600_clocks_init(void); > > extern struct platform_device *mxc_register_gpio(char *name, int id, > > resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); > > extern void mxc_set_cpu_type(unsigned int type); > > This hunk belongs into the first patch, right? > The declaration is only used in this patch by mach-mvf600.c. > Actually I think you should move that driver to drivers/clk and use > of_clk_init(NULL) to initialize it. > The mvf600 clock driver uses a lot of base clk support from mach-imx, and can not be moved into drivers/clk as a single driver. Right now, in IMX clock drivers, we call of_clk_init() to only register fixed rate clocks, since all the other clocks are not represented in device tree. > > +static void __init mvf600_init_machine(void) > > +{ > > + mxc_arch_reset_init_dt(); > > I don't see the mxc_arch_reset_init_dt function in 3.10-rc1. Where does it > get introduced? > It gets introduced by my series below. And I guess Jiangchang is basing his series on my imx/soc branch. http://thread.gmane.org/gmane.linux.ports.arm.kernel/235986/focus=236091 > It would be nice if we could integrate that into the watchdog driver, > so that driver just registers a pm_restart function when it gets loaded. > It is a rather small driver, so it would not hurt to always load it. > Sound like a good idea. We will consider it as another cleanup task for mach-imx. > > + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); > > +} > > It would be nicer if you could just use the default init_machine. > > > +static void __init mvf600_init_irq(void) > > +{ > > + struct device_node *np; > > + void __iomem *mscm_base; > > + int i; > > + > > + l2x0_of_init(0, ~0UL); > > + > > + np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-mscm"); > > + mscm_base = of_iomap(np, 0); > > + if (!mscm_base) > > + return; > > + > > + /* route all shared peripheral interrupts to CP0 */ > > + for (i = 0; i < 111; i++) > > + __raw_writew(1, mscm_base + 0x880 + 2 * i); > > + > > + iounmap(mscm_base); > > + > > + irqchip_init(); > > +} > > What is the mscm? Shouldn't the boot loader have set this up correctly? > If you can remove that code from the kernel, you can use the default > irqchip_init call. > Yeah, and if we find another way for l2x0_of_init() call. > > +static void __init mvf600_init_time(void) > > +{ > > + mvf600_clocks_init(); > > + clocksource_of_init(); > > +} > > I would like to call of_clk_init(NULL) unconditionally on all machines > in 3.11, so this function could also go away. > of_clk_init() has been called in mvf600_clocks_init(), but as explained as above, it only registers fixed rate clocks and can not save mvf600_clocks_init() call right now where most of mvf600 clocks gets registered. > > +static const char *mvf600_dt_compat[] __initdata = { > > + "fsl,mvf600", > > + NULL, > > +}; > > + > > +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid MVF600 (Device Tree)") > > + .init_irq = mvf600_init_irq, > > + .init_time = mvf600_init_time, > > + .init_machine = mvf600_init_machine, > > + .dt_compat = mvf600_dt_compat, > > + .restart = mxc_restart, > > +MACHINE_END > > If we can do all of the above, we can actually remove the entire machine > descriptor here, since all its members are NULL. > Yeah, we understand the goal, and this will be the goal of mach-imx cleanup. Shawn ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-17 8:57 ` Shawn Guo @ 2013-05-17 12:29 ` Arnd Bergmann 2013-05-17 12:31 ` Arnd Bergmann 2013-05-17 13:06 ` Shawn Guo 0 siblings, 2 replies; 19+ messages in thread From: Arnd Bergmann @ 2013-05-17 12:29 UTC (permalink / raw) To: linux-arm-kernel On Friday 17 May 2013, Shawn Guo wrote: > On Thu, May 16, 2013 at 12:29:28PM +0200, Arnd Bergmann wrote: > > On Thursday 16 May 2013 14:10:46 Jingchang Lu wrote: > > > +config SOC_MVF600 > > > > Shouldn't that 'depends on ARCH_MULTI_V7'? > > > SOC_MVF600 is added as a sub-item of ARCH_MXC which already handles the > ARCH_MULTI_* dependency. Ah, makes sense. > > Can you describe how much Vybrid is actually like MXC? Do you actually > > use most of the mach-imx code? > > > Jingchang mentioned some IP blocks shared between IMX and Vybrid. Right > now, mvf600 reuses mxc_restart() and some amount of clk code > clk-pllv3.c, clk-gate2.c clk.c etc. in arch/arm/mach-imx. Ok. > > Actually I think you should move that driver to drivers/clk and use > > of_clk_init(NULL) to initialize it. > > > The mvf600 clock driver uses a lot of base clk support from mach-imx, > and can not be moved into drivers/clk as a single driver. Right now, in > IMX clock drivers, we call of_clk_init() to only register fixed rate > clocks, since all the other clocks are not represented in device tree. What are your plans for this in the long run? > > It would be nice if we could integrate that into the watchdog driver, > > so that driver just registers a pm_restart function when it gets loaded. > > It is a rather small driver, so it would not hurt to always load it. > > > Sound like a good idea. We will consider it as another cleanup task for > mach-imx. Ok > > What is the mscm? Shouldn't the boot loader have set this up correctly? > > If you can remove that code from the kernel, you can use the default > > irqchip_init call. > > > Yeah, and if we find another way for l2x0_of_init() call. Good point. That is something we need to do anyway. > > > +static const char *mvf600_dt_compat[] __initdata = { > > > + "fsl,mvf600", > > > + NULL, > > > +}; > > > + > > > +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid MVF600 (Device Tree)") > > > + .init_irq = mvf600_init_irq, > > > + .init_time = mvf600_init_time, > > > + .init_machine = mvf600_init_machine, > > > + .dt_compat = mvf600_dt_compat, > > > + .restart = mxc_restart, > > > +MACHINE_END > > > > If we can do all of the above, we can actually remove the entire machine > > descriptor here, since all its members are NULL. > > > Yeah, we understand the goal, and this will be the goal of mach-imx > cleanup. Ok. I guess we just won't be there for 3.11 then. Arnd ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-17 12:29 ` Arnd Bergmann @ 2013-05-17 12:31 ` Arnd Bergmann 2013-05-17 13:06 ` Shawn Guo 1 sibling, 0 replies; 19+ messages in thread From: Arnd Bergmann @ 2013-05-17 12:31 UTC (permalink / raw) To: linux-arm-kernel On Friday 17 May 2013, Arnd Bergmann wrote: > > > > +static const char *mvf600_dt_compat[] __initdata = { > > > > + "fsl,mvf600", > > > > + NULL, > > > > +}; > > > > + > > > > +DT_MACHINE_START(VYBRID_VF6XX, "Freescale Vybrid MVF600 (Device Tree)") > > > > + .init_irq = mvf600_init_irq, > > > > + .init_time = mvf600_init_time, > > > > + .init_machine = mvf600_init_machine, > > > > + .dt_compat = mvf600_dt_compat, > > > > + .restart = mxc_restart, > > > > +MACHINE_END > > > > > > If we can do all of the above, we can actually remove the entire machine > > > descriptor here, since all its members are NULL. > > > > > Yeah, we understand the goal, and this will be the goal of mach-imx > > cleanup. > > Ok. I guess we just won't be there for 3.11 then. To clarify: what I mean is we should try to remove all the callbacks we can here, but merge the MVF600 port anyway, even if we still need a couple of them. Arnd ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-17 12:29 ` Arnd Bergmann 2013-05-17 12:31 ` Arnd Bergmann @ 2013-05-17 13:06 ` Shawn Guo 2013-05-17 13:17 ` Arnd Bergmann 1 sibling, 1 reply; 19+ messages in thread From: Shawn Guo @ 2013-05-17 13:06 UTC (permalink / raw) To: linux-arm-kernel On Fri, May 17, 2013 at 02:29:52PM +0200, Arnd Bergmann wrote: > > > Actually I think you should move that driver to drivers/clk and use > > > of_clk_init(NULL) to initialize it. > > > > > The mvf600 clock driver uses a lot of base clk support from mach-imx, > > and can not be moved into drivers/clk as a single driver. Right now, in > > IMX clock drivers, we call of_clk_init() to only register fixed rate > > clocks, since all the other clocks are not represented in device tree. > > What are your plans for this in the long run? > We can move all the IMX clock drivers into drivers/clk at some point when necessary. But I do not have a plan to register all the clocks by merely calling of_clk_init(), because doing that would mean we have to represent all these clocks in device tree. For imx6q example, it's about 200 ~ 300 nodes addition to DTB. Device tree maintainers are against to the idea. They are perfectly fine with having clock driver in kernel to represent/register these SoC internal clocks to clk framework. Shawn ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-17 13:06 ` Shawn Guo @ 2013-05-17 13:17 ` Arnd Bergmann 2013-05-17 13:54 ` Shawn Guo 2013-05-21 2:17 ` Shawn Guo 0 siblings, 2 replies; 19+ messages in thread From: Arnd Bergmann @ 2013-05-17 13:17 UTC (permalink / raw) To: linux-arm-kernel On Friday 17 May 2013 21:06:05 Shawn Guo wrote: > On Fri, May 17, 2013 at 02:29:52PM +0200, Arnd Bergmann wrote: > > > > Actually I think you should move that driver to drivers/clk and use > > > > of_clk_init(NULL) to initialize it. > > > > > > > The mvf600 clock driver uses a lot of base clk support from mach-imx, > > > and can not be moved into drivers/clk as a single driver. Right now, in > > > IMX clock drivers, we call of_clk_init() to only register fixed rate > > > clocks, since all the other clocks are not represented in device tree. > > > > What are your plans for this in the long run? > > > We can move all the IMX clock drivers into drivers/clk at some point > when necessary. But I do not have a plan to register all the clocks > by merely calling of_clk_init(), because doing that would mean we have > to represent all these clocks in device tree. For imx6q example, it's > about 200 ~ 300 nodes addition to DTB. Device tree maintainers are > against to the idea. They are perfectly fine with having clock driver > in kernel to represent/register these SoC internal clocks to clk > framework. Can't we move the driver to drivers/clk and have it initialized through of_clk_init() without representing all clocks in the DT? For all I can tell, CLK_OF_DECLARE() requires only the clock provider to be described in DT, but not the actual clocks. Arnd ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-17 13:17 ` Arnd Bergmann @ 2013-05-17 13:54 ` Shawn Guo 2013-05-21 2:17 ` Shawn Guo 1 sibling, 0 replies; 19+ messages in thread From: Shawn Guo @ 2013-05-17 13:54 UTC (permalink / raw) To: linux-arm-kernel On Fri, May 17, 2013 at 03:17:31PM +0200, Arnd Bergmann wrote: > Can't we move the driver to drivers/clk and have it initialized through > of_clk_init() without representing all clocks in the DT? > > For all I can tell, CLK_OF_DECLARE() requires only the clock provider > to be described in DT, but not the actual clocks. Clock provider is actually a "clk". For fixed rate clock example, of_fixed_factor_clk_setup() firstly parses DT to get all the necessary data and then calls clk_register_fixed_factor() to register the clk to framework, lastly calls of_clk_add_provider() to register the clk as a provider. Shawn ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-17 13:17 ` Arnd Bergmann 2013-05-17 13:54 ` Shawn Guo @ 2013-05-21 2:17 ` Shawn Guo 1 sibling, 0 replies; 19+ messages in thread From: Shawn Guo @ 2013-05-21 2:17 UTC (permalink / raw) To: linux-arm-kernel On Fri, May 17, 2013 at 03:17:31PM +0200, Arnd Bergmann wrote: > On Friday 17 May 2013 21:06:05 Shawn Guo wrote: > > On Fri, May 17, 2013 at 02:29:52PM +0200, Arnd Bergmann wrote: > > > > > Actually I think you should move that driver to drivers/clk and use > > > > > of_clk_init(NULL) to initialize it. > > > > > > > > > The mvf600 clock driver uses a lot of base clk support from mach-imx, > > > > and can not be moved into drivers/clk as a single driver. Right now, in > > > > IMX clock drivers, we call of_clk_init() to only register fixed rate > > > > clocks, since all the other clocks are not represented in device tree. > > > > > > What are your plans for this in the long run? > > > > > We can move all the IMX clock drivers into drivers/clk at some point > > when necessary. But I do not have a plan to register all the clocks > > by merely calling of_clk_init(), because doing that would mean we have > > to represent all these clocks in device tree. For imx6q example, it's > > about 200 ~ 300 nodes addition to DTB. Device tree maintainers are > > against to the idea. They are perfectly fine with having clock driver > > in kernel to represent/register these SoC internal clocks to clk > > framework. > > Can't we move the driver to drivers/clk and have it initialized through > of_clk_init() without representing all clocks in the DT? Sorry. I just get aware of that I misunderstood your comment. Yes, declaring the clock initialization function with CLK_OF_DECLARE(), we can use of_clk_init() to have them invoked properly. I just sent a patch to change imx6 clock driver to do that. Shawn ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-16 6:10 ` [PATCH v3 2/4] ARM: imx: add initial support for MVF600 Jingchang Lu 2013-05-16 10:29 ` Arnd Bergmann @ 2013-05-17 9:08 ` Shawn Guo 2013-05-18 1:27 ` Shawn Guo 2 siblings, 0 replies; 19+ messages in thread From: Shawn Guo @ 2013-05-17 9:08 UTC (permalink / raw) To: linux-arm-kernel On Thu, May 16, 2013 at 02:10:46PM +0800, Jingchang Lu wrote: > Add initial support for Vybrid MVF600 SoC. > > Signed-off-by: Jingchang Lu <b35083@freescale.com> > --- > v3: > remove unused #include header lines. There are more ... > +#include <linux/io.h> > +#include <linux/delay.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_platform.h> > +#include <linux/clk.h> > +#include <linux/clocksource.h> > +#include <linux/irqchip.h> > +#include <linux/irqchip/arm-gic.h> > +#include <asm/mach/arch.h> > +#include <asm/hardware/cache-l2x0.h> > +#include <asm/system_misc.h> #include <linux/delay.h> #include <linux/clk.h> #include <linux/irqchip/arm-gic.h> #include <asm/system_misc.h> I do not see how these 4 headers are needed. Shawn ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/4] ARM: imx: add initial support for MVF600 2013-05-16 6:10 ` [PATCH v3 2/4] ARM: imx: add initial support for MVF600 Jingchang Lu 2013-05-16 10:29 ` Arnd Bergmann 2013-05-17 9:08 ` Shawn Guo @ 2013-05-18 1:27 ` Shawn Guo 2 siblings, 0 replies; 19+ messages in thread From: Shawn Guo @ 2013-05-18 1:27 UTC (permalink / raw) To: linux-arm-kernel On Thu, May 16, 2013 at 02:10:46PM +0800, Jingchang Lu wrote: > +static void __init mvf600_init_irq(void) > +{ > + struct device_node *np; > + void __iomem *mscm_base; > + int i; > + > + l2x0_of_init(0, ~0UL); > + > + np = of_find_compatible_node(NULL, NULL, "fsl,mvf600-mscm"); > + mscm_base = of_iomap(np, 0); > + if (!mscm_base) > + return; > + > + /* route all shared peripheral interrupts to CP0 */ > + for (i = 0; i < 111; i++) > + __raw_writew(1, mscm_base + 0x880 + 2 * i); I second Arnd's comment on this. Can we have this setup done in bootloader? Shawn > + > + iounmap(mscm_base); > + > + irqchip_init(); > +} ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 3/4] ARM: dts: add SoC level device tree source for MVF600 2013-05-16 6:10 [PATCH v3 0/4] Add initial Freescale Vybrid MVF600 support Jingchang Lu 2013-05-16 6:10 ` [PATCH v3 1/4] ARM: imx: add MVF600 clock support Jingchang Lu 2013-05-16 6:10 ` [PATCH v3 2/4] ARM: imx: add initial support for MVF600 Jingchang Lu @ 2013-05-16 6:10 ` Jingchang Lu 2013-05-19 14:14 ` Shawn Guo 2013-05-16 6:10 ` [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts support Jingchang Lu 3 siblings, 1 reply; 19+ messages in thread From: Jingchang Lu @ 2013-05-16 6:10 UTC (permalink / raw) To: linux-arm-kernel Add SoC level device tree source for Freescale Vybrid MVF600. Signed-off-by: Jingchang Lu <b35083@freescale.com> --- v3: define mvf600 pinfunc ID as <mux_reg input_reg mux_mode input_val>. clean up code. arch/arm/boot/dts/mvf600-pinfunc.h | 810 +++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/mvf600.dtsi | 475 ++++++++++++++++++++++ 2 files changed, 1285 insertions(+) create mode 100644 arch/arm/boot/dts/mvf600-pinfunc.h create mode 100644 arch/arm/boot/dts/mvf600.dtsi diff --git a/arch/arm/boot/dts/mvf600-pinfunc.h b/arch/arm/boot/dts/mvf600-pinfunc.h new file mode 100644 index 0000000..355c580 --- /dev/null +++ b/arch/arm/boot/dts/mvf600-pinfunc.h @@ -0,0 +1,810 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_MVF600_PINFUNC_H +#define __DTS_MVF600_PINFUNC_H + +/* + * The pin function ID for MVF600 is a tuple of: + * <mux_reg input_reg mux_mode input_val> + */ + +#define ALT0 0x0 +#define ALT1 0x1 +#define ALT2 0x2 +#define ALT3 0x3 +#define ALT4 0x4 +#define ALT5 0x5 +#define ALT6 0x6 +#define ALT7 0x7 + + +#define MVF600_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 +#define MVF600_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 +#define MVF600_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 +#define MVF600_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0 +#define MVF600_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0 +#define MVF600_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0 +#define MVF600_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0 +#define MVF600_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0 +#define MVF600_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0 +#define MVF600_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0 +#define MVF600_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0 +#define MVF600_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0 +#define MVF600_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1 +#define MVF600_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0 +#define MVF600_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0 +#define MVF600_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0 +#define MVF600_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0 +#define MVF600_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0 +#define MVF600_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0 +#define MVF600_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0 +#define MVF600_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0 +#define MVF600_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0 +#define MVF600_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0 +#define MVF600_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0 +#define MVF600_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0 +#define MVF600_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0 +#define MVF600_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0 +#define MVF600_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1 +#define MVF600_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0 +#define MVF600_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0 +#define MVF600_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0 +#define MVF600_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0 +#define MVF600_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0 +#define MVF600_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0 +#define MVF600_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0 +#define MVF600_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0 +#define MVF600_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0 +#define MVF600_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0 +#define MVF600_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0 +#define MVF600_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0 +#define MVF600_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0 +#define MVF600_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0 +#define MVF600_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0 +#define MVF600_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0 +#define MVF600_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0 +#define MVF600_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0 +#define MVF600_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0 +#define MVF600_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0 +#define MVF600_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0 +#define MVF600_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0 +#define MVF600_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0 +#define MVF600_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0 +#define MVF600_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0 +#define MVF600_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0 +#define MVF600_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0 +#define MVF600_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0 +#define MVF600_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0 +#define MVF600_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0 +#define MVF600_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0 +#define MVF600_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0 +#define MVF600_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0 +#define MVF600_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0 +#define MVF600_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0 +#define MVF600_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0 +#define MVF600_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0 +#define MVF600_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0 +#define MVF600_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0 +#define MVF600_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0 +#define MVF600_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0 +#define MVF600_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0 +#define MVF600_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0 +#define MVF600_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0 +#define MVF600_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0 +#define MVF600_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0 +#define MVF600_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0 +#define MVF600_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0 +#define MVF600_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0 +#define MVF600_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0 +#define MVF600_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0 +#define MVF600_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0 +#define MVF600_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0 +#define MVF600_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0 +#define MVF600_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0 +#define MVF600_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0 +#define MVF600_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0 +#define MVF600_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0 +#define MVF600_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0 +#define MVF600_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0 +#define MVF600_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0 +#define MVF600_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0 +#define MVF600_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0 +#define MVF600_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0 +#define MVF600_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0 +#define MVF600_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0 +#define MVF600_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0 +#define MVF600_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0 +#define MVF600_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0 +#define MVF600_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0 +#define MVF600_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0 +#define MVF600_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0 +#define MVF600_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0 +#define MVF600_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0 +#define MVF600_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0 +#define MVF600_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0 +#define MVF600_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0 +#define MVF600_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0 +#define MVF600_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0 +#define MVF600_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0 +#define MVF600_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0 +#define MVF600_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0 +#define MVF600_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0 +#define MVF600_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0 +#define MVF600_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0 +#define MVF600_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0 +#define MVF600_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0 +#define MVF600_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0 +#define MVF600_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0 +#define MVF600_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0 +#define MVF600_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0 +#define MVF600_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0 +#define MVF600_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0 +#define MVF600_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0 +#define MVF600_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0 +#define MVF600_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1 +#define MVF600_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0 +#define MVF600_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0 +#define MVF600_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0 +#define MVF600_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0 +#define MVF600_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0 +#define MVF600_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0 +#define MVF600_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1 +#define MVF600_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0 +#define MVF600_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0 +#define MVF600_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0 +#define MVF600_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0 +#define MVF600_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0 +#define MVF600_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1 +#define MVF600_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0 +#define MVF600_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0 +#define MVF600_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0 +#define MVF600_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0 +#define MVF600_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0 +#define MVF600_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0 +#define MVF600_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0 +#define MVF600_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1 +#define MVF600_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0 +#define MVF600_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0 +#define MVF600_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0 +#define MVF600_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0 +#define MVF600_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0 +#define MVF600_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0 +#define MVF600_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0 +#define MVF600_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1 +#define MVF600_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0 +#define MVF600_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0 +#define MVF600_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0 +#define MVF600_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0 +#define MVF600_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0 +#define MVF600_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0 +#define MVF600_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0 +#define MVF600_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0 +#define MVF600_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0 +#define MVF600_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0 +#define MVF600_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0 +#define MVF600_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0 +#define MVF600_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0 +#define MVF600_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0 +#define MVF600_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0 +#define MVF600_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0 +#define MVF600_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0 +#define MVF600_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0 +#define MVF600_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0 +#define MVF600_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0 +#define MVF600_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0 +#define MVF600_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0 +#define MVF600_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0 +#define MVF600_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0 +#define MVF600_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0 +#define MVF600_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0 +#define MVF600_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0 +#define MVF600_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0 +#define MVF600_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0 +#define MVF600_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0 +#define MVF600_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0 +#define MVF600_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0 +#define MVF600_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0 +#define MVF600_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0 +#define MVF600_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0 +#define MVF600_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0 +#define MVF600_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0 +#define MVF600_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0 +#define MVF600_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0 +#define MVF600_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0 +#define MVF600_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0 +#define MVF600_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1 +#define MVF600_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1 +#define MVF600_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0 +#define MVF600_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0 +#define MVF600_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0 +#define MVF600_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1 +#define MVF600_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0 +#define MVF600_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0 +#define MVF600_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0 +#define MVF600_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0 +#define MVF600_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2 +#define MVF600_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0 +#define MVF600_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1 +#define MVF600_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0 +#define MVF600_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0 +#define MVF600_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0 +#define MVF600_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0 +#define MVF600_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0 +#define MVF600_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0 +#define MVF600_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0 +#define MVF600_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0 +#define MVF600_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0 +#define MVF600_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0 +#define MVF600_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0 +#define MVF600_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0 +#define MVF600_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0 +#define MVF600_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0 +#define MVF600_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0 +#define MVF600_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0 +#define MVF600_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0 +#define MVF600_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0 +#define MVF600_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0 +#define MVF600_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0 +#define MVF600_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0 +#define MVF600_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1 +#define MVF600_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0 +#define MVF600_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0 +#define MVF600_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0 +#define MVF600_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0 +#define MVF600_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1 +#define MVF600_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0 +#define MVF600_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0 +#define MVF600_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0 +#define MVF600_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0 +#define MVF600_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1 +#define MVF600_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0 +#define MVF600_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0 +#define MVF600_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0 +#define MVF600_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1 +#define MVF600_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0 +#define MVF600_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0 +#define MVF600_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0 +#define MVF600_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2 +#define MVF600_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0 +#define MVF600_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0 +#define MVF600_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0 +#define MVF600_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0 +#define MVF600_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0 +#define MVF600_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0 +#define MVF600_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0 +#define MVF600_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0 +#define MVF600_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0 +#define MVF600_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0 +#define MVF600_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0 +#define MVF600_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0 +#define MVF600_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0 +#define MVF600_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0 +#define MVF600_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0 +#define MVF600_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0 +#define MVF600_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1 +#define MVF600_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0 +#define MVF600_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0 +#define MVF600_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1 +#define MVF600_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0 +#define MVF600_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0 +#define MVF600_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0 +#define MVF600_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0 +#define MVF600_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0 +#define MVF600_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0 +#define MVF600_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0 +#define MVF600_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1 +#define MVF600_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0 +#define MVF600_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0 +#define MVF600_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0 +#define MVF600_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0 +#define MVF600_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0 +#define MVF600_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0 +#define MVF600_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0 +#define MVF600_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1 +#define MVF600_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0 +#define MVF600_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0 +#define MVF600_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0 +#define MVF600_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0 +#define MVF600_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0 +#define MVF600_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0 +#define MVF600_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1 +#define MVF600_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0 +#define MVF600_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0 +#define MVF600_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0 +#define MVF600_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0 +#define MVF600_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0 +#define MVF600_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0 +#define MVF600_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0 +#define MVF600_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0 +#define MVF600_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0 +#define MVF600_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0 +#define MVF600_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0 +#define MVF600_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0 +#define MVF600_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0 +#define MVF600_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0 +#define MVF600_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1 +#define MVF600_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0 +#define MVF600_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0 +#define MVF600_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0 +#define MVF600_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0 +#define MVF600_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0 +#define MVF600_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0 +#define MVF600_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0 +#define MVF600_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0 +#define MVF600_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0 +#define MVF600_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0 +#define MVF600_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0 +#define MVF600_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0 +#define MVF600_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0 +#define MVF600_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0 +#define MVF600_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0 +#define MVF600_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0 +#define MVF600_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0 +#define MVF600_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0 +#define MVF600_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0 +#define MVF600_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0 +#define MVF600_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0 +#define MVF600_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0 +#define MVF600_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0 +#define MVF600_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0 +#define MVF600_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0 +#define MVF600_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1 +#define MVF600_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1 +#define MVF600_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0 +#define MVF600_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0 +#define MVF600_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0 +#define MVF600_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1 +#define MVF600_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1 +#define MVF600_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0 +#define MVF600_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0 +#define MVF600_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0 +#define MVF600_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1 +#define MVF600_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 +#define MVF600_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 +#define MVF600_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 +#define MVF600_PAD_PTC12__ENET_RMII_RXD1 0x0E4 0x000 ALT1 0x0 +#define MVF600_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 +#define MVF600_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 +#define MVF600_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 +#define MVF600_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0 +#define MVF600_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0 +#define MVF600_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1 +#define MVF600_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2 +#define MVF600_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0 +#define MVF600_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0 +#define MVF600_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0 +#define MVF600_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1 +#define MVF600_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0 +#define MVF600_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2 +#define MVF600_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0 +#define MVF600_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0 +#define MVF600_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0 +#define MVF600_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0 +#define MVF600_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1 +#define MVF600_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0 +#define MVF600_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0 +#define MVF600_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0 +#define MVF600_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0 +#define MVF600_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0 +#define MVF600_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0 +#define MVF600_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1 +#define MVF600_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0 +#define MVF600_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2 +#define MVF600_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0 +#define MVF600_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0 +#define MVF600_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0 +#define MVF600_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0 +#define MVF600_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0 +#define MVF600_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0 +#define MVF600_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1 +#define MVF600_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0 +#define MVF600_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0 +#define MVF600_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0 +#define MVF600_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0 +#define MVF600_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0 +#define MVF600_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0 +#define MVF600_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0 +#define MVF600_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0 +#define MVF600_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0 +#define MVF600_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0 +#define MVF600_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0 +#define MVF600_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0 +#define MVF600_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0 +#define MVF600_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0 +#define MVF600_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0 +#define MVF600_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0 +#define MVF600_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0 +#define MVF600_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 +#define MVF600_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 +#define MVF600_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 +#define MVF600_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 +#define MVF600_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 +#define MVF600_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 +#define MVF600_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 +#define MVF600_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0 +#define MVF600_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0 +#define MVF600_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0 +#define MVF600_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0 +#define MVF600_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0 +#define MVF600_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0 +#define MVF600_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1 +#define MVF600_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0 +#define MVF600_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0 +#define MVF600_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0 +#define MVF600_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0 +#define MVF600_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0 +#define MVF600_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0 +#define MVF600_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0 +#define MVF600_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0 +#define MVF600_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0 +#define MVF600_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0 +#define MVF600_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0 +#define MVF600_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0 +#define MVF600_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0 +#define MVF600_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0 +#define MVF600_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0 +#define MVF600_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0 +#define MVF600_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0 +#define MVF600_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0 +#define MVF600_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0 +#define MVF600_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0 +#define MVF600_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0 +#define MVF600_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0 +#define MVF600_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0 +#define MVF600_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1 +#define MVF600_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0 +#define MVF600_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1 +#define MVF600_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0 +#define MVF600_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0 +#define MVF600_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0 +#define MVF600_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0 +#define MVF600_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0 +#define MVF600_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1 +#define MVF600_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0 +#define MVF600_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1 +#define MVF600_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0 +#define MVF600_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0 +#define MVF600_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0 +#define MVF600_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0 +#define MVF600_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0 +#define MVF600_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0 +#define MVF600_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0 +#define MVF600_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0 +#define MVF600_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0 +#define MVF600_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0 +#define MVF600_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0 +#define MVF600_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0 +#define MVF600_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0 +#define MVF600_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0 +#define MVF600_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0 +#define MVF600_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0 +#define MVF600_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0 +#define MVF600_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0 +#define MVF600_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0 +#define MVF600_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2 +#define MVF600_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0 +#define MVF600_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0 +#define MVF600_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0 +#define MVF600_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0 +#define MVF600_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0 +#define MVF600_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0 +#define MVF600_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2 +#define MVF600_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0 +#define MVF600_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0 +#define MVF600_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0 +#define MVF600_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0 +#define MVF600_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0 +#define MVF600_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0 +#define MVF600_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2 +#define MVF600_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0 +#define MVF600_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0 +#define MVF600_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0 +#define MVF600_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0 +#define MVF600_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0 +#define MVF600_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2 +#define MVF600_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0 +#define MVF600_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0 +#define MVF600_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0 +#define MVF600_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2 +#define MVF600_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0 +#define MVF600_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0 +#define MVF600_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0 +#define MVF600_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0 +#define MVF600_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0 +#define MVF600_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2 +#define MVF600_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0 +#define MVF600_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0 +#define MVF600_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0 +#define MVF600_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0 +#define MVF600_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0 +#define MVF600_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0 +#define MVF600_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0 +#define MVF600_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0 +#define MVF600_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0 +#define MVF600_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0 +#define MVF600_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0 +#define MVF600_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0 +#define MVF600_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1 +#define MVF600_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0 +#define MVF600_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0 +#define MVF600_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0 +#define MVF600_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0 +#define MVF600_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0 +#define MVF600_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0 +#define MVF600_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0 +#define MVF600_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0 +#define MVF600_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0 +#define MVF600_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0 +#define MVF600_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0 +#define MVF600_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0 +#define MVF600_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1 +#define MVF600_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0 +#define MVF600_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0 +#define MVF600_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0 +#define MVF600_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0 +#define MVF600_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1 +#define MVF600_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0 +#define MVF600_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0 +#define MVF600_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0 +#define MVF600_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0 +#define MVF600_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0 +#define MVF600_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0 +#define MVF600_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0 +#define MVF600_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0 +#define MVF600_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0 +#define MVF600_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0 +#define MVF600_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1 +#define MVF600_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0 +#define MVF600_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0 +#define MVF600_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0 +#define MVF600_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0 +#define MVF600_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0 +#define MVF600_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0 +#define MVF600_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0 +#define MVF600_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0 +#define MVF600_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0 +#define MVF600_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0 +#define MVF600_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0 +#define MVF600_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0 +#define MVF600_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0 +#define MVF600_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0 +#define MVF600_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0 +#define MVF600_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0 +#define MVF600_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0 +#define MVF600_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0 +#define MVF600_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0 +#define MVF600_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0 +#define MVF600_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0 +#define MVF600_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0 +#define MVF600_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0 +#define MVF600_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0 +#define MVF600_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0 +#define MVF600_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0 +#define MVF600_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0 +#define MVF600_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0 +#define MVF600_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0 +#define MVF600_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0 +#define MVF600_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2 +#define MVF600_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1 +#define MVF600_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0 +#define MVF600_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0 +#define MVF600_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0 +#define MVF600_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0 +#define MVF600_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0 +#define MVF600_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0 +#define MVF600_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2 +#define MVF600_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1 +#define MVF600_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0 +#define MVF600_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0 +#define MVF600_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0 +#define MVF600_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0 +#define MVF600_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0 +#define MVF600_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0 +#define MVF600_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0 +#define MVF600_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1 +#define MVF600_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0 +#define MVF600_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0 +#define MVF600_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0 +#define MVF600_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0 +#define MVF600_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0 +#define MVF600_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2 +#define MVF600_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0 +#define MVF600_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0 +#define MVF600_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0 +#define MVF600_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0 +#define MVF600_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0 +#define MVF600_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0 +#define MVF600_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0 +#define MVF600_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0 +#define MVF600_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0 +#define MVF600_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0 +#define MVF600_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0 +#define MVF600_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0 +#define MVF600_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0 +#define MVF600_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0 +#define MVF600_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0 +#define MVF600_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0 +#define MVF600_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0 +#define MVF600_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0 +#define MVF600_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0 +#define MVF600_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0 +#define MVF600_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0 +#define MVF600_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0 +#define MVF600_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0 +#define MVF600_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0 +#define MVF600_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0 +#define MVF600_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0 +#define MVF600_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0 +#define MVF600_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0 +#define MVF600_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0 +#define MVF600_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0 +#define MVF600_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0 +#define MVF600_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0 +#define MVF600_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0 +#define MVF600_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0 +#define MVF600_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0 +#define MVF600_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0 +#define MVF600_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0 +#define MVF600_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0 +#define MVF600_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0 +#define MVF600_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0 +#define MVF600_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0 +#define MVF600_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0 +#define MVF600_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0 +#define MVF600_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0 +#define MVF600_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0 +#define MVF600_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0 +#define MVF600_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0 +#define MVF600_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0 +#define MVF600_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0 +#define MVF600_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0 +#define MVF600_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0 +#define MVF600_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0 +#define MVF600_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0 +#define MVF600_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0 +#define MVF600_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0 +#define MVF600_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1 +#define MVF600_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0 +#define MVF600_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0 +#define MVF600_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0 +#define MVF600_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0 +#define MVF600_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0 +#define MVF600_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0 +#define MVF600_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0 +#define MVF600_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0 +#define MVF600_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0 +#define MVF600_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0 +#define MVF600_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0 +#define MVF600_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0 +#define MVF600_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0 +#define MVF600_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0 +#define MVF600_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0 +#define MVF600_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0 +#define MVF600_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0 +#define MVF600_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0 +#define MVF600_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0 +#define MVF600_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0 +#define MVF600_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0 +#define MVF600_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0 +#define MVF600_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0 +#define MVF600_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0 +#define MVF600_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0 +#define MVF600_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0 +#define MVF600_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0 +#define MVF600_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0 +#define MVF600_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0 +#define MVF600_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0 +#define MVF600_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0 +#define MVF600_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0 +#define MVF600_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0 +#define MVF600_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0 +#define MVF600_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0 +#define MVF600_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0 +#define MVF600_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0 +#define MVF600_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0 +#define MVF600_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0 +#define MVF600_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0 +#define MVF600_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0 +#define MVF600_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0 +#define MVF600_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0 +#define MVF600_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0 +#define MVF600_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0 +#define MVF600_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0 +#define MVF600_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0 +#define MVF600_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0 +#define MVF600_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0 +#define MVF600_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0 +#define MVF600_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0 +#define MVF600_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0 +#define MVF600_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0 +#define MVF600_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0 +#define MVF600_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0 +#define MVF600_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0 +#define MVF600_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0 +#define MVF600_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0 +#define MVF600_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0 +#define MVF600_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0 +#define MVF600_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0 +#define MVF600_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0 +#define MVF600_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0 +#define MVF600_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0 +#define MVF600_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0 +#define MVF600_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0 +#define MVF600_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0 +#define MVF600_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0 +#define MVF600_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0 +#define MVF600_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0 +#define MVF600_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0 +#define MVF600_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0 +#define MVF600_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0 +#define MVF600_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0 +#define MVF600_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0 +#define MVF600_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0 +#define MVF600_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0 +#define MVF600_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0 +#define MVF600_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0 +#define MVF600_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0 +#define MVF600_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0 +#define MVF600_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0 +#define MVF600_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0 +#define MVF600_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0 +#define MVF600_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0 +#define MVF600_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0 +#define MVF600_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0 +#define MVF600_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0 +#define MVF600_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0 +#define MVF600_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0 +#define MVF600_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0 +#define MVF600_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0 +#define MVF600_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0 +#define MVF600_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3 +#define MVF600_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0 +#define MVF600_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0 +#define MVF600_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0 +#define MVF600_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0 +#define MVF600_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3 +#define MVF600_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0 +#define MVF600_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0 +#define MVF600_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0 +#define MVF600_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0 +#define MVF600_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0 +#define MVF600_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0 +#define MVF600_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0 +#define MVF600_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0 +#define MVF600_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0 +#define MVF600_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0 +#define MVF600_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0 +#define MVF600_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0 +#define MVF600_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0 +#define MVF600_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0 +#define MVF600_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0 +#define MVF600_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0 +#define MVF600_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0 +#define MVF600_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0 +#define MVF600_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0 +#define MVF600_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0 +#define MVF600_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0 +#define MVF600_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0 +#define MVF600_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0 +#define MVF600_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0 +#define MVF600_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0 +#define MVF600_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0 +#define MVF600_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0 +#define MVF600_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3 +#define MVF600_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0 +#define MVF600_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0 +#define MVF600_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0 +#define MVF600_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0 +#define MVF600_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3 +#define MVF600_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 +#define MVF600_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 +#define MVF600_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 + +#endif diff --git a/arch/arm/boot/dts/mvf600.dtsi b/arch/arm/boot/dts/mvf600.dtsi new file mode 100644 index 0000000..a3c3353 --- /dev/null +++ b/arch/arm/boot/dts/mvf600.dtsi @@ -0,0 +1,475 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "skeleton.dtsi" +#include "mvf600-pinfunc.h" +#include <dt-bindings/clock/mvf600-clock.h> + +/ { + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + compatible = "arm,cortex-a5"; + device_type = "cpu"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + sxosc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + fxosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + aips0: aips-bus at 40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + reg = <0x40000000 0x70000>; + ranges; + + mscm: mscm at 40001000 { + compatible = "fsl,mvf600-mscm"; + reg = <0x40001000 0x1000>; + }; + + intc: interrupt-controller at 40002000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x40003000 0x1000>, + <0x40002100 0x100>; + }; + + L2: l2-cache at 40006000 { + compatible = "arm,pl310-cache"; + reg = <0x40006000 0x1000>; + cache-unified; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <2 2 2>; + }; + + uart0: serial at 40027000 { + compatible = "fsl,mvf600-uart","fsl,lpuart"; + reg = <0x40027000 0x1000>; + interrupts = <0 61 0x00>; + clocks = <&clks MVF600_CLK_UART0>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart1: serial at 40028000 { + compatible = "fsl,mvf600-uart","fsl,lpuart"; + reg = <0x40028000 0x1000>; + interrupts = <0 62 0x04>; + clocks = <&clks MVF600_CLK_UART1>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart2: serial at 40029000 { + compatible = "fsl,mvf600-uart","fsl,lpuart"; + reg = <0x40029000 0x1000>; + interrupts = <0 63 0x04>; + clocks = <&clks MVF600_CLK_UART2>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart3: serial at 4002a000 { + compatible = "fsl,mvf600-uart","fsl,lpuart"; + reg = <0x4002a000 0x1000>; + interrupts = <0 64 0x04>; + clocks = <&clks MVF600_CLK_UART3>; + clock-names = "ipg"; + status = "disabled"; + }; + + sai2: sai at 40031000 { + compatible = "fsl,mvf600-sai"; + reg = <0x40031000 0x1000>; + interrupts = <0 86 0x04>; + clocks = <&clks MVF600_CLK_SAI2>; + clock-names = "sai"; + status = "disabled"; + }; + + pit:pit at 40037000 { + compatible = "fsl,mvf600-pit"; + reg = <0x40037000 0x1000>; + interrupts = <0 39 0x04>; + clock-names = "pit"; + clocks = <&clks MVF600_CLK_PIT>; + }; + + wdog at 4003e000 { + compatible = "fsl,mvf600-wdt","fsl,imx21-wdt"; + reg = <0x4003e000 0x1000>; + clock-names = "wdog"; + clocks = <&clks MVF600_CLK_WDT>; + }; + + qspi0: quadspi at 40044000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mvf600-qspi"; + reg = <0x40044000 0x1000>; + interrupts = <0 24 0x04>; + clocks = <&clks MVF600_CLK_QSPI0_EN>, + <&clks MVF600_CLK_QSPI0>; + clock-names = "qspi0_en", "qspi0"; + status = "disabled"; + }; + + iomuxc: iomuxc at 40048000 { + compatible = "fsl,mvf600-iomuxc"; + reg = <0x40048000 0x1000>; + #gpio-range-cells = <2>; + + /* functions and groups pins */ + + dcu0 { + pinctrl_dcu0_1: dcu0grp_1 { + fsl,pins = < + MVF600_PAD_PTB8__GPIO_30 0x42 + MVF600_PAD_PTE0__DCU0_HSYNC 0x42 + MVF600_PAD_PTE1__DCU0_VSYNC 0x42 + MVF600_PAD_PTE2__DCU0_PCLK 0x42 + MVF600_PAD_PTE4__DCU0_DE 0x42 + MVF600_PAD_PTE5__DCU0_R0 0x42 + MVF600_PAD_PTE6__DCU0_R1 0x42 + MVF600_PAD_PTE7__DCU0_R2 0x42 + MVF600_PAD_PTE8__DCU0_R3 0x42 + MVF600_PAD_PTE9__DCU0_R4 0x42 + MVF600_PAD_PTE10__DCU0_R5 0x42 + MVF600_PAD_PTE11__DCU0_R6 0x42 + MVF600_PAD_PTE12__DCU0_R7 0x42 + MVF600_PAD_PTE13__DCU0_G0 0x42 + MVF600_PAD_PTE14__DCU0_G1 0x42 + MVF600_PAD_PTE15__DCU0_G2 0x42 + MVF600_PAD_PTE16__DCU0_G3 0x42 + MVF600_PAD_PTE17__DCU0_G4 0x42 + MVF600_PAD_PTE18__DCU0_G5 0x42 + MVF600_PAD_PTE19__DCU0_G6 0x42 + MVF600_PAD_PTE20__DCU0_G7 0x42 + MVF600_PAD_PTE21__DCU0_B0 0x42 + MVF600_PAD_PTE22__DCU0_B1 0x42 + MVF600_PAD_PTE23__DCU0_B2 0x42 + MVF600_PAD_PTE24__DCU0_B3 0x42 + MVF600_PAD_PTE25__DCU0_B4 0x42 + MVF600_PAD_PTE26__DCU0_B5 0x42 + MVF600_PAD_PTE27__DCU0_B6 0x42 + MVF600_PAD_PTE28__DCU0_B7 0x42 + >; + }; + }; + + dspi0 { + pinctrl_dspi0_1: dspi0grp_1 { + fsl,pins = < + MVF600_PAD_PTB19__DSPI0_CS0 0x1182 + MVF600_PAD_PTB20__DSPI0_SIN 0x1181 + MVF600_PAD_PTB21__DSPI0_SOUT 0x1182 + MVF600_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp_1 { + fsl,pins = < + MVF600_PAD_PTA24__ESDHC1_CLK 0x31ef + MVF600_PAD_PTA25__ESDHC1_CMD 0x31ef + MVF600_PAD_PTA26__ESDHC1_DAT0 0x31ef + MVF600_PAD_PTA27__ESDHC1_DAT1 0x31ef + MVF600_PAD_PTA28__ESDHC1_DATA2 0x31ef + MVF600_PAD_PTA29__ESDHC1_DAT3 0x31ef + MVF600_PAD_PTA7__GPIO_134 0x219d + >; + }; + }; + + fec0 { + pinctrl_fec0_1: fec0grp_1 { + fsl,pins = < + MVF600_PAD_PTA6__RMII_CLKIN 0x30d1 + MVF600_PAD_PTC0__ENET_RMII0_MDC 0x30d3 + MVF600_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 + MVF600_PAD_PTC2__ENET_RMII0_CRS 0x30d1 + MVF600_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 + MVF600_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 + MVF600_PAD_PTC5__ENET_RMII0_RXER 0x30d1 + MVF600_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 + MVF600_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 + MVF600_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 + >; + }; + }; + + fec1 { + pinctrl_fec1_1: fec1grp_1 { + fsl,pins = < + MVF600_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + MVF600_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + MVF600_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + MVF600_PAD_PTC12__ENET_RMII_RXD1 0x30d1 + MVF600_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + MVF600_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + MVF600_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + MVF600_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + MVF600_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + }; + + i2c0 { + pinctrl_i2c0_1: i2c0grp_1 { + fsl,pins = < + MVF600_PAD_PTB14__I2C0_SCL 0x30d3 + MVF600_PAD_PTB15__I2C0_SDA 0x30d3 + >; + }; + }; + + pwm0 { + pinctrl_pwm0_1: pwm0grp_1 { + fsl,pins = < + MVF600_PAD_PTB0__FTM0_CH0 0x1582 + MVF600_PAD_PTB1__FTM0_CH1 0x1582 + MVF600_PAD_PTB2__FTM0_CH2 0x1582 + MVF600_PAD_PTB3__FTM0_CH3 0x1582 + MVF600_PAD_PTB6__FTM0_CH6 0x1582 + MVF600_PAD_PTB7__FTM0_CH7 0x1582 + >; + }; + }; + + qspi0 { + pinctrl_qspi0_1: qspi0grp_1 { + fsl,pins = < + MVF600_PAD_PTD0__QSPI0_A_QSCK 0x307b + MVF600_PAD_PTD1__QSPI0_A_CS0 0x307f + MVF600_PAD_PTD2__QSPI0_A_DATA3 0x3073 + MVF600_PAD_PTD3__QSPI0_A_DATA2 0x3073 + MVF600_PAD_PTD4__QSPI0_A_DATA1 0x3073 + MVF600_PAD_PTD5__QSPI0_A_DATA0 0x307b + MVF600_PAD_PTD7__QSPI0_B_QSCK 0x307b + MVF600_PAD_PTD8__QSPI0_B_CS0 0x307f + MVF600_PAD_PTD9__QSPI0_B_DATA3 0x3073 + MVF600_PAD_PTD10__QSPI0_B_DATA2 0x3073 + MVF600_PAD_PTD11__QSPI0_B_DATA1 0x3073 + MVF600_PAD_PTD12__QSPI0_B_DATA0 0x307b + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MVF600_PAD_PTA16__SAI2_TX_BCLK 0x02ed + MVF600_PAD_PTA18__SAI2_TX_DATA 0x02ee + MVF600_PAD_PTA19__SAI2_TX_SYNC 0x02ed + MVF600_PAD_PTA21__SAI2_RX_BCLK 0x02ed + MVF600_PAD_PTA22__SAI2_RX_DATA 0x02ed + MVF600_PAD_PTA23__SAI2_RX_SYNC 0x02ed + MVF600_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed + >; + }; + }; + + touchscreen0 { + pinctrl_ts0_1: ts0grp_1 { + fsl,pins = < + MVF600_PAD_PTA31__GPIO_21 0x219d + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp_1 { + fsl,pins = < + MVF600_PAD_PTB4__UART1_TX(0x21a2) + MVF600_PAD_PTB5__UART1_RX(0x21a1) + >; + }; + }; + + usbvbus { + pinctrl_usbvbus_1: usbvbusgrp_1 { + fsl,pins = < + MVF600_PAD_PTA24__USB1_VBUS_EN(0x219c) + MVF600_PAD_PTA16__USB0_VBUS_EN(0x219c) + >; + }; + }; + + }; + + gpio1: gpio at 40049000 { + compatible = "fsl,mvf600-gpio"; + reg = <0x40049000 0x1000 0x400ff000 0x40>; + interrupts = <0 107 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 32>; + }; + + gpio2: gpio at 4004a000 { + compatible = "fsl,mvf600-gpio"; + reg = <0x4004a000 0x1000 0x400ff040 0x40>; + interrupts = <0 108 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 32 32>; + }; + + gpio3: gpio at 4004b000 { + compatible = "fsl,mvf600-gpio"; + reg = <0x4004b000 0x1000 0x400ff080 0x40>; + interrupts = <0 109 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 64 32>; + }; + + gpio4: gpio at 4004c000 { + compatible = "fsl,mvf600-gpio"; + reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; + interrupts = <0 110 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 96 32>; + }; + + gpio5: gpio at 4004d000 { + compatible = "fsl,mvf600-gpio"; + reg = <0x4004d000 0x1000 0x400ff100 0x40>; + interrupts = <0 111 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 128 7>; + }; + + anatop at 40050000 { + compatible = "fsl,mvf600-anatop"; + reg = <0x40050000 0x1000>; + }; + + i2c0: i2c at 40066000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mvf600-i2c"; + reg = <0x40066000 0x1000>; + interrupts =<0 71 0x04>; + clocks = <&clks MVF600_CLK_I2C0>; + clock-names = "ipg"; + status = "disabled"; + }; + + clks: ccm at 4006b000 { + compatible = "fsl,mvf600-ccm"; + reg = <0x4006b000 0x1000>; + #clock-cells = <1>; + }; + }; + + aips1: aips-bus at 40080000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40080000 0x80000>; + ranges; + + uart4: serial at 400a9000 { + compatible = "fsl,mvf600-uart","fsl,lpuart"; + reg = <0x400a9000 0x1000>; + interrupts = <0 65 0x04>; + clocks = <&clks MVF600_CLK_UART4>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart5: serial at 400aa000 { + compatible = "fsl,mvf600-uart","fsl,lpuart"; + reg = <0x400aa000 0x1000>; + interrupts = <0 66 0x04>; + clocks = <&clks MVF600_CLK_UART5>; + clock-names = "ipg"; + status = "disabled"; + }; + + fec0: ethernet at 400d0000 { + compatible = "fsl,mvf600-fec","fsl,mvf-fec"; + reg = <0x400d0000 0x1000>; + interrupts = <0 78 0x04>; + clocks = <&clks MVF600_CLK_ENET>, + <&clks MVF600_CLK_ENET>, + <&clks MVF600_CLK_ENET>; + clock-names = "ipg", "ahb", "ptp"; + }; + + fec1: ethernet at 400d1000 { + compatible = "fsl,mvf600-fec","fsl,mvf-fec"; + reg = <0x400d1000 0x1000>; + interrupts = <0 79 0x04>; + clocks = <&clks MVF600_CLK_ENET>, + <&clks MVF600_CLK_ENET>, + <&clks MVF600_CLK_ENET>; + clock-names = "ipg", "ahb", "ptp"; + }; + }; + }; +}; -- 1.8.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 3/4] ARM: dts: add SoC level device tree source for MVF600 2013-05-16 6:10 ` [PATCH v3 3/4] ARM: dts: add SoC level device tree source " Jingchang Lu @ 2013-05-19 14:14 ` Shawn Guo 0 siblings, 0 replies; 19+ messages in thread From: Shawn Guo @ 2013-05-19 14:14 UTC (permalink / raw) To: linux-arm-kernel On Thu, May 16, 2013 at 02:10:47PM +0800, Jingchang Lu wrote: > diff --git a/arch/arm/boot/dts/mvf600.dtsi b/arch/arm/boot/dts/mvf600.dtsi > new file mode 100644 > index 0000000..a3c3353 > --- /dev/null > +++ b/arch/arm/boot/dts/mvf600.dtsi > @@ -0,0 +1,475 @@ > +/* > + * Copyright 2013 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#include "skeleton.dtsi" > +#include "mvf600-pinfunc.h" > +#include <dt-bindings/clock/mvf600-clock.h> > + > +/ { > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + serial4 = &uart4; > + serial5 = &uart5; > + gpio0 = &gpio1; > + gpio1 = &gpio2; > + gpio2 = &gpio3; > + gpio3 = &gpio4; > + gpio4 = &gpio5; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu at 0 { > + compatible = "arm,cortex-a5"; > + device_type = "cpu"; > + reg = <0x0>; > + next-level-cache = <&L2>; > + }; > + }; > + > + clocks { > + #address-cells = <1>; > + #size-cells = <0>; > + > + sxosc { > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + }; > + > + fxosc { > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + }; > + }; > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + interrupt-parent = <&intc>; > + ranges; > + > + aips0: aips-bus at 40000000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&intc>; > + reg = <0x40000000 0x70000>; > + ranges; > + > + mscm: mscm at 40001000 { > + compatible = "fsl,mvf600-mscm"; > + reg = <0x40001000 0x1000>; > + }; > + > + intc: interrupt-controller at 40002000 { > + compatible = "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-controller; > + reg = <0x40003000 0x1000>, > + <0x40002100 0x100>; > + }; > + > + L2: l2-cache at 40006000 { > + compatible = "arm,pl310-cache"; > + reg = <0x40006000 0x1000>; > + cache-unified; > + cache-level = <2>; > + arm,data-latency = <1 1 1>; > + arm,tag-latency = <2 2 2>; > + }; > + > + uart0: serial at 40027000 { > + compatible = "fsl,mvf600-uart","fsl,lpuart"; We generally avoid using generic compatible string for IP block but prefer to encode SoC name in the string to define the version/revision using SoC part name. That said, "fsl,mvf600-uart" is good enough to specify the IP block. More on this later. > + reg = <0x40027000 0x1000>; > + interrupts = <0 61 0x00>; > + clocks = <&clks MVF600_CLK_UART0>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + uart1: serial at 40028000 { > + compatible = "fsl,mvf600-uart","fsl,lpuart"; > + reg = <0x40028000 0x1000>; > + interrupts = <0 62 0x04>; > + clocks = <&clks MVF600_CLK_UART1>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + uart2: serial at 40029000 { > + compatible = "fsl,mvf600-uart","fsl,lpuart"; > + reg = <0x40029000 0x1000>; > + interrupts = <0 63 0x04>; > + clocks = <&clks MVF600_CLK_UART2>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + uart3: serial at 4002a000 { > + compatible = "fsl,mvf600-uart","fsl,lpuart"; > + reg = <0x4002a000 0x1000>; > + interrupts = <0 64 0x04>; > + clocks = <&clks MVF600_CLK_UART3>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + sai2: sai at 40031000 { > + compatible = "fsl,mvf600-sai"; > + reg = <0x40031000 0x1000>; > + interrupts = <0 86 0x04>; > + clocks = <&clks MVF600_CLK_SAI2>; > + clock-names = "sai"; > + status = "disabled"; > + }; > + > + pit:pit at 40037000 { Nit: put a space after "pit:". > + compatible = "fsl,mvf600-pit"; > + reg = <0x40037000 0x1000>; > + interrupts = <0 39 0x04>; > + clock-names = "pit"; > + clocks = <&clks MVF600_CLK_PIT>; Nit: I've seen some nodes have "clock-names" before "clocks" and others have it after "clocks". Please be consistent. > + }; > + > + wdog at 4003e000 { > + compatible = "fsl,mvf600-wdt","fsl,imx21-wdt"; Nit: please have a space between two strings (after comma). > + reg = <0x4003e000 0x1000>; > + clock-names = "wdog"; > + clocks = <&clks MVF600_CLK_WDT>; > + }; > + > + qspi0: quadspi at 40044000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,mvf600-qspi"; > + reg = <0x40044000 0x1000>; > + interrupts = <0 24 0x04>; > + clocks = <&clks MVF600_CLK_QSPI0_EN>, > + <&clks MVF600_CLK_QSPI0>; > + clock-names = "qspi0_en", "qspi0"; > + status = "disabled"; > + }; > + > + iomuxc: iomuxc at 40048000 { > + compatible = "fsl,mvf600-iomuxc"; > + reg = <0x40048000 0x1000>; > + #gpio-range-cells = <2>; > + > + /* functions and groups pins */ > + > + dcu0 { > + pinctrl_dcu0_1: dcu0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTB8__GPIO_30 0x42 > + MVF600_PAD_PTE0__DCU0_HSYNC 0x42 > + MVF600_PAD_PTE1__DCU0_VSYNC 0x42 > + MVF600_PAD_PTE2__DCU0_PCLK 0x42 > + MVF600_PAD_PTE4__DCU0_DE 0x42 > + MVF600_PAD_PTE5__DCU0_R0 0x42 > + MVF600_PAD_PTE6__DCU0_R1 0x42 > + MVF600_PAD_PTE7__DCU0_R2 0x42 > + MVF600_PAD_PTE8__DCU0_R3 0x42 > + MVF600_PAD_PTE9__DCU0_R4 0x42 > + MVF600_PAD_PTE10__DCU0_R5 0x42 > + MVF600_PAD_PTE11__DCU0_R6 0x42 > + MVF600_PAD_PTE12__DCU0_R7 0x42 > + MVF600_PAD_PTE13__DCU0_G0 0x42 > + MVF600_PAD_PTE14__DCU0_G1 0x42 > + MVF600_PAD_PTE15__DCU0_G2 0x42 > + MVF600_PAD_PTE16__DCU0_G3 0x42 > + MVF600_PAD_PTE17__DCU0_G4 0x42 > + MVF600_PAD_PTE18__DCU0_G5 0x42 > + MVF600_PAD_PTE19__DCU0_G6 0x42 > + MVF600_PAD_PTE20__DCU0_G7 0x42 > + MVF600_PAD_PTE21__DCU0_B0 0x42 > + MVF600_PAD_PTE22__DCU0_B1 0x42 > + MVF600_PAD_PTE23__DCU0_B2 0x42 > + MVF600_PAD_PTE24__DCU0_B3 0x42 > + MVF600_PAD_PTE25__DCU0_B4 0x42 > + MVF600_PAD_PTE26__DCU0_B5 0x42 > + MVF600_PAD_PTE27__DCU0_B6 0x42 > + MVF600_PAD_PTE28__DCU0_B7 0x42 > + >; > + }; > + }; > + > + dspi0 { > + pinctrl_dspi0_1: dspi0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTB19__DSPI0_CS0 0x1182 > + MVF600_PAD_PTB20__DSPI0_SIN 0x1181 > + MVF600_PAD_PTB21__DSPI0_SOUT 0x1182 > + MVF600_PAD_PTB22__DSPI0_SCK 0x1182 > + >; > + }; > + }; > + > + esdhc1 { > + pinctrl_esdhc1_1: esdhc1grp_1 { > + fsl,pins = < > + MVF600_PAD_PTA24__ESDHC1_CLK 0x31ef > + MVF600_PAD_PTA25__ESDHC1_CMD 0x31ef > + MVF600_PAD_PTA26__ESDHC1_DAT0 0x31ef > + MVF600_PAD_PTA27__ESDHC1_DAT1 0x31ef > + MVF600_PAD_PTA28__ESDHC1_DATA2 0x31ef > + MVF600_PAD_PTA29__ESDHC1_DAT3 0x31ef > + MVF600_PAD_PTA7__GPIO_134 0x219d > + >; > + }; > + }; > + > + fec0 { > + pinctrl_fec0_1: fec0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTA6__RMII_CLKIN 0x30d1 > + MVF600_PAD_PTC0__ENET_RMII0_MDC 0x30d3 > + MVF600_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 > + MVF600_PAD_PTC2__ENET_RMII0_CRS 0x30d1 > + MVF600_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 > + MVF600_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 > + MVF600_PAD_PTC5__ENET_RMII0_RXER 0x30d1 > + MVF600_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 > + MVF600_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 > + MVF600_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 > + >; > + }; > + }; > + > + fec1 { > + pinctrl_fec1_1: fec1grp_1 { > + fsl,pins = < > + MVF600_PAD_PTC9__ENET_RMII1_MDC 0x30d2 > + MVF600_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 > + MVF600_PAD_PTC11__ENET_RMII1_CRS 0x30d1 > + MVF600_PAD_PTC12__ENET_RMII_RXD1 0x30d1 > + MVF600_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 > + MVF600_PAD_PTC14__ENET_RMII1_RXER 0x30d1 > + MVF600_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 > + MVF600_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 > + MVF600_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 > + >; > + }; > + }; > + > + i2c0 { > + pinctrl_i2c0_1: i2c0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTB14__I2C0_SCL 0x30d3 > + MVF600_PAD_PTB15__I2C0_SDA 0x30d3 > + >; > + }; > + }; > + > + pwm0 { > + pinctrl_pwm0_1: pwm0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTB0__FTM0_CH0 0x1582 > + MVF600_PAD_PTB1__FTM0_CH1 0x1582 > + MVF600_PAD_PTB2__FTM0_CH2 0x1582 > + MVF600_PAD_PTB3__FTM0_CH3 0x1582 > + MVF600_PAD_PTB6__FTM0_CH6 0x1582 > + MVF600_PAD_PTB7__FTM0_CH7 0x1582 > + >; > + }; > + }; > + > + qspi0 { > + pinctrl_qspi0_1: qspi0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTD0__QSPI0_A_QSCK 0x307b > + MVF600_PAD_PTD1__QSPI0_A_CS0 0x307f > + MVF600_PAD_PTD2__QSPI0_A_DATA3 0x3073 > + MVF600_PAD_PTD3__QSPI0_A_DATA2 0x3073 > + MVF600_PAD_PTD4__QSPI0_A_DATA1 0x3073 > + MVF600_PAD_PTD5__QSPI0_A_DATA0 0x307b > + MVF600_PAD_PTD7__QSPI0_B_QSCK 0x307b > + MVF600_PAD_PTD8__QSPI0_B_CS0 0x307f > + MVF600_PAD_PTD9__QSPI0_B_DATA3 0x3073 > + MVF600_PAD_PTD10__QSPI0_B_DATA2 0x3073 > + MVF600_PAD_PTD11__QSPI0_B_DATA1 0x3073 > + MVF600_PAD_PTD12__QSPI0_B_DATA0 0x307b > + >; > + }; > + }; > + > + sai2 { > + pinctrl_sai2_1: sai2grp_1 { > + fsl,pins = < > + MVF600_PAD_PTA16__SAI2_TX_BCLK 0x02ed > + MVF600_PAD_PTA18__SAI2_TX_DATA 0x02ee > + MVF600_PAD_PTA19__SAI2_TX_SYNC 0x02ed > + MVF600_PAD_PTA21__SAI2_RX_BCLK 0x02ed > + MVF600_PAD_PTA22__SAI2_RX_DATA 0x02ed > + MVF600_PAD_PTA23__SAI2_RX_SYNC 0x02ed > + MVF600_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed > + >; > + }; > + }; > + > + touchscreen0 { > + pinctrl_ts0_1: ts0grp_1 { > + fsl,pins = < > + MVF600_PAD_PTA31__GPIO_21 0x219d > + >; > + }; > + }; The pin group represented in <soc>.dtsi should be those defined by SoC design. This group does not look like the case. > + > + uart1 { > + pinctrl_uart1_1: uart1grp_1 { > + fsl,pins = < > + MVF600_PAD_PTB4__UART1_TX(0x21a2) > + MVF600_PAD_PTB5__UART1_RX(0x21a1) Something forgot to change from last version. > + >; > + }; > + }; > + > + usbvbus { > + pinctrl_usbvbus_1: usbvbusgrp_1 { > + fsl,pins = < > + MVF600_PAD_PTA24__USB1_VBUS_EN(0x219c) > + MVF600_PAD_PTA16__USB0_VBUS_EN(0x219c) Ditto > + >; > + }; > + }; > + > + }; > + > + gpio1: gpio at 40049000 { > + compatible = "fsl,mvf600-gpio"; > + reg = <0x40049000 0x1000 0x400ff000 0x40>; > + interrupts = <0 107 0x04>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 0 32>; > + }; > + > + gpio2: gpio at 4004a000 { > + compatible = "fsl,mvf600-gpio"; > + reg = <0x4004a000 0x1000 0x400ff040 0x40>; > + interrupts = <0 108 0x04>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 32 32>; > + }; > + > + gpio3: gpio at 4004b000 { > + compatible = "fsl,mvf600-gpio"; > + reg = <0x4004b000 0x1000 0x400ff080 0x40>; > + interrupts = <0 109 0x04>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 64 32>; > + }; > + > + gpio4: gpio at 4004c000 { > + compatible = "fsl,mvf600-gpio"; > + reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; > + interrupts = <0 110 0x04>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 96 32>; > + }; > + > + gpio5: gpio at 4004d000 { > + compatible = "fsl,mvf600-gpio"; > + reg = <0x4004d000 0x1000 0x400ff100 0x40>; > + interrupts = <0 111 0x04>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 128 7>; > + }; > + > + anatop at 40050000 { > + compatible = "fsl,mvf600-anatop"; > + reg = <0x40050000 0x1000>; > + }; > + > + i2c0: i2c at 40066000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,mvf600-i2c"; > + reg = <0x40066000 0x1000>; > + interrupts =<0 71 0x04>; > + clocks = <&clks MVF600_CLK_I2C0>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + clks: ccm at 4006b000 { > + compatible = "fsl,mvf600-ccm"; > + reg = <0x4006b000 0x1000>; > + #clock-cells = <1>; > + }; > + }; > + > + aips1: aips-bus at 40080000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x40080000 0x80000>; > + ranges; > + > + uart4: serial at 400a9000 { > + compatible = "fsl,mvf600-uart","fsl,lpuart"; > + reg = <0x400a9000 0x1000>; > + interrupts = <0 65 0x04>; > + clocks = <&clks MVF600_CLK_UART4>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + uart5: serial at 400aa000 { > + compatible = "fsl,mvf600-uart","fsl,lpuart"; > + reg = <0x400aa000 0x1000>; > + interrupts = <0 66 0x04>; > + clocks = <&clks MVF600_CLK_UART5>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + fec0: ethernet at 400d0000 { > + compatible = "fsl,mvf600-fec","fsl,mvf-fec"; "fsl,mvf-fec" is not a good compatible string. I will try to send a patch to change fec driver on this. Shawn > + reg = <0x400d0000 0x1000>; > + interrupts = <0 78 0x04>; > + clocks = <&clks MVF600_CLK_ENET>, > + <&clks MVF600_CLK_ENET>, > + <&clks MVF600_CLK_ENET>; > + clock-names = "ipg", "ahb", "ptp"; > + }; > + > + fec1: ethernet at 400d1000 { > + compatible = "fsl,mvf600-fec","fsl,mvf-fec"; > + reg = <0x400d1000 0x1000>; > + interrupts = <0 79 0x04>; > + clocks = <&clks MVF600_CLK_ENET>, > + <&clks MVF600_CLK_ENET>, > + <&clks MVF600_CLK_ENET>; > + clock-names = "ipg", "ahb", "ptp"; > + }; > + }; > + }; > +}; > -- > 1.8.0 > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts support 2013-05-16 6:10 [PATCH v3 0/4] Add initial Freescale Vybrid MVF600 support Jingchang Lu ` (2 preceding siblings ...) 2013-05-16 6:10 ` [PATCH v3 3/4] ARM: dts: add SoC level device tree source " Jingchang Lu @ 2013-05-16 6:10 ` Jingchang Lu 2013-05-19 15:29 ` Shawn Guo 3 siblings, 1 reply; 19+ messages in thread From: Jingchang Lu @ 2013-05-16 6:10 UTC (permalink / raw) To: linux-arm-kernel Add initial MVF600 Tower board support with uart, fec, i2c, qspi, and sai enabled. Signed-off-by: Xiaochun Li <b41219@freescale.com> Signed-off-by: Jingchang Lu <b35083@freescale.com> --- v3: split DTS support to SoC and board patches. sort node by alphabet order of labels. arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/mvf600-twr.dts | 108 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mvf600-twr.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 87e603c..968164b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -122,7 +122,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ imx6q-sbc6x.dtb \ - imx6sl-evk.dtb + imx6sl-evk.dtb \ + mvf600-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx23-olinuxino.dtb \ imx23-stmp378x_devb.dtb \ diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts new file mode 100644 index 0000000..fe2e0e6 --- /dev/null +++ b/arch/arm/boot/dts/mvf600-twr.dts @@ -0,0 +1,108 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "mvf600.dtsi" + +/ { + model = "MVF600 Tower Board"; + compatible = "fsl,mvf600-twr", "fsl,mvf600"; + + chosen { + bootargs = "console=ttyLP1,115200"; + }; + + memory { + reg = <0x80000000 0x8000000>; + }; + + clocks { + audio_ext { + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + enet_ext { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + sound { + compatible = "fsl,mvf600-audio-sgtl5000"; + model = "mvf600-sgtl5000"; + sai-controller = <&sai2>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + +}; + +&fec0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec0_1>; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1_1>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_1>; + + codec: sgtl5000 at 0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&clks MVF600_CLK_SAI2>; + }; +}; + +&qspi0 { /* QuadSPI0 */ + fsl,spi-num-chipselects = <1>; + fsl,spi-flash-chipselects = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0_1>; + status = "okay"; + + flash: s25fl128s at 0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl128s"; + spi-max-frequency = <20000000>; + reg = <0>; + linux,modalias = "m25p80"; + modal = "s25fl128s"; + partition at 0 { + label = "s25fl128s"; + reg = <0x0 0x1000000>; + }; + }; +}; + +&sai2 { + fsl,mode = "i2s-slave"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; -- 1.8.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts support 2013-05-16 6:10 ` [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts support Jingchang Lu @ 2013-05-19 15:29 ` Shawn Guo 2013-05-20 5:01 ` Lu Jingchang-B35083 0 siblings, 1 reply; 19+ messages in thread From: Shawn Guo @ 2013-05-19 15:29 UTC (permalink / raw) To: linux-arm-kernel On Thu, May 16, 2013 at 02:10:48PM +0800, Jingchang Lu wrote: > Add initial MVF600 Tower board support with uart, fec, > i2c, qspi, and sai enabled. > > Signed-off-by: Xiaochun Li <b41219@freescale.com> > Signed-off-by: Jingchang Lu <b35083@freescale.com> > --- > v3: > split DTS support to SoC and board patches. > sort node by alphabet order of labels. > > arch/arm/boot/dts/Makefile | 3 +- > arch/arm/boot/dts/mvf600-twr.dts | 108 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 110 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/boot/dts/mvf600-twr.dts > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 87e603c..968164b 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -122,7 +122,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ > imx6q-sabrelite.dtb \ > imx6q-sabresd.dtb \ > imx6q-sbc6x.dtb \ > - imx6sl-evk.dtb > + imx6sl-evk.dtb \ > + mvf600-twr.dtb > dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ > imx23-olinuxino.dtb \ > imx23-stmp378x_devb.dtb \ > diff --git a/arch/arm/boot/dts/mvf600-twr.dts b/arch/arm/boot/dts/mvf600-twr.dts > new file mode 100644 > index 0000000..fe2e0e6 > --- /dev/null > +++ b/arch/arm/boot/dts/mvf600-twr.dts > @@ -0,0 +1,108 @@ > +/* > + * Copyright 2013 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +/dts-v1/; > +#include "mvf600.dtsi" > + > +/ { > + model = "MVF600 Tower Board"; > + compatible = "fsl,mvf600-twr", "fsl,mvf600"; > + > + chosen { > + bootargs = "console=ttyLP1,115200"; > + }; > + > + memory { > + reg = <0x80000000 0x8000000>; > + }; > + > + clocks { > + audio_ext { > + compatible = "fixed-clock"; > + clock-frequency = <24576000>; > + }; > + > + enet_ext { > + compatible = "fixed-clock"; > + clock-frequency = <50000000>; > + }; > + }; > + > + sound { > + compatible = "fsl,mvf600-audio-sgtl5000"; > + model = "mvf600-sgtl5000"; > + sai-controller = <&sai2>; > + audio-codec = <&codec>; > + audio-routing = > + "MIC_IN", "Mic Jack", > + "Mic Jack", "Mic Bias", > + "Headphone Jack", "HP_OUT"; > + }; Has this been tested against mainline kernel? If not, please remove it. > + > +}; > + > +&fec0 { > + phy-mode = "rmii"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec0_1>; > +}; > + > +&fec1 { > + phy-mode = "rmii"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec1_1>; > +}; For the peripherals where the availability can be a decision of board designers, we generally disable them in <soc>.dtsi by default with status = "disabled", and only enable them on boards where they are available in <board>.dts with status = "okay". One way to judge this type of peripherals could be seeing if they will need to have their pins routed on boards to function. > + > +&i2c0 { > + status = "okay"; We generally put status at the end of property list of a node. > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c0_1>; > + > + codec: sgtl5000 at 0a { > + compatible = "fsl,sgtl5000"; > + reg = <0x0a>; > + clocks = <&clks MVF600_CLK_SAI2>; The sgtl5000 uses SAI2 clock? > + }; > +}; Is i2c-imx driver working for mvf600 right now? > + > +&qspi0 { /* QuadSPI0 */ > + fsl,spi-num-chipselects = <1>; > + fsl,spi-flash-chipselects = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_qspi0_1>; > + status = "okay"; > + > + flash: s25fl128s at 0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "spansion,s25fl128s"; > + spi-max-frequency = <20000000>; > + reg = <0>; > + linux,modalias = "m25p80"; > + modal = "s25fl128s"; > + partition at 0 { > + label = "s25fl128s"; > + reg = <0x0 0x1000000>; > + }; > + }; > +}; Do we have a QuadSPI driver on mainline kernel? Please only add it when it's been tested against mainline kernel. > + > +&sai2 { > + fsl,mode = "i2s-slave"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_sai2_1>; > + status = "okay"; > +}; Ditto Shawn > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1_1>; > + status = "okay"; > +}; > -- > 1.8.0 > > ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts support 2013-05-19 15:29 ` Shawn Guo @ 2013-05-20 5:01 ` Lu Jingchang-B35083 2013-05-20 5:53 ` Shawn Guo 0 siblings, 1 reply; 19+ messages in thread From: Lu Jingchang-B35083 @ 2013-05-20 5:01 UTC (permalink / raw) To: linux-arm-kernel >> + >> + sound { >> + compatible = "fsl,mvf600-audio-sgtl5000"; >> + model = "mvf600-sgtl5000"; >> + sai-controller = <&sai2>; >> + audio-codec = <&codec>; >> + audio-routing = >> + "MIC_IN", "Mic Jack", >> + "Mic Jack", "Mic Bias", >> + "Headphone Jack", "HP_OUT"; >> + }; > >Has this been tested against mainline kernel? If not, please remove it. > >> + clock-frequency = <100000>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_i2c0_1>; >> + >> + codec: sgtl5000 at 0a { >> + compatible = "fsl,sgtl5000"; >> + reg = <0x0a>; >> + clocks = <&clks MVF600_CLK_SAI2>; > >The sgtl5000 uses SAI2 clock? [Lu Jingchang-B35083] Yes, the sgtl5000 uses the SAI2 clock on MVF600 Tower board. Thanks! > >> + }; >> +}; > >Is i2c-imx driver working for mvf600 right now? > > >Do we have a QuadSPI driver on mainline kernel? Please only add it when >it's been tested against mainline kernel. [Lu Jingchang-B35083] Sound, I2C, QuadSPI and SAI added in the initial dts have been test locally on the mainline kernel, and the patches will be sent to maillist later. Thanks! ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts support 2013-05-20 5:01 ` Lu Jingchang-B35083 @ 2013-05-20 5:53 ` Shawn Guo 0 siblings, 0 replies; 19+ messages in thread From: Shawn Guo @ 2013-05-20 5:53 UTC (permalink / raw) To: linux-arm-kernel On Mon, May 20, 2013 at 05:01:47AM +0000, Lu Jingchang-B35083 wrote: > [Lu Jingchang-B35083] > Sound, I2C, QuadSPI and SAI added in the initial dts have been test locally on the mainline kernel, and the patches will be sent to maillist later. Thanks! > Please add them after driver patches get accepted by subsystem maintainers. If the DT bindings can not be accepted as it is, we will end up changing the dts files back and forth. Shawn ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2013-05-21 2:17 UTC | newest] Thread overview: 19+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-05-16 6:10 [PATCH v3 0/4] Add initial Freescale Vybrid MVF600 support Jingchang Lu 2013-05-16 6:10 ` [PATCH v3 1/4] ARM: imx: add MVF600 clock support Jingchang Lu 2013-05-16 6:10 ` [PATCH v3 2/4] ARM: imx: add initial support for MVF600 Jingchang Lu 2013-05-16 10:29 ` Arnd Bergmann 2013-05-17 8:57 ` Shawn Guo 2013-05-17 12:29 ` Arnd Bergmann 2013-05-17 12:31 ` Arnd Bergmann 2013-05-17 13:06 ` Shawn Guo 2013-05-17 13:17 ` Arnd Bergmann 2013-05-17 13:54 ` Shawn Guo 2013-05-21 2:17 ` Shawn Guo 2013-05-17 9:08 ` Shawn Guo 2013-05-18 1:27 ` Shawn Guo 2013-05-16 6:10 ` [PATCH v3 3/4] ARM: dts: add SoC level device tree source " Jingchang Lu 2013-05-19 14:14 ` Shawn Guo 2013-05-16 6:10 ` [PATCH v3 4/4] ARM: dts: add initial MVF600 Tower board dts support Jingchang Lu 2013-05-19 15:29 ` Shawn Guo 2013-05-20 5:01 ` Lu Jingchang-B35083 2013-05-20 5:53 ` Shawn Guo
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