Re: [PATCH 1/2] arm64: dts: imx8mq: Correct MIPI CSI clocks

[Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>]

On piątek, 17 kwietnia 2026 13:01:59 czas środkowoeuropejski letni Robby Cai 
wrote:
> CSI capture may intermittently fail due to mismatched clock rates. The
> previous configuration violated the timing requirement stated in the
> i.MX8MQ Reference Manual:
> 
>   "The frequency of clk must be exactly equal to or greater than the RX
>    byte clock coming from the RX DPHY."
> 
> Update the clock configuration to ensure that the CSI core clock rate is
> equal to or greater than the incoming DPHY byte clock. The updated clock
> ratios are consistent with those used in NXP's downstream BSP.

I believe this is a misreading of the docs.

IMX8MQ_CLK_CSIX_PHY_REF refers to the UI pixel clock (clk_ui), not the RX DPHY 
byte clock. All this change would do is to break streaming with more than 100 
Mpixels per second / 1064 Mbps per MIPI lane.

As mentioned in the reference manual:

"The frequency of clk_ui must be such that the data received on the data_out 
output is greater than or equal to the total bandwidth of the physical MIPI 
interface. Clk_ui has no relationship requirement with regards to ‘clk’ other 
than the bandwidth requirement mentioned previously."

> Fixes: bcadd5f66c2a ("arm64: dts: imx8mq: add mipi csi phy and csi bridge
> descriptions") Cc: stable@vger.kernel.org
> Signed-off-by: Robby Cai <robby.cai@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index
> 6a25e219832c..165716d08e64 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1377,7 +1377,7 @@ mipi_csi1: csi@30a70000 {
>  				assigned-clocks = <&clk 
IMX8MQ_CLK_CSI1_CORE>,
>  				    <&clk 
IMX8MQ_CLK_CSI1_PHY_REF>,
>  				    <&clk IMX8MQ_CLK_CSI1_ESC>;
> -				assigned-clock-rates = 
<266000000>, <333000000>, <66000000>;
> +				assigned-clock-rates = 
<133000000>, <100000000>, <66000000>;
>  				assigned-clock-parents = <&clk 
IMX8MQ_SYS1_PLL_266M>,
>  					<&clk 
IMX8MQ_SYS2_PLL_1000M>,
>  					<&clk 
IMX8MQ_SYS1_PLL_800M>;
> @@ -1429,7 +1429,7 @@ mipi_csi2: csi@30b60000 {
>  				assigned-clocks = <&clk 
IMX8MQ_CLK_CSI2_CORE>,
>  				    <&clk 
IMX8MQ_CLK_CSI2_PHY_REF>,
>  				    <&clk IMX8MQ_CLK_CSI2_ESC>;
> -				assigned-clock-rates = 
<266000000>, <333000000>, <66000000>;
> +				assigned-clock-rates = 
<133000000>, <100000000>, <66000000>;
>  				assigned-clock-parents = <&clk 
IMX8MQ_SYS1_PLL_266M>,
>  					<&clk 
IMX8MQ_SYS2_PLL_1000M>,
>  					<&clk 
IMX8MQ_SYS1_PLL_800M>;